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| ElanTMSC520 Microcontroller Register Set Manual Order #22005B (c) 2001 Advanced Micro Devices, Inc. All rights reserved. The contents of this document are provided in connection with Advanced Micro Devices, Inc. ("AMD") products. AMD makes no representations or warranties with respect to the accuracy or completeness of the contents of this publication and reserves the right to make changes to specifications and product descriptions at any time without notice. No license, whether express, implied, arising by estoppel or otherwise, to any intellectual property rights is granted by this publication. Except as set forth in AMD's Standard Terms and Conditions of Sale, AMD assumes no liability whatsoever, and disclaims any express or implied warranty, relating to its products including, but not limited to, the implied warranty of merchantability, fitness for a particular purpose, or infringement of any intellectual property right. AMD's products are not designed, intended, authorized or warranted for use as components in systems intended for surgical implant into the body, or in other applications intended to support or sustain life, or in any other application in which the failure of AMD's product could create a situation where personal injury, death, or severe property or environmental damage may occur. AMD reserves the right to discontinue or make changes to its products at any time without notice. Trademarks AMD, the AMD logo, and combinations thereof, AMDebug, E86, and Elan are trademarks, Am486 and Am5x86 are registered trademarks, and FusionE86 is a service mark of Advanced Micro Devices, Inc. Product names used in this publication are for identification purposes only and may be trademarks of their respective companies. IF YOU HAVE QUESTIONS, WE'RE HERE TO HELP YOU. The AMD customer service network includes U.S. offices, international offices, and a customer training center. Expert technical assistance is available from the AMD worldwide staff of field application engineers and factory support staff to answer E86TM family hardware and software development questions. Frequently accessed numbers are listed below. Additional contact information is listed on the back of this manual. AMD's WWW site lists the latest phone numbers. Technical Support Answers to technical questions are available online, through e-mail, and by telephone. Go to AMD's home page at www.amd.com and follow the Support link for the latest AMD technical support phone numbers, software, and Frequently Asked Questions. For technical support questions on all E86 products, send e-mail to epd.support@amd.com (in the US and Canada) or euro.tech@amd.com (in Europe and the UK). You can also call the AMD Corporate Applications Hotline at: (800) 222-9323 44-(0) 1276-803-299 Toll-free for U.S. and Canada U.K. and Europe hotline WWW Support For specific information on E86 products, access the AMD home page at www.amd.com and follow the Embedded Processors link. These pages provide information on upcoming product releases, overviews of existing products, information on product support and tools, and a list of technical documentation. Support tools include online benchmarking tools and CodeKit software--tested source code example applications. Many of the technical documents are available online in PDF form. Questions, requests, and input concerning AMD's WWW pages can be sent via e-mail to web.feedback@amd.com. Documentation and Literature Support Data books, user's manuals, data sheets, application notes, and product CDs are free with a simple phone call. Internationally, contact your local AMD sales office for product literature. To order literature, go to www.amd.com/support/literature.html or, in the U.S. and Canada, call (800) 222-9323. Third-Party Support AMD FusionE86SM partners provide an array of products designed to meet critical time-to-market needs. Products and solutions available include emulators, hardware and software debuggers, board-level products, and software development tools, among others. The WWW site and the E86TM Family Products Development Tools CD, order #21058, describe these solutions. In addition, mature development tools and applications for the x86 platform are widely available in the general marketplace. ElanTMSC520 Microcontroller Register Set Manual iii iv ElanTMSC520 Microcontroller Register Set Manual TABLE OF CONTENTS PREFACE INTRODUCTION XV ElanTMSC520 Microcontroller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .xv Purpose of this Manual . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .xv Intended Audience . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .xv Overview of this Manual . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .xv Related Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xvi AMD Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xvi Additional Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xvii Documentation Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xviii CONFIGURATION REGISTER OVERVIEW 1-1 1.1 Memory-Mapped Configuration Region (MMCR) Registers. . . . . . . . . . . . 1-1 1.2 Direct-Mapped I/O Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7 1.3 PCI Host Bridge Indexed Configuration Registers . . . . . . . . . . . . . . . . . . 1-10 1.4 RTC and CMOS RAM Indexed Registers. . . . . . . . . . . . . . . . . . . . . . . . . 1-11 SYSTEM ADDRESS MAPPING REGISTERS 2-1 2.1 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 2.2 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 Address Decode Control (ADDDECCTL) . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 Write-Protect Violation Status (WPVSTA) . . . . . . . . . . . . . . . . . . . . . . . . . 2-4 Programmable Address Region 0 (PAR0) . . . . . . . . . . . . . . . . . . . . . . . . . 2-5 Programmable Address Region 1 (PAR1) . . . . . . . . . . . . . . . . . . . . . . . . . 2-5 Programmable Address Region 2 (PAR2) . . . . . . . . . . . . . . . . . . . . . . . . . 2-5 Programmable Address Region 3 (PAR3) . . . . . . . . . . . . . . . . . . . . . . . . . 2-5 Programmable Address Region 4 (PAR4) . . . . . . . . . . . . . . . . . . . . . . . . . 2-5 Programmable Address Region 5 (PAR5) . . . . . . . . . . . . . . . . . . . . . . . . . 2-5 Programmable Address Region 6 (PAR6) . . . . . . . . . . . . . . . . . . . . . . . . . 2-5 Programmable Address Region 7 (PAR7) . . . . . . . . . . . . . . . . . . . . . . . . . 2-5 Programmable Address Region 8 (PAR8) . . . . . . . . . . . . . . . . . . . . . . . . . 2-5 Programmable Address Region 9 (PAR9) . . . . . . . . . . . . . . . . . . . . . . . . . 2-5 Programmable Address Region 10 (PAR10) . . . . . . . . . . . . . . . . . . . . . . . 2-5 Programmable Address Region 11 (PAR11) . . . . . . . . . . . . . . . . . . . . . . . 2-5 Programmable Address Region 12 (PAR12) . . . . . . . . . . . . . . . . . . . . . . . 2-5 Programmable Address Region 13 (PAR13) . . . . . . . . . . . . . . . . . . . . . . . 2-5 Programmable Address Region 14 (PAR14) . . . . . . . . . . . . . . . . . . . . . . . 2-5 Programmable Address Region 15 (PAR15) . . . . . . . . . . . . . . . . . . . . . . . 2-5 Configuration Base Address (CBAR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9 RESET GENERATION REGISTERS 3-1 3.1 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 3.2 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 System Board Information (SYSINFO). . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 Reset Configuration (RESCFG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3 Reset Status (RESSTA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5 SCP Data Port (SCPDATA). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7 SCP Command Port (SCPCMD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8 System Control Port A (SYSCTLA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9 CHAPTER 1 CHAPTER 2 CHAPTER 3 ElanTMSC520 Microcontroller Register Set Manual v Table of Contents CHAPTER 4 Am5X86(R) CPU REGISTERS 4-1 4.1 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 4.2 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 ElanTMSC520 Microcontroller Revision ID (REVID) . . . . . . . . . . . . . . . . . . 4-2 Am5x86(R) CPU Control (CPUCTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3 SYSTEM ARBITRATION REGISTERS 5-1 5.1 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1 5.2 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1 System Arbiter Control (SYSARBCTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2 PCI Bus Arbiter Status (PCIARBSTA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3 System Arbiter Master Enable (SYSARBMENB) . . . . . . . . . . . . . . . . . . . . 5-4 Arbiter Priority Control (ARBPRICTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-6 PCI BUS HOST BRIDGE REGISTERS 6-1 6.1 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1 6.2 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1 Host Bridge Control (HBCTL). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-3 Host Bridge Target Interrupt Control (HBTGTIRQCTL) . . . . . . . . . . . . . . . 6-5 Host Bridge Target Interrupt Status (HBTGTIRQSTA) . . . . . . . . . . . . . . . . 6-7 Host Bridge Master Interrupt Control (HBMSTIRQCTL) . . . . . . . . . . . . . . 6-9 Host Bridge Master Interrupt Status (HBMSTIRQSTA) . . . . . . . . . . . . . . 6-12 Host Bridge Master Interrupt Address (MSTINTADD) . . . . . . . . . . . . . . . 6-14 PCI Configuration Address (PCICFGADR) . . . . . . . . . . . . . . . . . . . . . . . 6-15 PCI Configuration Data (PCICFGDATA) . . . . . . . . . . . . . . . . . . . . . . . . . . 6-17 Device/Vendor ID (PCIDEVID) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-18 Status/Command (PCISTACMD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-19 Class Code/Revision ID (PCICCREVID) . . . . . . . . . . . . . . . . . . . . . . . . . 6-22 Header Type (PCIHEADTYPE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-23 Master Retry Time-Out (PCIMRETRYTO) . . . . . . . . . . . . . . . . . . . . . . . . 6-24 SDRAM CONTROLLER REGISTERS 7-1 7.1 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-1 7.2 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-1 SDRAM Control (DRCCTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-2 SDRAM Timing Control (DRCTMCTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-4 SDRAM Bank Configuration (DRCCFG) . . . . . . . . . . . . . . . . . . . . . . . . . . 7-5 SDRAM Bank 0-3 Ending Address (DRCBENDADR) . . . . . . . . . . . . . . . . 7-7 ECC Control (ECCCTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-9 ECC Status (ECCSTA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-10 ECC Check Bit Position (ECCCKBPOS) . . . . . . . . . . . . . . . . . . . . . . . . . 7-11 ECC Check Code Test (ECCCKTEST) . . . . . . . . . . . . . . . . . . . . . . . . . . 7-12 ECC Single-Bit Error Address (ECCSBADD) . . . . . . . . . . . . . . . . . . . . . . 7-14 ECC Multi-Bit Error Address (ECCMBADD). . . . . . . . . . . . . . . . . . . . . . . 7-15 WRITE BUFFER AND READ BUFFER REGISTER 8-1 8.1 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-1 8.2 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-1 SDRAM Buffer Control (DBCTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-2 ROM/FLASH CONTROLLER REGISTERS 9-1 9.1 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-1 9.2 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-1 BOOTCS Control (BOOTCSCTL). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-2 ROMCS1 Control (ROMCS1CTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-4 ROMCS2 Control (ROMCS2CTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-6 CHAPTER 5 CHAPTER 6 CHAPTER 7 CHAPTER 8 CHAPTER 9 vi ElanTMSC520 Microcontroller Register Set Manual Table of Contents CHAPTER 10 GENERAL-PURPOSE BUS CONTROLLER REGISTERS 10-1 10.1 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-1 10.2 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-1 GP Echo Mode (GPECHO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-2 GP Chip Select Data Width (GPCSDW). . . . . . . . . . . . . . . . . . . . . . . . . . 10-3 GP Chip Select Qualification (GPCSQUAL) . . . . . . . . . . . . . . . . . . . . . . . 10-5 GP Chip Select Recovery Time (GPCSRT) . . . . . . . . . . . . . . . . . . . . . . . 10-7 GP Chip Select Pulse Width (GPCSPW) . . . . . . . . . . . . . . . . . . . . . . . . . 10-8 GP Chip Select Offset (GPCSOFF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-9 GP Read Pulse Width (GPRDW) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-10 GP Read Offset (GPRDOFF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-11 GP Write Pulse Width (GPWRW). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-12 GP Write Offset (GPWROFF). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-13 GPALE Pulse Width (GPALEW) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-14 GPALE Offset (GPALEOFF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-15 CHAPTER 11 GP DMA CONTROLLER REGISTERS 11-1 11.1 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-1 11.2 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-1 GP-DMA Control (GPDMACTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-4 GP-DMA Memory-Mapped I/O (GPDMAMMIO). . . . . . . . . . . . . . . . . . . . 11-5 GP-DMA Resource Channel Map A (GPDMAEXTCHMAPA) . . . . . . . . . 11-6 GP-DMA Resource Channel Map B (GPDMAEXTCHMAPB) . . . . . . . . . 11-8 GP-DMA Channel 0 Extended Page (GPDMAEXTPG0) . . . . . . . . . . . . 11-10 GP-DMA Channel 1 Extended Page (GPDMAEXTPG1) . . . . . . . . . . . . 11-11 GP-DMA Channel 2 Extended Page (GPDMAEXTPG2) . . . . . . . . . . . . 11-12 GP-DMA Channel 3 Extended Page (GPDMAEXTPG3) . . . . . . . . . . . . 11-13 GP-DMA Channel 5 Extended Page (GPDMAEXTPG5) . . . . . . . . . . . . 11-14 GP-DMA Channel 6 Extended Page (GPDMAEXTPG6) . . . . . . . . . . . . 11-15 GP-DMA Channel 7 Extended Page (GPDMAEXTPG7) . . . . . . . . . . . . 11-16 GP-DMA Channel 3 Extended Transfer Count (GPDMAEXTTC3). . . . . 11-17 GP-DMA Channel 5 Extended Transfer Count (GPDMAEXTTC5). . . . . 11-18 GP-DMA Channel 6 Extended Transfer Count (GPDMAEXTTC6). . . . . 11-19 GP-DMA Channel 7 Extended Transfer Count (GPDMAEXTTC7). . . . . 11-20 Buffer Chaining Control (GPDMABCCTL) . . . . . . . . . . . . . . . . . . . . . . . 11-21 Buffer Chaining Status (GPDMABCSTA) . . . . . . . . . . . . . . . . . . . . . . . . 11-22 Buffer Chaining Interrupt Enable (GPDMABSINTENB) . . . . . . . . . . . . . 11-24 Buffer Chaining Valid (GPDMABCVAL) . . . . . . . . . . . . . . . . . . . . . . . . . 11-25 GP-DMA Channel 3 Next Address Low (GPDMANXTADDL3). . . . . . . . 11-26 GP-DMA Channel 3 Next Address High (GPDMANXTADDH3) . . . . . . . 11-27 GP-DMA Channel 5 Next Address Low (GPDMANXTADDL5). . . . . . . . 11-28 GP-DMA Channel 5 Next Address High (GPDMANXTADDH5) . . . . . . . 11-29 GP-DMA Channel 6 Next Address Low (GPDMANXTADDL6). . . . . . . . 11-30 GP-DMA Channel 6 Next Address High (GPDMANXTADDH6) . . . . . . . 11-31 GP-DMA Channel 7 Next Address Low (GPDMANXTADDL7). . . . . . . . 11-32 GP-DMA Channel 7 Next Address High (GPDMANXTADDH7) . . . . . . . 11-33 GP-DMA Channel 3 Next Transfer Count Low (GPDMANXTTCL3) . . . . 11-34 GP-DMA Channel 3 Next Transfer Count High (GPDMANXTTCH3) . . . 11-35 GP-DMA Channel 5 Next Transfer Count Low (GPDMANXTTCL5) . . . . 11-36 GP-DMA Channel 5 Next Transfer Count High (GPDMANXTTCH5) . . . 11-37 GP-DMA Channel 6 Next Transfer Count Low (GPDMANXTTCL6) . . . . 11-38 GP-DMA Channel 6 Next Transfer Count High (GPDMANXTTCH6) . . . 11-39 GP-DMA Channel 7 Next Transfer Count Low (GPDMANXTTCL7) . . . . 11-40 GP-DMA Channel 7 Next Transfer Count High (GPDMANXTTCH7) . . . 11-41 Slave DMA Channel 0 Memory Address (GPDMA0MAR) . . . . . . . . . . . 11-42 Slave DMA Channel 0 Transfer Count (GPDMA0TC) . . . . . . . . . . . . . . 11-43 Slave DMA Channel 1 Memory Address (GPDMA1MAR) . . . . . . . . . . . 11-44 Slave DMA Channel 1 Transfer Count (GPDMA1TC) . . . . . . . . . . . . . . 11-45 Slave DMA Channel 2 Memory Address (GPDMA2MAR) . . . . . . . . . . . 11-46 Slave DMA Channel 2 Transfer Count (GPDMA2TC) . . . . . . . . . . . . . . 11-47 ElanTMSC520 Microcontroller Register Set Manual vii Table of Contents Slave DMA Channel 3 Memory Address (GPDMA3MAR) . . . . . . . . . . . 11-48 Slave DMA Channel 3 Transfer Count (GPDMA3TC) . . . . . . . . . . . . . . 11-49 Slave DMA Channel 0-3 Status (SLDMASTA). . . . . . . . . . . . . . . . . . . . 11-50 Slave DMA Channel 0-3 Control (SLDMACTL) . . . . . . . . . . . . . . . . . . . 11-51 Slave Software DRQ(n) Request (SLDMASWREQ) . . . . . . . . . . . . . . . 11-53 Slave DMA Channel 0-3 Mask (SLDMAMSK) . . . . . . . . . . . . . . . . . . . . 11-54 Slave DMA Channel 0-3 Mode (SLDMAMODE) . . . . . . . . . . . . . . . . . . 11-55 Slave DMA Clear Byte Pointer (SLDMACBP). . . . . . . . . . . . . . . . . . . . . 11-57 Slave DMA Controller Reset (SLDMARST) . . . . . . . . . . . . . . . . . . . . . . 11-58 Slave DMA Controller Temporary (SLDMATMP) . . . . . . . . . . . . . . . . . . 11-59 Slave DMA Mask Reset (SLDMAMSKRST) . . . . . . . . . . . . . . . . . . . . . . 11-60 Slave DMA General Mask (SLDMAGENMSK) . . . . . . . . . . . . . . . . . . . . 11-61 General 0 (GPDMAGR0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-62 Slave DMA Channel 2 Page (GPDMA2PG) . . . . . . . . . . . . . . . . . . . . . . 11-63 Slave DMA Channel 3 Page (GPDMA3PG) . . . . . . . . . . . . . . . . . . . . . . 11-64 Slave DMA Channel 1 Page (GPDMA1PG) . . . . . . . . . . . . . . . . . . . . . . 11-65 General 1 (GPDMAGR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-66 General 2 (GPDMAGR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-67 General 3 (GPDMAGR3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-68 Slave DMA Channel 0 Page (GPDMA0PG) . . . . . . . . . . . . . . . . . . . . . . 11-69 General 4 (GPDMAGR4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-70 Master DMA Channel 6 Page (GPDMA6PG) . . . . . . . . . . . . . . . . . . . . . 11-71 Master DMA Channel 7 Page (GPDMA7PG) . . . . . . . . . . . . . . . . . . . . . 11-72 Master DMA Channel 5 Page (GPDMA5PG) . . . . . . . . . . . . . . . . . . . . . 11-73 General 5 (GPDMAGR5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-74 General 6 (GPDMAGR6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-75 General 7 (GPDMAGR7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-76 General 8 (GPDMAGR8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-77 Master DMA Channel 4 Memory Address (GPDMA4MAR) . . . . . . . . . . 11-78 Master DMA Channel 4 Transfer Count (GPDMA4TC) . . . . . . . . . . . . . 11-79 Master DMA Channel 5 Memory Address (GPDMA5MAR) . . . . . . . . . . 11-80 Master DMA Channel 5 Transfer Count (GPDMA5TC) . . . . . . . . . . . . . 11-81 Master DMA Channel 6 Memory Address (GPDMA6MAR) . . . . . . . . . . 11-82 Master DMA Channel 6 Transfer Count (GPDMA6TC) . . . . . . . . . . . . . 11-83 Master DMA Channel 7 Memory Address (GPDMA7MAR) . . . . . . . . . . 11-84 Master DMA Channel 7 Transfer Count (GPDMA7TC) . . . . . . . . . . . . . 11-85 Master DMA Channel 4-7 Status (MSTDMASTA) . . . . . . . . . . . . . . . . . 11-86 Master DMA Channel 4-7 Control (MSTDMACTL) . . . . . . . . . . . . . . . . 11-87 Master Software DRQ(n) Request (MSTDMASWREQ) . . . . . . . . . . . . . 11-89 Master DMA Channel 4-7 Mask (MSTDMAMSK) . . . . . . . . . . . . . . . . . 11-90 Master DMA Channel 4-7 Mode (MSTDMAMODE) . . . . . . . . . . . . . . . 11-91 Master DMA Clear Byte Pointer (MSTDMACBP) . . . . . . . . . . . . . . . . . . 11-93 Master DMA Controller Reset (MSTDMARST) . . . . . . . . . . . . . . . . . . . 11-94 Master DMA Controller Temporary (MSTDMATMP). . . . . . . . . . . . . . . . 11-95 Master DMA Mask Reset (MSTDMAMSKRST) . . . . . . . . . . . . . . . . . . . 11-96 Master DMA General Mask (MSTDMAGENMSK) . . . . . . . . . . . . . . . . . 11-97 CHAPTER 12 PROGRAMMABLE INTERRUPT CONTROLLER REGISTERS 12-1 12.1 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-1 12.2 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-1 Interrupt Control (PICICR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-4 Master PIC Interrupt Mode (MPICMODE) . . . . . . . . . . . . . . . . . . . . . . . . 12-6 Slave 1 PIC Interrupt Mode (SL1PICMODE) . . . . . . . . . . . . . . . . . . . . . . 12-8 Slave 2 PIC Interrupt Mode (SL2PICMODE) . . . . . . . . . . . . . . . . . . . . . . 12-9 Software Interrupt 16-1 Control (SWINT16_1) . . . . . . . . . . . . . . . . . . . 12-10 Software Interrupt 22-17/NMI Control (SWINT22_17). . . . . . . . . . . . . . 12-13 Interrupt Pin Polarity (INTPINPOL). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-15 PCI Host Bridge Interrupt Mapping (PCIHOSTMAP) . . . . . . . . . . . . . . . 12-17 ECC Interrupt Mapping (ECCMAP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-19 viii ElanTMSC520 Microcontroller Register Set Manual Table of Contents GP Timer 0 Interrupt Mapping (GPTMR0MAP) . . . . . . . . . . . . . . . . . . . 12-21 GP Timer 1 Interrupt Mapping (GPTMR1MAP) . . . . . . . . . . . . . . . . . . . 12-21 GP Timer 2 Interrupt Mapping (GPTMR2MAP) . . . . . . . . . . . . . . . . . . . 12-21 PIT 0 Interrupt Mapping (PIT0MAP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-21 PIT 1 Interrupt Mapping (PIT1MAP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-21 PIT 2 Interrupt Mapping (PIT2MAP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-21 UART 1 Interrupt Mapping (UART1MAP) . . . . . . . . . . . . . . . . . . . . . . . . 12-21 UART 2 Interrupt Mapping (UART2MAP) . . . . . . . . . . . . . . . . . . . . . . . . 12-21 PCI Interrupt A Mapping (PCIINTAMAP) . . . . . . . . . . . . . . . . . . . . . . . . 12-21 PCI Interrupt B Mapping (PCIINTBMAP) . . . . . . . . . . . . . . . . . . . . . . . . 12-21 PCI Interrupt C Mapping (PCIINTCMAP) . . . . . . . . . . . . . . . . . . . . . . . . 12-21 PCI Interrupt D Mapping (PCIINTDMAP) . . . . . . . . . . . . . . . . . . . . . . . . 12-21 DMA Buffer Chaining Interrupt Mapping (DMABCINTMAP). . . . . . . . . . 12-21 SSI Interrupt Mapping (SSIMAP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-21 Watchdog Timer Interrupt Mapping (WDTMAP). . . . . . . . . . . . . . . . . . . 12-21 RTC Interrupt Mapping (RTCMAP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-21 Write-Protect Violation Interrupt Mapping (WPVMAP) . . . . . . . . . . . . . . 12-21 AMDebugTM Technology RX/TX Interrupt Mapping (ICEMAP) . . . . . . . . 12-21 Floating Point Error Interrupt Mapping (FERRMAP) . . . . . . . . . . . . . . . 12-21 GPIRQ0 Interrupt Mapping (GP0IMAP) . . . . . . . . . . . . . . . . . . . . . . . . . 12-21 GPIRQ1 Interrupt Mapping (GP1IMAP) . . . . . . . . . . . . . . . . . . . . . . . . . 12-21 GPIRQ2 Interrupt Mapping (GP2IMAP) . . . . . . . . . . . . . . . . . . . . . . . . . 12-21 GPIRQ3 Interrupt Mapping (GP3IMAP) . . . . . . . . . . . . . . . . . . . . . . . . . 12-21 GPIRQ4 Interrupt Mapping (GP4IMAP) . . . . . . . . . . . . . . . . . . . . . . . . . 12-21 GPIRQ5 Interrupt Mapping (GP5IMAP) . . . . . . . . . . . . . . . . . . . . . . . . . 12-21 GPIRQ6 Interrupt Mapping (GP6IMAP) . . . . . . . . . . . . . . . . . . . . . . . . . 12-21 GPIRQ7 Interrupt Mapping (GP7IMAP) . . . . . . . . . . . . . . . . . . . . . . . . . 12-21 GPIRQ8 Interrupt Mapping (GP8IMAP) . . . . . . . . . . . . . . . . . . . . . . . . . 12-21 GPIRQ9 Interrupt Mapping (GP9IMAP) . . . . . . . . . . . . . . . . . . . . . . . . . 12-21 GPIRQ10 Interrupt Mapping (GP10IMAP) . . . . . . . . . . . . . . . . . . . . . . . 12-21 Master PIC Interrupt Request (MPICIR). . . . . . . . . . . . . . . . . . . . . . . . . 12-24 Master PIC In-Service (MPICISR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-25 Master PIC Initialization Control Word 1 (MPICICW1) . . . . . . . . . . . . . . 12-26 Master PIC Operation Control Word 2 (MPICOCW2) . . . . . . . . . . . . . . 12-28 Master PIC Operation Control Word 3 (MPICOCW3) . . . . . . . . . . . . . . 12-30 Master PIC Initialization Control Word 2 (MPICICW2) . . . . . . . . . . . . . . 12-32 Master PIC Initialization Control Word 3 (MPICICW3) . . . . . . . . . . . . . . 12-33 Master PIC Initialization Control Word 4 (MPICICW4) . . . . . . . . . . . . . . 12-35 Master PIC Interrupt Mask (MPICINTMSK) . . . . . . . . . . . . . . . . . . . . . . 12-36 Slave 2 PIC Interrupt Request (S2PICIR) . . . . . . . . . . . . . . . . . . . . . . . 12-37 Slave 2 PIC In-Service (S2PICISR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-38 Slave 2 PIC Initialization Control Word 1 (S2PICICW1) . . . . . . . . . . . . . 12-39 Slave 2 PIC Operation Control Word 2 (S2PICOCW2) . . . . . . . . . . . . . 12-41 Slave 2 PIC Operation Control Word 3 (S2PICOCW3) . . . . . . . . . . . . . 12-43 Slave 2 PIC Initialization Control Word 2 (S2PICICW2) . . . . . . . . . . . . . 12-45 Slave 2 PIC Initialization Control Word 3 (S2PICICW3) . . . . . . . . . . . . . 12-46 Slave 2 PIC Initialization Control Word 4 (S2PICICW4) . . . . . . . . . . . . . 12-47 Slave 2 PIC Interrupt Mask (S2PICINTMSK) . . . . . . . . . . . . . . . . . . . . . 12-48 Slave 1 PIC Interrupt Request (S1PICIR) . . . . . . . . . . . . . . . . . . . . . . . 12-49 Slave 1 PIC In-Service (S1PICISR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-50 Slave 1 PIC Initialization Control Word 1 (S1PICICW1) . . . . . . . . . . . . . 12-51 Slave 1 PIC Operation Control Word 2 (S1PICOCW2) . . . . . . . . . . . . . 12-53 Slave 1 PIC Operation Control Word 3 (S1PICOCW3) . . . . . . . . . . . . . 12-55 Slave 1 PIC Initialization Control Word 2 (S1PICICW2) . . . . . . . . . . . . . 12-57 Slave 1 PIC Initialization Control Word 3 (S1PICICW3) . . . . . . . . . . . . . 12-58 Slave 1 PIC Initialization Control Word 4 (S1PICICW4) . . . . . . . . . . . . . 12-59 Slave 1 PIC Interrupt Mask (S1PICINTMSK) . . . . . . . . . . . . . . . . . . . . . 12-60 Floating Point Error Interrupt Clear (FPUERRCLR) . . . . . . . . . . . . . . . . 12-61 ElanTMSC520 Microcontroller Register Set Manual ix Table of Contents CHAPTER 13 PROGRAMMABLE INTERVAL TIMER REGISTERS 13-1 13.1 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-1 13.2 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-1 PIT Channel 0 Count (PIT0CNT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-2 PIT Channel 1 Count (PIT1CNT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-3 PIT Channel 2 Count (PIT2CNT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-4 PIT 0 Status (PIT0STA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-5 PIT 1 Status (PIT1STA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-5 PIT 2 Status (PIT2STA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-5 PIT Mode Control (PITMODECTL). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-7 PIT Counter Latch Command (PITCNTLAT) . . . . . . . . . . . . . . . . . . . . . 13-10 PIT Read-Back Command (PITRDBACK) . . . . . . . . . . . . . . . . . . . . . . . 13-11 System Control Port B (SYSCTLB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-13 CHAPTER 14 GENERAL-PURPOSE TIMER REGISTERS 14-1 14.1 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-1 14.2 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-1 GP Timers Status (GPTMRSTA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-2 GP Timer 0 Mode/Control (GPTMR0CTL) . . . . . . . . . . . . . . . . . . . . . . . . 14-3 GP Timer 0 Count (GPTMR0CNT). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-6 GP Timer 0 Maxcount Compare A (GPTMR0MAXCMPA) . . . . . . . . . . . . 14-7 GP Timer 0 Maxcount Compare B (GPTMR0MAXCMPB). . . . . . . . . . . . 14-8 GP Timer 1 Mode/Control (GPTMR1CTL) . . . . . . . . . . . . . . . . . . . . . . . . 14-9 GP Timer 1 Count (GPTMR1CNT). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-12 GP Timer 1 Maxcount Compare A (GPTMR1MAXCMPA) . . . . . . . . . . . 14-13 GP Timer 1 Maxcount Compare B (GPTMR1MAXCMPB). . . . . . . . . . . 14-14 GP Timer 2 Mode/Control (GPTMR2CTL) . . . . . . . . . . . . . . . . . . . . . . . 14-15 GP Timer 2 Count (GPTMR2CNT). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-17 GP Timer 2 Maxcount Compare A (GPTMR2MAXCMPA) . . . . . . . . . . . 14-18 CHAPTER 15 SOFTWARE TIMER REGISTERS 15-1 15.1 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-1 15.2 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-1 Software Timer Millisecond Count (SWTMRMILLI) . . . . . . . . . . . . . . . . . 15-2 Software Timer Microsecond Count (SWTMRMICRO) . . . . . . . . . . . . . . 15-3 Software Timer Configuration (SWTMRCFG) . . . . . . . . . . . . . . . . . . . . . 15-4 CHAPTER 16 WATCHDOG TIMER REGISTERS 16-1 16.1 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-1 16.2 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-1 Watchdog Timer Control (WDTMRCTL). . . . . . . . . . . . . . . . . . . . . . . . . . 16-2 Watchdog Timer Count Low (WDTMRCNTL). . . . . . . . . . . . . . . . . . . . . . 16-4 Watchdog Timer Count High (WDTMRCNTH) . . . . . . . . . . . . . . . . . . . . . 16-5 x ElanTMSC520 Microcontroller Register Set Manual Table of Contents CHAPTER 17 REAL-TIME CLOCK REGISTERS 17-1 17.1 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-1 17.2 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-1 RTC/CMOS RAM Index (RTCIDX) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-2 RTC/CMOS RAM Data Port (RTCDATA) . . . . . . . . . . . . . . . . . . . . . . . . . 17-3 RTC Current Second (RTCCURSEC) . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-4 RTC Alarm Second (RTCALMSEC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-5 RTC Current Minute (RTCCURMIN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-6 RTC Alarm Minute (RTCALMMIN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-7 RTC Current Hour (RTCCURHR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-8 RTC Alarm Hour (RTCALMHR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-9 RTC Current Day of the Week (RTCCURDOW). . . . . . . . . . . . . . . . . . . 17-10 RTC Current Day of the Month (RTCCURDOM) . . . . . . . . . . . . . . . . . . 17-11 RTC Current Month (RTCCURMON) . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-12 RTC Current Year (RTCCURYR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-13 RTC Control A (RTCCTLA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-14 RTC Control B (RTCCTLB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-16 RTC Status C (RTCSTAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-18 RTC Status D (RTCSTAD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-20 General-Purpose CMOS RAM (114 bytes) (RTCCMOS) . . . . . . . . . . . . 17-21 CHAPTER 18 UART SERIAL PORT REGISTERS 18-1 18.1 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-1 18.2 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-1 UART 1 General Control (UART1CTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-3 UART 2 General Control (UART2CTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-3 UART 1 General Status (UART1STA) . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-4 UART 2 General Status (UART2STA) . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-4 UART 1 FIFO Control Shadow (UART1FCRSHAD) . . . . . . . . . . . . . . . . . 18-5 UART 2 FIFO Control Shadow (UART2FCRSHAD) . . . . . . . . . . . . . . . . . 18-5 UART 2 Transmit Holding (UART2THR) . . . . . . . . . . . . . . . . . . . . . . . . . . 18-7 UART 1 Transmit Holding (UART1THR) . . . . . . . . . . . . . . . . . . . . . . . . . . 18-7 UART 2 Receive Buffer (UART2RBR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-8 UART 1 Receive Buffer (UART1RBR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-8 UART 2 Baud Clock Divisor Latch LSB (UART2BCDL) . . . . . . . . . . . . . . 18-9 UART 1 Baud Clock Divisor Latch LSB (UART1BCDL) . . . . . . . . . . . . . . 18-9 UART 2 Baud Clock Divisor Latch MSB (UART2BCDH) . . . . . . . . . . . . 18-10 UART 1 Baud Clock Divisor Latch MSB (UART1BCDH) . . . . . . . . . . . . 18-10 UART 2 Interrupt Enable (UART2INTENB) . . . . . . . . . . . . . . . . . . . . . . 18-11 UART 1 Interrupt Enable (UART1INTENB) . . . . . . . . . . . . . . . . . . . . . . 18-11 UART 2 Interrupt ID (UART2INTID) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-12 UART 1 Interrupt ID (UART1INTID) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-12 UART 2 FIFO Control (UART2FCR). . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-15 UART 1 FIFO Control (UART1FCR). . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-15 UART 2 Line Control (UART2LCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-17 UART 1 Line Control (UART1LCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-17 UART 2 Modem Control (UART2MCR) . . . . . . . . . . . . . . . . . . . . . . . . . 18-19 UART 1 Modem Control (UART1MCR) . . . . . . . . . . . . . . . . . . . . . . . . . 18-19 UART 2 Line Status (UART2LSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-21 UART 1 Line Status (UART1LSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-21 UART 2 Modem Status (UART2MSR) . . . . . . . . . . . . . . . . . . . . . . . . . . 18-23 UART 1 Modem Status (UART1MSR) . . . . . . . . . . . . . . . . . . . . . . . . . . 18-23 UART 2 Scratch Pad (UART2SCRATCH). . . . . . . . . . . . . . . . . . . . . . . . 18-25 UART 1 Scratch Pad (UART1SCRATCH). . . . . . . . . . . . . . . . . . . . . . . . 18-25 ElanTMSC520 Microcontroller Register Set Manual xi Table of Contents CHAPTER 19 SYNCHRONOUS SERIAL INTERFACE REGISTERS 19-1 19.1 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-1 19.2 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-1 SSI Control (SSICTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-2 SSI Transmit (SSIXMIT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-4 SSI Command (SSICMD). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-5 SSI Status (SSISTA). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-6 SSI Receive (SSIRCV) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-7 CHAPTER 20 PROGRAMMABLE INPUT/OUTPUT REGISTERS 20-1 20.1 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-1 20.2 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-1 PIO15-PIO0 Pin Function Select (PIOPFS15_0) . . . . . . . . . . . . . . . . . . 20-3 PIO31-PIO16 Pin Function Select (PIOPFS31_16) . . . . . . . . . . . . . . . . 20-5 Chip Select Pin Function Select (CSPFS) . . . . . . . . . . . . . . . . . . . . . . . . 20-7 Clock Select (CLKSEL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-9 Drive Strength Control (DSCTL). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-10 PIO15-PIO0 Direction (PIODIR15_0) . . . . . . . . . . . . . . . . . . . . . . . . . . 20-12 PIO31-PIO16 Direction (PIODIR31_16) . . . . . . . . . . . . . . . . . . . . . . . . 20-14 PIO15-PIO0 Data (PIODATA15_0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-16 PIO31-PIO16 Data (PIODATA31_16) . . . . . . . . . . . . . . . . . . . . . . . . . . 20-18 PIO15-PIO0 Set (PIOSET15_0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-20 PIO31-PIO16 Set (PIOSET31_16) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-22 PIO15-PIO0 Clear (PIOCLR15_0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-24 PIO31-PIO16 Clear (PIOCLR31_16). . . . . . . . . . . . . . . . . . . . . . . . . . . 20-26 INDEX Index-1 xii ElanTMSC520 Microcontroller Register Set Manual Table of Contents LIST OF FIGURES Figure 7-1 Examples of Bank Ending Address Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-8 Figure 7-2 ECC Check Bit and Data Bit Positions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-11 Figure 10-1 GP Bus Signal Timing Adjustment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-7 LIST OF TABLES Table 0-1 Documentation Notation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xviii Table 1-1 Memory-Mapped Configuration Region (MMCR) Registers (By Offset) . . . . . . . . . . . . . 1-2 Table 1-2 Direct-Mapped I/O Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7 Table 1-3 PCI Indexed Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-11 Table 1-4 Real-Time Clock Indexed Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-11 Table 2-1 System Address Mapping MMCR Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 Table 2-2 System Address Mapping Direct-Mapped Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 Table 3-1 Reset Generation MMCR Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 Table 3-2 Reset Generation Direct-Mapped Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 Table 3-3 Microcontroller Reset Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6 Table 4-1 Am5x86(R) CPU MMCR Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 Table 5-1 System Arbiter MMCR Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1 Table 6-1 PCI Bus Host Bridge MMCR Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1 Table 6-2 PCI Bus Host Bridge Direct-Mapped Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-2 Table 6-3 PCI Bus Host Bridge Indexed Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-2 Table 7-1 SDRAM Controller MMCR Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-1 Table 7-2 Example ECC Check Codes and Associated Data. . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-13 Table 8-1 Write Buffer and Read Buffer MMCR Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-1 Table 9-1 ROM Controller MMCR Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-1 Table 10-1 GP Bus MMCR Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-1 Table 10-2 GP Bus Echo Mode Minimum Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-2 Table 11-1 GP-DMA MMCR Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-1 Table 11-2 GP-DMA Direct-Mapped Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-2 Table 12-1 Programmable Interrupt Controller MMCR Registers . . . . . . . . . . . . . . . . . . . . . . . . . . 12-1 Table 12-2 Programmable Interrupt Controller Direct-Mapped Registers . . . . . . . . . . . . . . . . . . . . 12-2 Table 12-3 Master PIC I/O Port 0020h Access Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-27 Table 12-4 Master PIC I/O Port 0020h Access Summary (Same as Table 12-3) . . . . . . . . . . . . . 12-29 Table 12-5 Master PIC I/O Port 0020h Access Summary (Same as Table 12-3) . . . . . . . . . . . . . 12-31 Table 12-6 Slave 2 PIC I/O Port 0024h Access Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-40 Table 12-7 Slave 2 PIC I/O Port 0024h Access Summary (Same as Table 12-6) . . . . . . . . . . . . 12-42 Table 12-8 Slave 2 PIC I/O Port 0024h Access Summary (Same as Table 12-6) . . . . . . . . . . . . 12-44 Table 12-9 Slave 1 PIC I/O Port 00A0h Access Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-52 Table 12-10Slave 1 PIC I/O Port 00A0h Access Summary (Same as Table 12-9) . . . . . . . . . . . . 12-54 Table 12-11Slave 1 PIC I/O Port 00A0h Access Summary (Same as Table 12-9) . . . . . . . . . . . . 12-56 Table 13-1 Programmable Interval Timer Direct-Mapped Registers . . . . . . . . . . . . . . . . . . . . . . . . 13-1 Table 13-2 PIT Counter Mode Settings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-9 Table 14-1 General-Purpose Timer MMCR Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-1 Table 15-1 Software Timer MMCR Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-1 Table 16-1 Watchdog Timer MMCR Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-1 Table 16-2 Watchdog Timer Exponent Selections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-3 Table 17-1 Real-Time Clock Direct-Mapped Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-1 Table 17-2 Real-Time Clock Indexed Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-1 Table 18-1 UART MMCR Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-1 Table 18-2 UART Direct-Mapped Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-1 Table 18-3 Baud Rates, Divisors, and Clock Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-9 Table 18-4 UART Interrupt Identification and Priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-13 Table 18-5 UART Interrupt Programming Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-14 Table 19-1 SSI MMCR Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-1 Table 19-2 SSI Clock Speed Selections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-2 Table 20-1 Programmable I/O MMCR Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-1 Table 20-2 PIO Register Programming Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-2 ElanTMSC520 Microcontroller Register Set Manual xiii Table of Contents xiv ElanTMSC520 Microcontroller Register Set Manual PREFACE INTRODUCTION ELANTMSC520 MICROCONTROLLER The ElanTMSC520 microcontroller is a full-featured microcontroller developed for the general embedded market. The ELANSC520 microcontroller combines a 32-bit, low-voltage Am5x86(R) CPU with a complete set of integrated peripherals suitable for both real-time and PC/AT-compatible embedded applications. PURPOSE OF THIS MANUAL This manual includes in reference format the complete set of registers required to configure the ELANSC520 microcontroller and control its peripherals. This manual does not document the Am5x86 processor registers. Intended Audience This reference manual is intended primarily for programmers who are developing code for the ELANSC520 microcontroller. Computer software and hardware architects and system engineers who are designing or are considering designing systems based on this microcontroller may also be interested in the information contained in this document. For more information on programming this microcontroller, see the ElanTMSC520 Microcontroller User's Manual, order #22004. Overview of this Manual The manual is organized into the following chapters: s Chapter 1 contains an overview of all the microcontroller's configuration registers. s Chapter 2 describes the system address mapping registers. s Chapter 3 describes the reset generation registers. s Chapter 4 describes the Am5x86 CPU registers. s Chapter 5 describes the system arbitration registers. s Chapter 6 describes the PCI host bridge registers. s Chapter 7 describes the synchronous DRAM (SDRAM) controller registers. s Chapter 8 describes the write buffer and read buffer register. s Chapter 9 describes the ROM/Flash memory controller registers. s Chapter 10 describes the general-purpose (GP) bus controller registers. s Chapter 11 describes the GP bus DMA controller registers. s Chapter 12 describes the programmable interrupt controller (PIC) registers. s Chapter 13 describes the programmable interval timer (PIT) registers. s Chapter 14 describes the general-purpose (GP) timer registers. s Chapter 15 describes the software timer registers. s Chapter 16 describes the watchdog timer (WDT) registers. s Chapter 17 describes the real-time clock (RTC) registers. ElanTMSC520 Microcontroller Register Set Manual xv Introduction s Chapter 18 describes the UART registers. s Chapter 19 describes the synchronous serial interface (SSI) registers. s Chapter 20 describes the programmable I/O (PIO) registers. s The Index lists all registers and bits alphabetically by name and mnemonic. Each chapter describes the function's memory-mapped configuration region (MMCR) registers first, followed by direct-mapped and then indexed register descriptions, if any. Within each chapter, the registers of each type are listed in ascending hexadecimal order unless descriptions for identical registers (for example, direct-mapped UART registers) are combined. RELATED DOCUMENTS The following documents contain additional information that will be useful in designing an embedded application based on the ELANSC520 microcontroller. AMD Documentation In addition to this manual, the documentation set for the ELANSC520 microcontroller includes the following documents: s ElanTMSC520 Microcontroller User's Manual, order #22004, provides a functional description of the microcontroller for both hardware and software designers. s ElanTMSC520 Microcontroller Data Sheet, order #22003, includes complete pin lists, pin state tables, timing and thermal characteristics, and package dimensions for the ELANSC520 microcontroller. Other information of interest: s The Am486(R) Microprocessor Software User's Manual, order #18497, includes the complete instruction set for the integrated Am5x86 CPU. s Am5x86(R) Microprocessor Family Data Sheet, order #19751 s Am486(R)DX/DX2 Microprocessor Hardware Reference Manual, order #17965 s E86TM Family Products and Development Tools CD, order #21058, provides a singlesource multimedia tool for customer evaluation of AMD products, as well as FusionE86 partner tools and technologies that support the E86 family. Technical documentation is included on the CD in PDF format. To order literature, contact the nearest AMD sales office or call the literature center at one of the numbers listed on the back cover of this manual. In addition, all these documents are available in PDF form on the AMD web site. To access the AMD home page, go to www.amd.com. Then follow the Embedded Processor link for information about AMD's E86 family of microcontrollers. xvi ElanTMSC520 Microcontroller Register Set Manual Introduction Additional Information The following non-AMD documents and sources provide additional information that may be of interest to ELANSC520 microcontroller users: s PCI Local Bus Specification, Revision 2.2, December 18, 1998, PCI Special Interest Group, 800-433-5177 (US), 503-693-6360 (International), www.pcisig.com. s IEEE Std 1149.1-1990 Standard Test Access Port and Boundary-Scan Architecture, (order #SH16626-NYF), Institute of Electrical and Electronic Engineers, Inc., 800-6784333, www.ieee.org. s PCI System Architecture, Mindshare, Inc., Reading, MA: Addison-Wesley, 1995, ISBN 0-201-40993-3. s ISA System Architecture, Mindshare, Inc., Reading, MA: Addison-Wesley, 1995, ISBN 0-201-40996-8. s 80486 System Architecture, Mindshare, Inc., Reading, MA: Addison-Wesley, 1995, ISBN 0-201-40994-1 s The Indispensable PC Hardware Book, Hans-Peter Messmer, Wokingham, England: Addison-Wesley, 1995, ISBN 0-201-87697-3. ElanTMSC520 Microcontroller Register Set Manual xvii Introduction DOCUMENTATION CONVENTIONS Table 0-1 lists the documentation conventions used throughout this manual. Table 0-1 Documentation Notation Notation Reset Default Values Default 0 1 x ? Read/Write Attributes R The bit field is read-only. A write to the register at this bit field has no effect. The contents may or may not be changed by hardware. The bit field is write-only. Reading this register at this bit field does not return a meaningful value and has no side effects. The bit field is read/write. Reading the register at this bit field always returns the last value written. Reads have no side effects. The bit field is read/write with conditions. The "!" indicates that there are side effects to using this bit. For example, reading a bit or register might not always return the last value written. Note that both reads and writes can have side effects. If you see a "!", be sure to read the bit description and programming notes. The bit field is reserved for internal test/debug or future expansion. This bit field should be written to 0 for normal system operation. This bit field always returns 0 when read. The bit field is reserved for compatibility purposes. For example, the bit field might be ignored during writes to maintain software compatibility. If you see a "!", be sure to read the bit description and programming notes. Value after a system reset Low Active or High No value is guaranteed Determined by sources external to the ELANSC520 microcontroller Meaning W R/W R/W! RSV RSV! Reference Notation MMCR offset 00h PCI index 00h Port 00h RTC index 00h ELANSC520 microcontroller Memory-Mapped Configuration Region (MMCR) offset register 00h PCI indexed register 00h Direct-mapped I/O register 00h RTC and configuration RAM indexed register 00h xviii ElanTMSC520 Microcontroller Register Set Manual Introduction Table 0-1 Documentation Notation (Continued) Notation Pin Naming {} [] ROMCS1 GPRESET ads, hold ROMCS2-ROMCS1 ROMCSx Numbers b d h x in register address Binary number Decimal number Decimal is the default radix Hexadecimal number Any of several legal values; e.g., using 0xF8h for the UART Transmit Holding register is either 02F8h or 03F8h, depending on the UART The bit field that consists of bits X through Y. Example: The SB_ADDR[23-16] bit field. Refers to the system clock frequency being used. This can be either 33.000 MHz or 33.333 MHz. See the ElanTMSC520 Microcontroller User's Manual, order #22004, for more information about clock generation. Pin function during hardware reset Alternative pin function selected by software configuration An overbar indicates that the signal assumes the logic Low state when asserted. The absence of an overbar indicates that the signal assumes the logic High state when asserted. A signal name in all lowercase indicates an internal signal. Two ROM chip select signals Any of the two ROM chip select signals Meaning [X-Y] 33 MHz General field can will Set the ENB bit. Bit field in a register (one or more consecutive and related bits) It is possible to perform an action if properly configured A certain action is going to occur Write the ENB bit to 1. Note: The bit referred to is either in the register being described, or the register is referred to explicitly in the surrounding text. Change the ENB bit to 0. Usually a bit is cleared by writing a 0 to it; however, some bits are cleared by writing a 1. Context-sensitive. Can refer either to resetting the bit to its default value or to clearing the bit. Clear the ENB bit. Reset the ENB bit. ElanTMSC520 Microcontroller Register Set Manual xix Introduction xx ElanTMSC520 Microcontroller Register Set Manual CHAPTER 1 CONFIGURATION REGISTER OVERVIEW The ElanTMSC520 microcontroller has four different types of configuration registers: s Memory-Mapped Configuration Region (MMCR) Registers--These are memorymapped peripherals and configuration registers that are specific to the ELANSC520 microcontroller's control and status functions, such as the SDRAM and GP bus controllers. These registers are 8-bits, 16-bits, or 32-bits wide and reside in memory space. s Direct-Mapped Registers--These include the Configuration Base Address (CBAR) register, the PCI Configuration Address and Data (PCICFGADR and PCICFGDATA) registers, and PC/AT-compatible peripherals. All direct-mapped I/O registers reside in fixed I/O space. The CBAR, PCICFGADR, and PCICFGDATA registers are 32 bits wide. All other direct-mapped peripheral configuration registers are 8 bits wide. s PCI Host Bridge Indexed Configuration Registers--These registers are located in the PCI bus configuration space, which is defined in the PCI Local Bus Specification, Revision 2.2, to be accessed through two 32-bit I/O locations at 0CF8h (index) and 0CFCh (data). s RTC Indexed Registers--These registers are located in the PC/AT-compatible realtime clock (RTC) configuration space, which is accessed using I/O ports 0070h (index) and 0071h (data). Register descriptions are organized within this manual by function, e.g., GP bus, SDRAM, or UART. Each function's chapter describes the MMCR registers first, followed by directmapped, and then indexed register descriptions, if any. In each chapter, registers of each type are listed in ascending hexadecimal order unless descriptions for identical registers (for example, direct-mapped UART registers) are combined. The remainder of this chapter presents an overview of the registers by type. 1.1 MEMORY-MAPPED CONFIGURATION REGION (MMCR) REGISTERS The ELANSC520 microcontroller's memory-mapped configuration region (MMCR) contains all internal peripheral control and configuration registers that are not defined as directmapped I/O, PCI indexed, or RTC indexed registers. After reset, the MMCR registers are located in the 4-Kbyte region in memory address space from FFFEF000-FFFEFFFFh. The MMCR registers can be aliased to any 4-Kbyte region in the lower 1-Gbyte address space (00000000h-1FFFFFFh) via the I/O-mapped CBAR register (see page 2-9). The MMCR is available at its original location in high memory even if it is aliased via the CBAR register. See the memory and I/O space chapter in the ElanTMSC520 Microcontroller User's Manual, order #22004, for more detail. Table 1-1 on page 1-2 lists all the MMCR registers included in the ELANSC520 microcontroller. ElanTMSC520 Microcontroller Register Set Manual 1-1 Configuration Register Overview Table 1-1 Memory-Mapped Configuration Region (MMCR) Registers (By Offset) Mnemonic REVID CPUCTL DRCCTL DRCTMCTL DRCCFG DRCBENDADR ECCCTL ECCSTA ECCCKBPOS ECCCKTEST ECCSBADD ECCMBADD DBCTL BOOTCSCTL ROMCS1CTL ROMCS2CTL HBCTL HBTGTIRQCTL HBTGTIRQSTA HBMSTIRQCTL HBMSTIRQSTA MSTINTADD SYSARBCTL PCIARBSTA SYSARBMENB ARBPRICTL MMCR Offset Page Number 00-02h 00h 02h 10-28h 10h 12h 14h 18h 20h 21h 22h 23h 24h 28h 40h 40h 50-56h 50h 54h 56h 60-6Ch 60h 62h 64h 66h 68h 6Ch 70-74h 70h 71h 72h 74h page 5-2 page 5-3 page 5-4 page 5-6 page 6-3 page 6-5 page 6-7 page 6-9 page 6-12 page 6-14 page 9-2 page 9-4 page 9-6 page 8-2 page 7-4 page 7-4 page 7-5 page 7-7 page 7-9 page 7-10 page 7-11 page 7-12 page 7-14 page 7-15 page 4-2 page 4-3 Register Name CPU ELANSC520 Microcontroller Revision ID Am5x86(R) CPU Control SDRAM Controller SDRAM Control SDRAM Timing Control SDRAM Bank Configuration SDRAM Bank 0-3 Ending Address ECC Control ECC Status ECC Check Bit Position ECC Check Code Test ECC Single-Bit Error Address ECC Multi-Bit Error Address SDRAM Buffer SDRAM Buffer Control ROM/Flash Controller BOOTCS Control ROMCS1 Control ROMCS2 Control PCI Bus Host Bridge Host Bridge Control Host Bridge Target Interrupt Control Host Bridge Target Interrupt Status Host Bridge Master Interrupt Control Host Bridge Master Interrupt Status Host Bridge Master Interrupt Address System Arbitration System Arbiter Control PCI Bus Arbiter Status System Arbiter Master Enable Arbiter Priority Control 1-2 ElanTMSC520 Microcontroller Register Set Manual Configuration Register Overview Table 1-1 Memory-Mapped Configuration Region (MMCR) Registers (By Offset) (Continued) Mnemonic ADDDECCTL WPVSTA PAR0 PAR1 PAR2 PAR3 PAR4 PAR5 PAR6 PAR7 PAR8 PAR9 PAR10 PAR11 PAR12 PAR13 PAR14 PAR15 GPECHO GPCSDW GPCSQUAL GPCSRT GPCSPW GPCSOFF GPRDW GPRDOFF GPWRW GPWROFF GPALEW GPALEOFF MMCR Offset Page Number 80-C4h 80h 82h 88h 8Ch 90h 94h 98h 9Ch A0h A4h A8h ACh B0h B4h B8h BCh C0h C4h C00-C10h C00h C01h C02h C08h C09h C0Ah C0Bh C0Ch C0Dh C0Eh C0Fh C10h page 10-2 page 10-3 page 10-5 page 10-7 page 10-8 page 10-9 page 10-10 page 10-11 page 10-12 page 10-13 page 10-14 page 10-15 page 2-2 page 2-4 page 2-5 page 2-5 page 2-5 page 2-5 page 2-5 page 2-5 page 2-5 page 2-5 page 2-5 page 2-5 page 2-5 page 2-5 page 2-5 page 2-5 page 2-5 page 2-5 Register Name System Address Mapping Address Decode Control Write-Protect Violation Status Programmable Address Region 0 Programmable Address Region 1 Programmable Address Region 2 Programmable Address Region 3 Programmable Address Region 4 Programmable Address Region 5 Programmable Address Region 6 Programmable Address Region 7 Programmable Address Region 8 Programmable Address Region 9 Programmable Address Region 10 Programmable Address Region 11 Programmable Address Region 12 Programmable Address Region 13 Programmable Address Region 14 Programmable Address Region 15 GP Bus Controller GP Echo Mode GP Chip Select Data Width GP Chip Select Qualification GP Chip Select Recovery Time GP Chip Select Pulse Width GP Chip Select Offset GP Read Pulse Width GP Read Offset GP Write Pulse Width GP Write Offset GPALE Pulse Width GPALE Offset ElanTMSC520 Microcontroller Register Set Manual 1-3 Configuration Register Overview Table 1-1 Memory-Mapped Configuration Region (MMCR) Registers (By Offset) (Continued) Mnemonic PIOPFS15_0 PIOPFS31_16 CSPFS CLKSEL DSCTL PIODIR15_0 PIODIR31_16 PIODATA15_0 PIODATA31_16 PIOSET15_0 PIOSET31_16 PIOCLR15_0 PIOCLR31_16 SWTMRMILLI SWTMRMICRO SWTMRCFG GPTMRSTA GPTMR0CTL GPTMR0CNT GPTMR0MAXCMPA GPTMR0MAXCMPB GPTMR1CTL GPTMR1CNT GPTMR1MAXCMPA GPTMR1MAXCMPB GPTMR2CTL GPTMR2CNT GPTMR2MAXCMPA WDTMRCTL WDTMRCNTL WDTMRCNTH -- MMCR Offset Page Number C20-C3Ah C20h C22h C24h C26h C28h C2Ah C2Ch C30h C32h C34h C36h C38h C3Ah C60-C62h C60h C62h C64h C70-C8Eh C70h C72h C74h C76h C78h C7Ah C7Ch C7Eh C80h C82h C84h C8Eh CB0-CB6h CB0h CB2h CB4h CB6h page 16-2 page 16-4 page 16-5 -- page 14-2 page 14-3 page 14-6 page 14-7 page 14-8 page 14-9 page 14-12 page 14-13 page 14-14 page 14-15 page 14-17 page 14-18 page 15-2 page 15-3 page 15-4 page 20-3 page 20-5 page 20-7 page 20-9 page 20-10 page 20-12 page 20-14 page 20-16 page 20-18 page 20-20 page 20-22 page 20-24 page 20-26 Register Name Programmable Input/Output PIO15-PIO0 Pin Function Select PIO31-PIO16 Pin Function Select Chip Select Pin Function Select Clock Select Drive Strength Control PIO15-PIO0 Direction PIO31-PIO16 Direction PIO15-PIO0 Data PIO31-PIO16 Data PIO15-PIO0 Set PIO31-PIO16 Set PIO15-PIO0 Clear PIO31-PIO16 Clear Software Timer Software Timer Millisecond Count Software Timer Microsecond Count Software Timer Configuration General-Purpose Timers GP Timers Status GP Timer 0 Mode/Control GP Timer 0 Count GP Timer 0 Maxcount Compare A GP Timer 0 Maxcount Compare B GP Timer 1 Mode/Control GP Timer 1 Count GP Timer 1 Maxcount Compare A GP Timer 1 Maxcount Compare B GP Timer 2 Mode/Control GP Timer 2 Count GP Timer 2 Maxcount Compare A Watchdog Timer Watchdog Timer Control Watchdog Timer Count Low Watchdog Timer Count High Reserved 1-4 ElanTMSC520 Microcontroller Register Set Manual Configuration Register Overview Table 1-1 Memory-Mapped Configuration Region (MMCR) Registers (By Offset) (Continued) Mnemonic UART1CTL UART1STA UART1FCRSHAD UART2CTL UART2STA UART2FCRSHAD SSICTL SSIXMIT SSICMD SSISTA SSIRCV PICICR MPICMODE SL1PICMODE SL2PICMODE SWINT16_1 SWINT22_17 INTPINPOL PCIHOSTMAP ECCMAP GPTMR0MAP GPTMR1MAP GPTMR2MAP PIT0MAP PIT1MAP PIT2MAP UART1MAP UART2MAP PCIINTAMAP PCIINTBMAP PCIINTCMAP PCIINTDMAP DMABCINTMAP SSIMAP WDTMAP RTCMAP WPVMAP ICEMAP MMCR Offset Page Number CC0-CC6h CC0h CC1h CC2h CC4h CC5h CC6h CD0-CD4h CD0h CD1h CD2h CD3h CD4h D00-D5Ah D00h D02h D03h D04h D08h D0Ah D10h D14h D18h D1Ah D1Bh D1Ch D20h D21h D22h D28h D29h D30h D31h D32h D33h D40h D41h D42h D43h D44h D45h page 12-4 page 12-6 page 12-8 page 12-9 page 12-10 page 12-13 page 12-15 page 12-17 page 12-19 page 12-21 page 12-21 page 12-21 page 12-21 page 12-21 page 12-21 page 12-21 page 12-21 page 12-21 page 12-21 page 12-21 page 12-21 page 12-21 page 12-21 page 12-21 page 12-21 page 12-21 page 12-21 page 19-2 page 19-4 page 19-5 page 19-6 page 19-7 page 18-3 page 18-4 page 18-5 page 18-3 page 18-4 page 18-5 Register Name UART Serial Ports UART 1 General Control UART 1 General Status UART 1 FIFO Control Shadow UART 2 General Control UART 2 General Status UART 2 FIFO Control Shadow Synchronous Serial Interface SSI Control SSI Transmit SSI Command SSI Status SSI Receive Programmable Interrupt Controller Interrupt Control Master PIC Interrupt Mode Slave 1 PIC Interrupt Mode Slave 2 PIC Interrupt Mode Software Interrupt 16-1 Control Software Interrupt 22-17/NMI Control Interrupt Pin Polarity PCI Host Bridge Interrupt Mapping ECC Interrupt Mapping GP Timer 0 Interrupt Mapping GP Timer 1 Interrupt Mapping GP Timer 2 Interrupt Mapping PIT 0 Interrupt Mapping PIT 1 Interrupt Mapping PIT 2 Interrupt Mapping UART 1 Interrupt Mapping UART 2 Interrupt Mapping PCI Interrupt A Mapping PCI Interrupt B Mapping PCI Interrupt C Mapping PCI Interrupt D Mapping DMA Buffer Chaining Interrupt Mapping SSI Interrupt Mapping Watchdog Timer Interrupt Mapping RTC Interrupt Mapping Write-Protect Violation Interrupt Mapping AMDebugTM Technology RX/TX Interrupt Mapping ElanTMSC520 Microcontroller Register Set Manual 1-5 Configuration Register Overview Table 1-1 Memory-Mapped Configuration Region (MMCR) Registers (By Offset) (Continued) Mnemonic FERRMAP GP0IMAP GP1IMAP GP2IMAP GP3IMAP GP4IMAP GP5IMAP GP6IMAP GP7IMAP GP8IMAP GP9IMAP GP10IMAP SYSINFO RESCFG RESSTA GPDMACTL GPDMAMMIO GPDMAEXTCHMAPA GPDMAEXTCHMAPB GPDMAEXTPG0 GPDMAEXTPG1 GPDMAEXTPG2 GPDMAEXTPG3 GPDMAEXTPG5 GPDMAEXTPG6 GPDMAEXTPG7 GPDMAEXTTC3 GPDMAEXTTC5 GPDMAEXTTC6 GPDMAEXTTC7 GPDMABCCTL GPDMABCSTA GPDMABSINTENB GPDMABCVAL GPDMANXTADDL3 GPDMANXTADDH3 GPDMANXTADDL5 GPDMANXTADDH5 GPDMANXTADDL6 MMCR Offset Page Number D46h D50h D51h D52h D53h D54h D55h D56h D57h D58h D59h D5Ah D70-D74h D70h D72h D74h D80-DBEh D80h D81h D82h D84h D86h D87h D88h D89h D8Ah D8Bh D8Ch D90h D91h D92h D93h D98h D99h D9Ah D9Bh DA0h DA2h DA4h DA6h DA8h page 11-4 page 11-5 page 11-6 page 11-8 page 11-10 page 11-11 page 11-12 page 11-13 page 11-14 page 11-15 page 11-16 page 11-17 page 11-18 page 11-19 page 11-20 page 11-21 page 11-22 page 11-24 page 11-25 page 11-26 page 11-27 page 11-28 page 11-29 page 11-30 page 3-2 page 3-3 page 3-5 page 12-21 page 12-21 page 12-21 page 12-21 page 12-21 page 12-21 page 12-21 page 12-21 page 12-21 page 12-21 page 12-21 page 12-21 Register Name Floating Point Error Interrupt Mapping GPIRQ0 Interrupt Mapping GPIRQ1 Interrupt Mapping GPIRQ2 Interrupt Mapping GPIRQ3 Interrupt Mapping GPIRQ4 Interrupt Mapping GPIRQ5 Interrupt Mapping GPIRQ6 Interrupt Mapping GPIRQ7 Interrupt Mapping GPIRQ8 Interrupt Mapping GPIRQ9 Interrupt Mapping GPIRQ10 Interrupt Mapping Reset Generation System Board Information Reset Configuration Reset Status GP DMA Controller GP-DMA Control GP-DMA Memory-Mapped I/O GP-DMA Resource Channel Map A GP-DMA Resource Channel Map B GP-DMA Channel 0 Extended Page GP-DMA Channel 1 Extended Page GP-DMA Channel 2 Extended Page GP-DMA Channel 3 Extended Page GP-DMA Channel 5 Extended Page GP-DMA Channel 6 Extended Page GP-DMA Channel 7 Extended Page GP-DMA Channel 3 Extended Transfer Count GP-DMA Channel 5 Extended Transfer Count GP-DMA Channel 6 Extended Transfer Count GP-DMA Channel 7 Extended Transfer Count Buffer Chaining Control Buffer Chaining Status Buffer Chaining Interrupt Enable Buffer Chaining Valid GP-DMA Channel 3 Next Address Low GP-DMA Channel 3 Next Address High GP-DMA Channel 5 Next Address Low GP-DMA Channel 5 Next Address High GP-DMA Channel 6 Next Address Low 1-6 ElanTMSC520 Microcontroller Register Set Manual Configuration Register Overview Table 1-1 Memory-Mapped Configuration Region (MMCR) Registers (By Offset) (Continued) Mnemonic GPDMANXTADDH6 GPDMANXTADDL7 GPDMANXTADDH7 GPDMANXTTCL3 GPDMANXTTCH3 GPDMANXTTCL5 GPDMANXTTCH5 GPDMANXTTCL6 GPDMANXTTCH6 GPDMANXTTCL7 GPDMANXTTCH7 MMCR Offset Page Number DAAh DACh DAEh DB0h DB2h DB4h DB6h DB8h DBAh DBCh DBEh page 11-31 page 11-32 page 11-33 page 11-34 page 11-35 page 11-36 page 11-37 page 11-38 page 11-39 page 11-40 page 11-41 Register Name GP-DMA Channel 6 Next Address High GP-DMA Channel 7 Next Address Low GP-DMA Channel 7 Next Address High GP-DMA Channel 3 Next Transfer Count Low GP-DMA Channel 3 Next Transfer Count High GP-DMA Channel 5 Next Transfer Count Low GP-DMA Channel 5 Next Transfer Count High GP-DMA Channel 6 Next Transfer Count Low GP-DMA Channel 6 Next Transfer Count High GP-DMA Channel 7 Next Transfer Count Low GP-DMA Channel 7 Next Transfer Count High 1.2 DIRECT-MAPPED I/O REGISTERS The direct-mapped I/O registers include the Configuration Base Address (CBAR) register and PC/AT-compatible peripheral registers, such as the programmable interval timer (PIT), programmable interrupt controller (PIC), direct memory access (DMA) controller, the realtime clock (RTC) index and data registers, the PCI configuration address and data registers, two universal asynchronous receive/transmit (UART) devices, and miscellaneous control registers defined for compatibility. (The microcontroller's third PIC and the CBAR register are not found in PC/AT-compatible systems.) Table 1-2 lists all of the direct-mapped I/O registers in the ELANSC520 microcontroller. Table 1-2 Direct-Mapped I/O Registers Mnemonic GPDMA0MAR GPDMA0TC GPDMA1MAR GPDMA1TC GPDMA2MAR GPDMA2TC GPDMA3MAR GPDMA3TC SLDMASTA SLDMACTL SLDMASWREQ SLDMAMSK SLDMAMODE SLDMACBP SLDMARST SLDMATMP SLDMAMSKRST SLDMAGENMSK I/O Address 0000-000Fh 0000h 0001h 0002h 0003h 0004h 0005h 0006h 0007h 0008h 0008h 0009h 000Ah 000Bh 000Ch 000Dh 000Dh 000Eh 000Fh page 11-42 page 11-43 page 11-44 page 11-45 page 11-46 page 11-47 page 11-48 page 11-49 page 11-50 page 11-51 page 11-53 page 11-54 page 11-55 page 11-57 page 11-58 page 11-59 page 11-60 page 11-61 Page Number Register Name Slave DMA Slave DMA Channel 0 Memory Address Slave DMA Channel 0 Transfer Count Slave DMA Channel 1 Memory Address Slave DMA Channel 1 Transfer Count Slave DMA Channel 2 Memory Address Slave DMA Channel 2 Transfer Count Slave DMA Channel 3 Memory Address Slave DMA Channel 3 Transfer Count Slave DMA Channel 0-3 Status Slave DMA Channel 0-3 Control Slave Software DRQ(n) Request Slave DMA Channel 0-3 Mask Slave DMA Channel 0-3 Mode Slave DMA Clear Byte Pointer Slave DMA Controller Reset Slave DMA Controller Temporary Slave DMA Mask Reset Slave DMA General Mask ElanTMSC520 Microcontroller Register Set Manual 1-7 Configuration Register Overview Table 1-2 Direct-Mapped I/O Registers (Continued) Mnemonic MPICIR MPICISR MPICICW1 MPICOCW2 MPICOCW3 MPICICW2 MPICICW3 MPICICW4 MPICINTMSK S2PICIR S2PICISR S2PICICW1 S2PICOCW2 S2PICOCW3 S2PICICW2 S2PICICW3 S2PICICW4 S2PICINTMSK PIT0CNT PIT1CNT PIT2CNT PIT0STA PIT1STA PIT2STA PITMODECTL PITCNTLAT PITRDBACK SCPDATA SYSCTLB SCPCMD RTCIDX RTCDATA GPDMAGR0 GPDMA2PG GPDMA3PG GPDMA1PG I/O Address 0020, 0021h 0020h 0020h 0020h 0020h 0020h 0021h 0021h 0021h 0021h 0024h, 0025h 0024h 0024h 0024h 0024h 0024h 0025h 0025h 0025h 0025h 0040-0043h 0040h 0041h 0042h 0040h 0041h 0042h 0043h 0043h 0043h 0060h 0061h 0064h 0070h, 0071h 0070h 0071h 0080-008Fh 0080h 0081h 0082h 0083h page 11-62 page 11-63 page 11-64 page 11-65 page 17-2 page 17-3 page 13-2 page 13-3 page 13-4 page 13-5 page 13-5 page 13-5 page 13-7 page 13-10 page 13-11 page 3-7 page 13-13 page 3-8 page 12-37 page 12-38 page 12-39 page 12-41 page 12-43 page 12-45 page 12-46 page 12-47 page 12-48 page 12-24 page 12-25 page 12-26 page 12-28 page 12-30 page 12-32 page 12-33 page 12-35 page 12-36 Page Number Register Name Master Programmable Interrupt Controller Master PIC Interrupt Request Master PIC In-Service Master PIC Initialization Control Word 1 Master PIC Operation Control Word 2 Master PIC Operation Control Word 3 Master PIC Initialization Control Word 2 Master PIC Initialization Control Word 3 Master PIC Initialization Control Word 4 Master PIC Interrupt Mask Slave 2 PIC Slave 2 PIC Interrupt Request Slave 2 PIC In-Service Slave 2 PIC Initialization Control Word 1 Slave 2 PIC Operation Control Word 2 Slave 2 PIC Operation Control Word 3 Slave 2 PIC Initialization Control Word 2 Slave 2 PIC Initialization Control Word 3 Slave 2 PIC Initialization Control Word 4 Slave 2 PIC Interrupt Mask Programmable Interval Timer PIT Channel 0 Count PIT Channel 1 Count PIT Channel 2 Count PIT 0 Status PIT 1 Status PIT 2 Status PIT Mode Control PIT Counter Latch Command PIT Read-Back Command SCP Data Port System Control Port B SCP Command Port RTC Index, Data RTC/CMOS RAM Index RTC/CMOS RAM Data Port DMA Page and General Registers General 0 Slave DMA Channel 2 Page Slave DMA Channel 3 Page Slave DMA Channel 1 Page 1-8 ElanTMSC520 Microcontroller Register Set Manual Configuration Register Overview Table 1-2 Direct-Mapped I/O Registers (Continued) Mnemonic GPDMAGR1 GPDMAGR2 GPDMAGR3 GPDMA0PG GPDMAGR4 GPDMA6PG GPDMA7PG GPDMA5PG GPDMAGR5 GPDMAGR6 GPDMAGR7 GPDMAGR8 SYSCTLA S1PICIR S1PICISR S1PICICW1 S1PICOCW2 S1PICOCW3 S1PICICW2 S1PICICW3 S1PICICW4 S1PICINTMSK GPDMA4MAR GPDMA4TC GPDMA5MAR GPDMA5TC GPDMA6MAR GPDMA6TC GPDMA7MAR GPDMA7TC MSTDMASTA MSTDMACTL MSTDMASWREQ MSTDMAMSK MSTDMAMODE MSTDMACBP MSTDMARST MSTDMATMP MSTDMAMSKRST MSTDMAGENMSK I/O Address 0084h 0085h 0086h 0087h 0088h 0089h 008Ah 008Bh 008Ch 008Dh 008Eh 008Fh 0092h 00A0-00A1h 00A0h 00A0h 00A0h 00A0h 00A0h 00A1h 00A1h 00A1h 00A1h 00C0-00DEh 00C0h 00C2h 00C4h 00C6h 00C8h 00CAh 00CCh 00CEh 00D0h 00D0h 00D2h 00D4h 00D6h 00D8h 00DAh 00DAh 00DCh 00DEh page 11-78 page 11-79 page 11-80 page 11-81 page 11-82 page 11-83 page 11-84 page 11-85 page 11-86 page 11-87 page 11-89 page 11-90 page 11-91 page 11-93 page 11-94 page 11-95 page 11-96 page 11-97 page 12-49 page 12-50 page 12-51 page 12-53 page 12-55 page 12-57 page 12-58 page 12-59 page 12-60 Page Number page 11-66 page 11-67 page 11-68 page 11-69 page 11-70 page 11-71 page 11-72 page 11-73 page 11-74 page 11-75 page 11-76 page 11-77 page 3-9 Register Name General 1 General 2 General 3 Slave DMA Channel 0 Page General 4 Master DMA Channel 6 Page Master DMA Channel 7 Page Master DMA Channel 5 Page General 5 General 6 General 7 General 8 System Control Port A Slave 1 PIC Slave 1 PIC Interrupt Request Slave 1 PIC In-Service Slave 1 PIC Initialization Control Word 1 Slave 1 PIC Operation Control Word 2 Slave 1 PIC Operation Control Word 3 Slave 1 PIC Initialization Control Word 2 Slave 1 PIC Initialization Control Word 3 Slave 1 PIC Initialization Control Word 4 Slave 1 PIC Interrupt Mask Master DMA Master DMA Channel 4 Memory Address Master DMA Channel 4 Transfer Count Master DMA Channel 5 Memory Address Master DMA Channel 5 Transfer Count Master DMA Channel 6 Memory Address Master DMA Channel 6 Transfer Count Master DMA Channel 7 Memory Address Master DMA Channel 7 Transfer Count Master DMA Channel 4-7 Status Master DMA Channel 4-7 Control Master Software DRQ(n) Request Master DMA Channel 4-7 Mask Master DMA Channel 4-7 Mode Master DMA Clear Byte Pointer Master DMA Controller Reset Master DMA Controller Temporary Master DMA Mask Reset Master DMA General Mask ElanTMSC520 Microcontroller Register Set Manual 1-9 Configuration Register Overview Table 1-2 Direct-Mapped I/O Registers (Continued) Mnemonic FPUERRCLR UART2THR UART2RBR UART2BCDL UART2BCDH UART2INTENB UART2INTID UART2FCR UART2LCR UART2MCR UART2LSR UART2MSR UART2SCRATCH UART1THR UART1RBR UART1BCDL UART1BCDH UART1INTENB UART1INTID UART1FCR UART1LCR UART1MCR UART1LSR UART1MSR UART1SCRATCH PCICFGADR PCICFGDATA CBAR I/O Address F0h 02F8-02FFh 02F8h 02F8h 02F8h 02F9h 02F9h 02FAh 02FAh 02FBh 02FCh 02FDh 02FEh 02FFh 03F8-03FFh 03F8h 03F8h 03F8h 03F9h 03F9h 03FAh 03FAh 03FBh 03FCh 03FDh 03FEh 03FFh 0CF8h, 0CFCh 0CF8h 0CFCh FFFCh page 6-15 page 6-17 page 2-9 page 18-7 page 18-8 page 18-9 page 18-10 page 18-11 page 18-12 page 18-15 page 18-17 page 18-19 page 18-21 page 18-23 page 18-25 page 18-7 page 18-8 page 18-9 page 18-10 page 18-11 page 18-12 page 18-15 page 18-17 page 18-19 page 18-21 page 18-23 page 18-25 Page Number page 12-61 Register Name Floating Point Error Interrupt Clear UART 2 UART 2 Transmit Holding UART 2 Receive Buffer UART 2 Baud Clock Divisor Latch LSB UART 2 Baud Clock Divisor Latch MSB UART 2 Interrupt Enable UART 2 Interrupt ID UART 2 FIFO Control UART 2 Line Control UART 2 Modem Control UART 2 Line Status UART 2 Modem Status UART 2 Scratch Pad UART 1 UART 1 Transmit Holding UART 1 Receive Buffer UART 1 Baud Clock Divisor Latch LSB UART 1 Baud Clock Divisor Latch MSB UART 1 Interrupt Enable UART 1 Interrupt ID UART 1 FIFO Control UART 1 Line Control UART 1 Modem Control UART 1 Line Status UART 1 Modem Status UART 1 Scratch Pad PCI Bus Configuration Space Index/Data (32-bit) PCI Configuration Address PCI Configuration Data Configuration Base Address 1.3 PCI HOST BRIDGE INDEXED CONFIGURATION REGISTERS The ELANSC520 microcontroller's PCI Host Bridge supports the required PCI configuration space header registers, plus a Host Bridge-specific Master Retry Time-Out (PCIMRETRYTO) register defined in the PCI configuration space. Note that additional microcontroller-specific PCI Host Bridge configuration registers are provided in the MMCR space (see Table 1-1). PCI indexed registers are accessed via two 32-bit direct-mapped I/O locations: Port 0CF8h and Port 0CFCh. The PCI configuration mechanism can be used to access either the Host Bridge-specific PCI indexed registers, or the device-specific PCI indexed registers for any 1-10 ElanTMSC520 Microcontroller Register Set Manual Configuration Register Overview other device that is connected to the PCI bus. Refer to the PCI Local Bus Specification, Revision 2.2, for details on PCI configuration. Table 1-3 lists all of the PCI indexed registers in the ELANSC520 microcontroller. Table 1-3 PCI Indexed Registers Mnemonic PCIDEVID PCISTACMD PCICCREVID PCIHEADTYPE PCIMRETRYTO I/O Address 0CF8h/0CFCh 0CF8h/0CFCh 0CF8h/0CFCh 0CF8h/0CFCh 0CF8h/0CFCh PCI Index Page Number 00h 04h 08h 0Eh 41h page 6-18 page 6-19 page 6-22 page 6-23 page 6-24 Register Name Device/Vendor ID Status/Command Class Code/Revision ID Header Type Master Retry Time-Out 1.4 RTC AND CMOS RAM INDEXED REGISTERS Real-time clock and CMOS RAM indexed registers are accessed using I/O ports 0070h (index) and 0071h (data). These registers provide PC/AT-compatible setup, control, and status functions for the RTC, as well as user CMOS RAM locations. Table 1-4 lists all of the RTC indexed registers in the ELANSC520 microcontroller. Table 1-4 Real-Time Clock Indexed Registers Mnemonic RTCCURSEC RTCALMSEC RTCCURMIN RTCALMMIN RTCCURHR RTCALMHR RTCCURDOW RTCCURDOM RTCCURMON RTCCURYR RTCCTLA RTCCTLB RTCSTAC RTCSTAD RTCCMOS I/O Address 70h/71h 70h/71h 70h/71h 70h/71h 70h/71h 70h/71h 70h/71h 70h/71h 70h/71h 70h/71h 70h/71h 70h/71h 70h/71h 70h/71h 70h/71h RTC Index Page Number 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0E-7Fh page 17-4 page 17-5 page 17-6 page 17-7 page 17-8 page 17-9 page 17-10 page 17-11 page 17-12 page 17-13 page 17-14 page 17-16 page 17-18 page 17-20 page 17-21 Register Name RTC Current Second RTC Alarm Second RTC Current Minute RTC Alarm Minute RTC Current Hour RTC Alarm Hour RTC Current Day of the Week RTC Current Day of the Month RTC Current Month RTC Current Year RTC Control A RTC Control B RTC Status C RTC Status D General-Purpose CMOS RAM (114 bytes) ElanTMSC520 Microcontroller Register Set Manual 1-11 Configuration Register Overview 1-12 ElanTMSC520 Microcontroller Register Set Manual CHAPTER 2 2.1 SYSTEM ADDRESS MAPPING REGISTERS OVERVIEW This chapter describes the system memory and I/O address mapping registers of the ELANSC520 microcontroller. The system address mapping register set consists of 18 memory-mapped configuration region (MMCR) registers and one direct-mapped I/O register used to define the memory and I/O map in an ELANSC520 microcontroller-based system, and to control specific attributes of SDRAM and ROM regions. See the ElanTMSC520 Microcontroller User's Manual, order #22004, for details about memory and I/O space. Table 2-1 and Table 2-2 list each type of memory and I/O space register in offset order, with the corresponding description's page number. 2.2 Table 2-1 REGISTERS System Address Mapping MMCR Registers Register Name Address Decode Control Write-Protect Violation Status Programmable Address Region 0 Programmable Address Region 1 Programmable Address Region 2 Programmable Address Region 3 Programmable Address Region 4 Programmable Address Region 5 Programmable Address Region 6 Programmable Address Region 7 Programmable Address Region 8 Programmable Address Region 9 Programmable Address Region 10 Programmable Address Region 11 Programmable Address Region 12 Programmable Address Region 13 Programmable Address Region 14 Programmable Address Region 15 Mnemonic ADDDECCTL WPVSTA PAR0 PAR1 PAR2 PAR3 PAR4 PAR5 PAR6 PAR7 PAR8 PAR9 PAR10 PAR11 PAR12 PAR13 PAR14 PAR15 MMCR Offset 80h 82h 88h 8Ch 90h 94h 98h 9Ch A0h A4h A8h ACh B0h B4h B8h BCh C0h C4h Page Number page 2-2 page 2-4 page 2-5 page 2-5 page 2-5 page 2-5 page 2-5 page 2-5 page 2-5 page 2-5 page 2-5 page 2-5 page 2-5 page 2-5 page 2-5 page 2-5 page 2-5 page 2-5 Table 2-2 System Address Mapping Direct-Mapped Register Register Name Configuration Base Address Mnemonic CBAR I/O Address FFFCh Page Number page 2-9 ElanTMSC520 Microcontroller Register Set Manual 2-1 System Address Mapping Registers Address Decode Control (ADDDECCTL) Memory-Mapped MMCR Offset 80h 7 Bit Reset R/W 6 Reserved 0 RSV 5 4 IO_HOLE_ DEST 3 Reserved 0 RSV 2 RTC_DIS 0 R/W 1 0 WPV_INT_ ENB 0 R/W UART2_DIS UART1_DIS 0 R/W 0 R/W 0 0 R/W Register Description This register controls miscellaneous functions in the ELANSC520 microcontroller address decode block. Bit Definitions Bit 7 Name WPV_INT_ ENB Function Write-Protect Violation Interrupt Enable This bit enables an interrupt request to be generated when a write-protect violation occurs. 0 = Write-protect violations do not generate an interrupt request to the CPU. 1 = Write-protect violations generate an interrupt request to the CPU. Before the WPV_INT_ENB bit is set, the WPVMAP register (see page 12-21) must be configured to route the interrupt to the appropriate interrupt request level and priority. The initiator of the access that caused the write-protect violation can be the Am5x86 CPU, any PCI bus master, or the GP bus DMA controller. This interrupt can only be generated if at least one of the PARx register windows is enabled and has the write-protect attribute selected (see page 2-6). 6-5 4 Reserved IO_HOLE_ DEST Reserved This bit field should be written to 0 for normal system operation. I/O Hole Access Destination This bit determines the destination of accesses performed by the Am5x86 CPU to certain I/O addresses in the range 0000h to 03FFh. 0 = The accesses are forwarded to the external GP bus (default). 1 = The accesses are forwarded to the PCI bus I/O space. I/O addresses in the range 0000h to 03FFh that are not occupied by the internal GP bus peripherals are normally reserved for PC/AT-compatible peripherals. Such addresses are referred to as holes in the I/O address space. See the memory and I/O chapter of the ElanTMSC520 Microcontroller User's Manual, order #22004, for details about these holes. If a PARx register (see page 2-6) is configured to address GP bus I/O space within a hole, accesses in the defined region are forwarded to the GP bus regardless of the IO_HOLE_DEST bit value. The PARx window must not overlap any of the internal peripherals' direct-mapped I/O addresses. 3 Reserved Reserved This bit field should be written to 0 for normal system operation. 2-2 ElanTMSC520 Microcontroller Register Set Manual System Address Mapping Registers Bit 2 Name RTC_DIS Function RTC Disable This bit causes the integrated RTC to be disabled. 0 = The integrated RTC is enabled. 1 = The integrated RTC is not used, and accesses to the RTC address space are forwarded externally to the GP bus. When the internal RTC is disabled, the corresponding interrupt request is not automatically disconnected from the PIC. If an external RTC is to drive the RTC interrupt request, then all interrupt enables in the RTCCTLB register must be cleared prior to disabling the internal RTC (see page 17-16). After the internal RTC is disabled, a PARx window can be defined to target a GPCSx chip select in the RTC I/O address space. If a PARx window is not used, the external RTC must fully decode the addresses. 1 UART2_DIS UART 2 Disable This bit causes the integrated UART 2 to be disabled. 0 = The integrated UART 2 is enabled. 1 = The integrated UART 2 is not used, and accesses to the UART 2 I/O address space are forwarded externally to the GP bus. When the internal UART 2 is disabled, the corresponding interrupt request is not automatically disconnected from the PIC. If an external UART is to drive the UART 2 interrupt request, then all interrupt enables in the UART2CTL and UART2INTENB registers must be cleared (see page 18-3 and page 18-11). After the internal UART 2 is disabled, a PARx window can be defined to target a GPCSx chip select in the UART 2 I/O address space. If a PARx window is not used, the external UART must fully decode the addresses. 0 UART1_DIS UART 1 Disable This bit causes the integrated UART 1 to be disabled. 0 = The integrated UART 1 is enabled. 1 = The integrated UART 1 is not used, and accesses to the UART 1 I/O address space are forwarded externally to the GP bus. When the internal UART 1 is disabled, the corresponding interrupt request is not automatically disconnected from the PIC. If an external UART is to drive the UART 1 interrupt request, then all interrupt enables in the UART1CTL and UART1INTENB registers must be cleared (see page 18-3 and page 18-11). After the internal UART 1 is disabled, a PARx window can be defined to target a GPCSx chip select in the UART 1 I/O address space. If a PARx window is not used, the external UART must fully decode the addresses. Programming Notes When the ELANSC520 microcontroller comes out of reset, the internal RTC and UARTs are enabled. If the system application requires the use of an external RTC or UARTs, the internal devices should be disabled during the boot process and initialization to prevent potential conflicts. When the integrated UARTs are disabled, only the I/O space accesses associated with these peripherals are forwarded externally. The accesses to the MMCR registers for the UARTs are not forwarded externally because these registers are specific to the integrated peripherals. Therefore, the UART MMCR registers should not be used while the integrated UARTs are disabled. Even if the internal RTC or UARTs are disabled, setting the IO_HOLE_DEST bit does not redirect accesses to the disabled peripherals to PCI bus I/O space. ElanTMSC520 Microcontroller Register Set Manual 2-3 System Address Mapping Registers Write-Protect Violation Status (WPVSTA) Memory-Mapped MMCR Offset 82h 15 Bit Reset R/W 14 13 12 Reserved 11 10 9 8 WPV_STA 0 R/W! 7 6 Reserved 0 0 RSV 0 5 0 0 WPV_MSTR[1-0] 0 0 0 R 3 2 1 0 0 0 RSV 4 Bit Reset R/W WPV_WINDOW[3-0] 0 0 0 R 0 0 Register Description This register provides write-protect violation status for the ELANSC520 microcontroller's address decode block. Bit Definitions Bit 15 Name WPV_STA Function Write-Protect Violation Interrupt Status This bit indicates whether an interrupt request is pending due to a write-protect violation. 0 = Write-protect violations interrupt request not pending. 1 = Write-protect violations interrupt request pending. Software must write a 1 to this bit to clear the interrupt (and the status bit) before the hardware can latch subsequent write-protect violations. This bit provides the status of the interrupt regardless of the setting of the WPV_INT_ENB bit in the ADDDECCTL register (see page 2-2). 14-10 9-8 Reserved WPV_MSTR [1-0] Reserved This bit field should be written to 0 for normal system operation. Write-Protect Violation Master This bit field identifies the master that caused the write-protect violation. 00 = The Am5x86 CPU caused the violation. 01 = A PCI bus master caused the violation. 10 = The GP bus DMA controller caused the violation. 11 = Reserved. This bit field contains valid information only while the WPV_STA bit is set. The master's identity is latched when a write-protect violation occurs. Subsequent write-protect violations are not captured until software clears the interrupt by writing a 1 to the WPV_STA bit. 7-4 3-0 Reserved WPV_WINDOW [3-0] Reserved This bit field should be written to 0 for normal system operation. Write-Protect Violation Window Number This bit field identifies the programmable address region window (PAR0-PAR15) in which the write-protect violation occurred. This bit field contains valid information only while the WPV_STA bit is set. The PARx window number is latched when a write-protect violation occurs. Subsequent write-protect violations are not captured until software clears the interrupt by writing a 1 to the WPV_STA bit. Programming Notes 2-4 ElanTMSC520 Microcontroller Register Set Manual System Address Mapping Registers Memory-Mapped Programmable Address Region 0 (PAR0) Programmable Address Region 1 (PAR1) Programmable Address Region 2 (PAR2) Programmable Address Region 3 (PAR3) Programmable Address Region 4 (PAR4) Programmable Address Region 5 (PAR5) Programmable Address Region 6 (PAR6) Programmable Address Region 7 (PAR7) Programmable Address Region 8 (PAR8) Programmable Address Region 9 (PAR9) Programmable Address Region 10 (PAR10) Programmable Address Region 11 (PAR11) Programmable Address Region 12 (PAR12) Programmable Address Region 13 (PAR13) Programmable Address Region 14 (PAR14) Programmable Address Region 15 (PAR15) MMCR Offset 88h MMCR Offset 8Ch MMCR Offset 90h MMCR Offset 94h MMCR Offset 98h MMCR Offset 9Ch MMCR Offset A0h MMCR Offset A4h MMCR Offset A8h MMCR Offset ACh MMCR Offset B0h MMCR Offset B4h MMCR Offset B8h MMCR Offset BCh MMCR Offset C0h MMCR Offset C4h 31 Bit Reset R/W 30 TARGET[2-0] 29 28 27 ATTR[2-0] 26 25 PG_SZ 24 SZ_ST_AD R[24] 0 R/W 16 0 0 R/W 0 0 0 R/W 0 0 R/W 23 Bit Reset R/W 22 21 20 19 18 17 SZ_ST_ADR[23-16] 0 0 0 0 R/W 15 14 13 12 11 10 9 8 0 0 0 0 Bit Reset R/W SZ_ST_ADR[15-8] 0 0 0 0 R/W 7 6 5 4 3 2 1 0 0 0 0 0 Bit Reset R/W SZ_ST_ADR[7-0] 0 0 0 0 R/W 0 0 0 0 ElanTMSC520 Microcontroller Register Set Manual 2-5 System Address Mapping Registers Register Description These registers can be used to map windows of memory address space to SDRAM, ROM, PCI bus, or GP bus; or to map windows of I/O space to the GP bus. These registers are also used to apply noncacheability, write-protect, and nonexecutable attributes to SDRAM and ROM regions. Bit Definitions Bit 31-29 Name TARGET[2-0] Function Target of the PARx Window This bit field defines the target (destination) of the PARx window being configured. If no PARx window is enabled (i.e., the TARGET bit field is 000b in all PARx registers), the default memory map for the lower 1 Gbyte address range (00000000h-3FFFFFFFh) is either SDRAM (if enabled) or PCI. Accesses to any external GP bus devices or devices connected to ROMCS1 or ROMCS2 require a PARx window to be enabled and configured to access them. 000 = The window is disabled. All other bits in the PARx register are ignored. 001 = The window targets a GP bus I/O region. This is the only I/O space access possible through a PARx window. All other settings refer to the memory address space. For GP bus windows, the ATTR bit field selects a GP bus chip select. See the programming notes for this register, on page 2-8, for GP-bus I/O address restrictions. 010 = The window targets a GP bus memory region. For GP bus windows, the ATTR bit field selects a GP bus chip select. 011 = The window targets a PCI bus memory region. Only PAR0 and PAR1 support a PCI bus memory region as a target. Define a PCI bus window only when attempting to forward cycles to the PCI bus in the lower 256 Mbyte address range (00000000h to 0FFFFFFFh). 100 = The window targets a BOOTCS region (boot ROM or Flash memory device). The ELANSC520 microcontroller forces the BOOTCS signal active at system reset, but the boot code must initialize a PARx register to decode the required space for the ROM. Refer to theElanTMSC520 Microcontroller User's Manual, order #22004, for details on configuring the boot ROM during system initialization. 101 = The window targets a ROMCS1 region (ROM or Flash memory devices). 110 = The window targets a ROMCS2 region (ROM or Flash memory devices). 111 = The window targets an SDRAM region. A PARx register is not required to access SDRAM. Target an SDRAM region only when applying one of the attributes described in the ATTR bit field. 2-6 ElanTMSC520 Microcontroller Register Set Manual System Address Mapping Registers Bit 28-26 Name ATTR[2-0] Function Attribute If the TARGET bit field selects the PCI bus (for PAR0 and PAR1 only), this bit field (ATTR) is ignored. If the TARGET bit field selects GP bus I/O or memory, this bit field (ATTR) specifies the GP bus chip select that is targeted, as follows: 000 = GPCS0 001 = GPCS1 010 = GPCS2 011 = GPCS3 100 = GPCS4 101 = GPCS5 110 = GPCS6 111 = GPCS7 If the TARGET bit field selects SDRAM or one of the ROM/Flash chip selects, each bit in this bit field (ATTR) specifies an attribute. The attribute bits for the region can be set or cleared independently, with the following effect: 0xx = Code execution is allowed in programmed memory region. 1xx = Code execution is prevented in programmed memory region. An attempt to execute code results in a processor exception and returns an illegal operand code (FFFFh). This attribute is useful for debugging software; for example, to prevent a program from erroneously executing out of a data region. x0x = Caching is enabled for the programmed memory region (Am5x86 CPU cache). x1x = Caching is disabled for the programmed memory region. This attribute can be used to minimize cache write-back cycle overhead in regions that are shared between the Am5x86 CPU and PCI bus masters or GP bus DMA devices. Software must flush the cache immediately after setting this attribute. xx0 = Writes are enabled in the programmed memory region. xx1 = Write protection is enabled (writes are disabled) in the programmed memory region. Write protection prevents writes from occurring in the region's address range. Writeprotect violations are reported by the WPVSTA register (see page 2-4), and a corresponding interrupt can be enabled via the WPV_INT_ENB bit in the ADDDECCTL register (see page 2-2). 25 PG_SZ Page Size This bit selects the page size of the memory region defined by the SZ_ST_ADR bit field. This bit is ignored during I/O cycles. 0 = 4-Kbyte page size selected 1 = 64-Kbyte page size selected Each PARx window's total size in memory space is defined by the combined settings of the PG_SZ and SZ_ST_ADR bit fields. The PG_SZ bit value affects the window start address resolution, the window size resolution, and the total size that is possible for the window. ElanTMSC520 Microcontroller Register Set Manual 2-7 System Address Mapping Registers Bit 24-0 Name SZ_ST_ADR [24-0] Function Region Size/Start Address This bit field, in conjunction with the PG_SZ bit, is used to specify the total region size and the starting address of the programmed address space. This bit field is used in one of three ways: For Memory Space Regions with 4-Kbyte Pages: s The PG_SZ bit is 0. s The SZ_ST_ADR[24-18] bit field is used to specify a memory space size of up to 128 pages, each 4 Kbytes in size, for a maximum PARx window size of 512 Kbytes. Pages start on 4-Kbyte boundaries. (A value of 00h specifies one page; 7Fh specifies 128 pages.) The SZ_ST_ADR[17-0] bit field is used to define the starting page of the region within the memory address space. The SZ_ST_ADR[17-0] bit field is compared to internal Am5x86 CPU bus signals a29-a12. s For Memory Space Regions with 64-Kbyte Pages: s The PG_SZ bit is 1. s The SZ_ST_ADR[24-14] bit field is used to specify a memory space size of up to 2048 pages, each 64 Kbytes in size, for a maximum PARx window size of 128 Mbytes. Pages start on 64-Kbyte boundaries. (A value of 000h specifies one page; 7FFh specifies 2048 pages.) The S Z_ST_ADR[13-0] bit field is used to define the starting page of the region within the memory address space. The SZ_ST_ADR[13-0] bit field is compared to internal Am5x86 CPU bus signals a29-a16. s For I/O Space Regions: s The PG_SZ bit is ignored. s s The SZ_ST_ADR[24-16] bit field is used to specify an I/O space size of byte granularity, for a total size up to 512 bytes. (A value of 000h specifies one byte; 1FFh specifies 512 bytes.) The SZ_ST_ADR[15-0] bit field is used to define the starting address of the window within the 64 -Kbyte I/O space. The SZ_ST_ADR[15-0] bit field is compared to internal Am5x86 CPU bus signals a15-a0. Note: If a larger window than the maximum size is required, multiple PARx registers can be used. Programming Notes Each PARx register must be written as a full 32-bit doubleword. The basic trade-off with setting the page size in a PARx register is the granularity of the memory region. The smaller page size restricts the total size of the region, but allows the smaller granularity of 4 Kbytes. The larger 64-Kbyte page size is an option when the total region size must be larger than 512 Kbytes, but this requires the pages to start on 64-Kbyte boundaries. If two PARx windows overlap, the lower-numbered PARx register's target has priority. For example, if a memory or I/O address falls within the windows defined by both the PAR4 register and the PAR 13 register, reads or writes to that address go to the PAR4 register's target, not the one defined in the PAR13 register. If a PARx window overlaps the MMCR alias defined by the CBAR register (see page 2-9), the MMCR alias has priority, with the following exception: if a PAR window is configured for PCI, and the CBAR register is programmed to overlap with this PAR window, and the PAR window is placed below the top of DRAM, then the MMCR is not given priority over the PCI access. This configuration could result in system errors due to concurrence of both PCI and internal MMCR accesses. PARx windows in the GP bus I/O space must not include any of the following direct-mapped register addresses: CBAR (Port FFFCh), PCICFGADR (Port 0CF8h), or PCICFGDATA (Port 0CFCh). Also, the PARx window must not overlap any direct-mapped I/O address belonging to an internal peripheral (i.e., GP bus DMA, PIC, PIT, system control ports, RTC, or UART I/O registers). When programming a PARx register for GP bus I/O space, it is best to start the space on a doubleword boundary. If an unaligned byte region is specified for I/O access, the software that accesses the region must directly address the correct byte or bytes. For example, if a PARx register is programmed for an I/O region starting at address xxx1h (i.e., byte1 of the associated doubleword), then when the CPU performs a word or doubleword access, the entire access is redirected to the PCI bus, and byte 1 is not accessed on the GP bus as programmed. In this case the byte requested must be directly accessed by the CPU at I/O address xxx1h. 2-8 ElanTMSC520 Microcontroller Register Set Manual System Address Mapping Registers Configuration Base Address (CBAR) Direct-Mapped I/O Address FFFCh 31 Bit Reset R/W 30 Reserved 0 RSV 22 29 28 27 26 25 24 ENABLE 0 R/W! 23 ADR[29-24] 0 0 0 R/W 21 20 19 18 17 16 0 0 0 Bit Reset R/W ADR[23-16] 0 0 0 0 R/W 15 14 13 12 11 10 Reserved 0 0 0 RSV 5 4 3 2 1 0 0 0 9 8 0 0 0 0 Bit Reset R/W ADR[15-12] 0 0 R/W 7 6 0 Bit Reset R/W MATCH[7-0] 0 0 0 0 W 0 0 0 0 Register Description This register can be used to alias the memory-mapped configuration region (MMCR) that is used to access many of the ELANSC520 microcontroller's integrated peripheral functions. The MMCR is always accessible at FFFEF000- FFFEFFFFh, in the region directly below the boot ROM space, but it can also be aliased to any 4-Kbyte boundary within the first 1 Gbyte of memory space. Bit Definitions Bit 31 Name ENABLE Function Enable This bit must be set to enable write access to the CBAR register. Upon reading, the ENABLE bit returns the state of the MMCR alias. 0 = MMCR alias is disabled. 1 = MMCR alias is enabled. Writes to this bit are ignored if the value CBh is not written to the MATCH bit field in the same write cycle. 30 29-12 Reserved ADR[29-12] Reserved This bit field should be written to 0 for normal system operation. Start Address This bit field defines the starting address of the memory-mapped configuration region on a 4-Kbyte boundary. The address programmed in this bit field is compared to internal Am5x86 CPU bus signals a29-a12. Writes to this bit field are ignored unless the ENABLE bit set and the value CBh is written to the MATCH bit field in the same write cycle. Both of these conditions are required for the write to take effect. ElanTMSC520 Microcontroller Register Set Manual 2-9 System Address Mapping Registers Bit 11-8 7-0 Name Reserved MATCH[7-0] Function Reserved This bit field should be written to 0 for normal system operation. Match The bit field is used to prevent illegal writes to this register. The data pattern written to this byte must be CBh. If any other data pattern is written to these bits, the entire 32-bit write is ignored. This bit field returns 0 when read. Programming Notes This register must be written as a full 32-bit doubleword. When the MMCR alias is enabled, the 4-Kbyte address range to which the alias is mapped becomes the MMCR, regardless of any PARx registers that are enabled in the same 4-Kbyte address range. In effect, the MMCR alias has higher priority than any of the PARx windows that are enabled. 2-10 ElanTMSC520 Microcontroller Register Set Manual CHAPTER 3 3.1 RESET GENERATION REGISTERS OVERVIEW This chapter describes the reset generation and reset-related registers of the ELANSC520 microcontroller. The ELANSC520 microcontroller provides several microcontroller-specific and PC/ATcompatible reset functions. The reset generation register set includes two groups of registers: s Three memory-mapped configuration region (MMCR) registers are used to provide system board information at reset, configure reset behavior, and provide reset status. s Three direct-mapped I/O registers are used to provide PC/AT-compatible reset-related functions. See the ElanTMSC520 Microcontroller User's Manual, order #22004, for details about reset generation. Table 3-1 and Table 3-2 list each type of reset register in offset order, with the corresponding description's page number. 3.2 Table 3-1 REGISTERS Reset Generation MMCR Registers Register Name System Board Information Reset Configuration Reset Status Mnemonic SYSINFO RESCFG RESSTA MMCR Offset D70h D72h D74h Page Number page 3-2 page 3-3 page 3-5 Table 3-2 Reset Generation Direct-Mapped Registers Register Name SCP Data Port SCP Command Port System Control Port A Mnemonic SCPDATA SCPCMD SYSCTLA I/O Address 0060h 0064h 0092h Page Number page 3-7 page 3-8 page 3-9 ElanTMSC520 Microcontroller Register Set Manual 3-1 Reset Generation Registers System Board Information (SYSINFO) Memory-Mapped MMCR Offset D70h 7 Bit Reset R/W 6 5 4 3 2 1 0 RST_LD[7-0] ? ? ? ? R ? ? ? ? Register Description This read-only register contains the state that was latched on the RSTLD7-RSTLD0 pins at the assertion of PWRGOOD. Bit Definitions Bit 7-0 Name RST_LD[7-0] Function Reset Latched Input Data The microcontroller initializes this bit field at the assertion of the PWRGOOD signal by latching the state of the shared RSTLD7-RSTLD0 pins. The information in this bit field remains static after it is latched. Programming Notes These are status-only bits used to provide static information to software. For example, the system hardware designer can configure pullup resistors as needed on the RSTLD7-RSTLD0 pins to provide board revision information to software. The pullup resistors' value should be approximately 10 KW. 3-2 ElanTMSC520 Microcontroller Register Set Manual Reset Generation Registers Reset Configuration (RESCFG) Memory-Mapped MMCR Offset D72h 7 Bit Reset R/W 6 Reserved 5 4 3 ICE_ON_ RST 2 PRG_RST_ ENB 0 R/W 1 GP_RST 0 R/W 0 SYS_RST 0 R/W! 0 0 RSV 0 0 0 R/W! Register Description This register provides a direct read/write port to program system reset and GP bus reset. It also provides a control bit to enable or disable the programmable system reset function of the PRGRESET pin and another control bit to enable the AMDebugTM technology. Bit Definitions Bit 7-4 3 Name Reserved ICE_ON_RST Function Reserved This bit field should be written to 0 for normal system operation. Enter AMDebugTM Technology Mode on Next Reset Setting this bit enables the microprocessor to enter AMDebug technology mode after a hard or soft reset has been asserted to the Am5x86 CPU. Writes to this bit are ignored if the AMDebug technology mode is not active. (The AMDebug technology mode is controlled by the software that drives the AMDebug technology port.) 0 = Do not enter AMDebug technology mode on a CPU hard or soft reset. 1 = Enable the microprocessor to enter AMDebug technology mode on a CPU hard or soft reset. 2 PRG_RST_ ENB Programmable Reset Enable 0 = Programmable reset is disabled. 1 = Programmable reset is enabled. Setting this bit enables programmable resets, during which SDRAM configuration and SDRAM contents are preserved. After this bit is set, programmable resets can be generated by one of four sources: s PRGRESET pin s s s Watchdog timer time-out-generated reset Software write to the SYS_RST bit (with the PRG_RST_ENB bit set in the same write) AMDebug technology system reset If this bit (PRG_RST_ENB) is cleared, the PRGRESET pin has no function. The other programmable reset sources, if generated, initiate non-SDRAM-preserving system resets. This bit is cleared by default, so a toggle on the PRGRESET pin does not affect the ELANSC520 microcontroller. 1 GP_RST Software GP Bus Reset Software can write to this bit to control the GPRESET pin and read back the pin's state. The internal registers are not affected. 0 = Deassert GP bus reset. 1 = Assert GP bus reset. ElanTMSC520 Microcontroller Register Set Manual 3-3 Reset Generation Registers Bit 0 Name SYS_RST Function Software System Reset Software can write to this bit to trigger a one-shot system reset. The last value written is what is read. 0 = Do not cause a one-shot system reset event to be generated. 1 = Cause a one-shot system reset event to be generated. Setting the SYS_RST bit also causes GP bus and PCI-Bus resets to be generated. If the PRG_RST_ENB bit is 1, setting the SYS_RST bit results in a system reset in which the SDRAM configuration is maintained. Programming Notes After a PWRGOOD reset, the programmable system reset feature is disabled and can be enabled only by software writing a 1 to the PRG_RST_ENB bit. If the PRGRESET pin is asserted after it has been enabled as a programmable reset, it causes a programmable reset, which does not reset the SDRAM controller configuration or contents. This allows the contents of SDRAM to be preserved. The PWRGOOD pin always has higher priority than the PRGRESET pin. For example, if the PRGRESET pin is asserted and PWRGOOD deasserted, PWRGOOD is serviced, and the PWRGOOD reset event disables the PRGRESET function. Unlike most other registers, the bits in this register (RESCFG) are only returned to their reset value by a PWRGOOD reset. They are not cleared by any other kind of reset. The AMDebug technology trace information is preserved only if a soft reset is generated to the CPU. See the ElanTMSC520 Microcontroller User's Manual, order #22004, for details about reset generation. Table 3-3 on page 3-6 provides a summary of ELANSC520 microcontroller reset sources and effects. 3-4 ElanTMSC520 Microcontroller Register Set Manual Reset Generation Registers Reset Status (RESSTA) Memory-Mapped MMCR Offset D74h 7 Bit Reset R/W 6 5 4 3 2 SD_RST_ DET 0 R/W! 1 0 Reserved 0 RSV SCP_RST_ ICE_HRST_ ICE_SRST_ WDT_RST_ DET DET DET DET 0 R/W! 0 R/W! 0 R/W! 0 R/W! RGOOD_ PRGRST_ PW DET DET 0 R/W! 1 R/W! Register Description This register provides status information on the various reset sources implemented in the ELANSC520 microcontroller: emulated system control processor (SCP)-generated reset, CPU shutdown, AMDebug technology system reset, AMDebug technology hard reset, watchdog timer, PWRGOOD signal, and PRGRESET signal. Bit Definitions Bit 7 6 Name Reserved SCP_RST_ DET Function Reserved This bit field should be written to 0 for normal system operation. SCP Reset Detect This bit is set when a soft reset is generated by the SCP emulation logic. Software clears this bit by writing a 1. 0 = No SCP reset was detected. 1 = The CPU soft reset event was from an SCP reset command. (See the SCPCMD register description on page 3-8). A soft reset event clears the NMI_ENB bit in the PICICR register (see page 12-4). This allows software to initialize the stack pointer before setting the NMI_ENB bit again after a soft reset. 5 ICE_HRST_ DET AMDebugTM Technology Hard Reset Detect This bit is set when a AMDebug technology hard reset is detected. Software clears this bit by writing a 1. 0 = No AMDebug technology hard reset was detected. 1 = The CPU hard reset event was from an AMDebug technology hard reset. AMDebugTM Technology System Reset Detect This bit is set when an AMDebug technology system reset is detected. Software clears this bit by writing a 1. 0 = No AMDebug technology system reset was detected. 1 = The system reset event was from an AMDebug technology system reset. If the PRG_RST_ENB bit is 1 in the RESCFG register (see page 3-3), an AMDebug technology system reset results in a programmable reset in which the SDRAM configuration is maintained. 4 ICE_SRST_ DET 3 WDT_RST_ DET Watchdog Timer Reset Detect This bit is set when a watchdog timer system reset is detected. Software clears this bit by writing a 1. 0 = No watchdog timer reset was detected. 1 = The system reset event was from a watchdog timer time-out. If the PRG_RST_ENB bit is 1 in the RESCFG register (see page 3-3), a watchdog timer reset results in a programmable reset in which the SDRAM configuration is maintained. ElanTMSC520 Microcontroller Register Set Manual 3-5 Reset Generation Registers Bit 2 Name SD_RST_DET Function CPU Shutdown Reset Detect This bit is set when a CPU shutdown cycle (typically caused by a software "triple-fault") is detected. Software clears this bit by writing a 1. 0 = No CPU shutdown cycle was detected. 1 = The CPU soft reset event was from a shutdown cycle. A soft reset event clears the NMI_ENB bit in the PICICR register (see page 12-4). This allows software to initialize the stack pointer before setting the NMI_ENB bit again after a soft reset. 1 PRGRST_DET PRGRESET Detect This bit is set when a reset from PRGRESET pin is detected. Software clears this bit by writing a 1. 0 = No PRGRESET pin reset was detected. 1 = The system reset event was from the PRGRESET pin. If the PRG_RST_ENB bit is 1 in the RESCFG register (see page 3-3), assertion of the PRGRESET pin while PWRGOOD is asserted results in a programmable reset in which the SDRAM configuration is maintained. 0 PWRGOOD_ DET POWERGOOD Reset Detect This bit is set when a reset from the PWRGOOD pin is detected. Software clears this bit by writing a 1. 0 = No PWRGOOD pin reset was detected. 1 = The system reset event was from the PWRGOOD pin. This reset event has higher priority over PRGRESET and disables the PRGRESET function (if it is enabled) by clearing the PRG_RST_ENB bit in the RESCFG register (see page 3-3). Programming Notes Unlike most other registers, the bits in this register are only returned to their reset value by a PWRGOOD reset. They are not cleared by any other kind of reset. The AMDebug technology trace information is preserved only if a soft reset is generated to the CPU. See the ElanTMSC520 Microcontroller User's Manual, order #22004, for details about reset generation. Table 3-3 provides a summary of ELANSC520 microcontroller reset sources and effects. Table 3-3 Source PWRGOOD pin PRGRESET pin SYS_RST bit, RESCFG register (see page 3-4) Watchdog timer reset event (page 16-2) AMDebug technology system reset CPU_RST bit, SYSCTLA register (page 3-9) SCP soft reset, SCPCMD register (page 3-7) CPU shutdown (typically caused by a triple-fault) GP_RST bit, RESCFG register (page 3-3) PCI_RST bit, HBCTL register (page 6-3) Microcontroller Reset Sources CPU (Hard/Soft) Hard Hard Hard Hard Hard Soft Soft Soft 1,2 2 2 2 3 GPRESET Pin RST Pin (PCI) Internal Registers Notes Notes: 1. The PRG_RST_ENB bit must be set in the RESCFG register (see page 3-3) to enable the reset function on this pin. 2. If the PRG_RST_ENB bit is set, the SDRAM controller configuration is maintained to support system reset in which SDRAM contents are also maintained. 3. Any write of a 1 to the CPU_RST bit causes a soft reset, regardless of whether the bit was previously 1 or 0. 3-6 ElanTMSC520 Microcontroller Register Set Manual Reset Generation Registers SCP Data Port (SCPDATA) Direct-Mapped I/O Address 0060h 7 Bit 6 5 4 SCP_DATA Reserved 3 2 1 0 A20_GATE 0 W! 0 0 1 CPU_RST 0 Reset R/W 0 0 0 Register Description This register is used to emulate system control processor (SCP) a20 gate control. Bit Definitions Bit 7-0 1 Name SCP_DATA A20_GATE Function System Control Processor Data All reads and writes to this port are echoed to the GP bus. A20 Gate Data The ELANSC520 microcontroller has no external input pin for the a20 gate signal that would normally be driven by an external PC/AT-compatible system control processor (SCP). In order to maintain software compatibility, internal logic is provided to watch the GP bus for SCP a20 gate pin control command sequences. Following a write of D1h to the SCPCMD register (see page 3-8), a write to this bit (A20_GATE) has the following effect: 0 = Internal a20 propagation is disabled (address space wraps at 1 Mbyte). 1 = Internal a20 propagation is enabled (addresses above 1 Mbyte can be accessed). This bit (A20_GATE) provides one of two sources of a20 gate control. The other source is the A20G_CTL bit in the SYSCTLA register (see page 3-9). A logical OR of these two sources is used to drive the Am5x86 CPU a20m signal. Therefore, a20 propagates if either source enables a20 to propagate. Note that this bit (A20_GATE) defaults to enabling a20 propagation. 0 CPU_RST CPU Reset Control On the ELANSC520 microcontroller, writing to this bit has no effect. On a PC/AT-compatible system, setting this bit to 1 after a write of D1h to the SCP Command Port (SCPCMD) register would hold the system in reset indefinitely. Programming Notes There is no internal storage element associated with this address. All accesses to this address go to the GP bus. Additionally, writes to this address are snooped by the ELANSC520 microcontroller. ElanTMSC520 Microcontroller Register Set Manual 3-7 Reset Generation Registers SCP Command Port (SCPCMD) Direct-Mapped I/O Address 0064h 7 Bit Reset R/W 6 5 4 SCP_CMD 3 2 1 0 0 0 0 0 W! 0 0 0 0 Register Description This register is used to emulate system control processor (SCP) a20 gate and CPU Reset commands. Bit Definitions Bit 7-0 Name SCP_CMD Function SCP Command The ELANSC520 microcontroller has no external input pins for the a20 gate and CPU reset signals that are normally driven by an external PC/AT-compatible system control processor (SCP). In order to maintain software compatibility, internal logic is provided to watch this port for SCP command sequences. D1h = To control the a20 signal, write the value D1h to this port, then write to the A20_GATE bit of the SCPDATA register (see page 3-7). FEh = To reset the CPU, write the value FEh to this port. This pulses the internal CPU sreset signal, generating a CPU soft reset. The Am5x86 CPU cache state and the ELANSC520 microcontroller MMCR, indexed, and direct-mapped registers are not affected by this soft reset, with the exception that the NMI_ENB bit in the PICICR register is cleared (see page 12-4). Clearing the NMI_ENB bit allows software to initialize the stack pointer before setting the NMI_ENB bit again after a soft reset. Following this reset, the SCP_RST_DET bit in the RESSTA register is set to indicate the source of this reset (see page 3-5). Programming Notes There is no internal storage element associated with this address. All accesses to this address go to the GP bus. Additionally, writes to this address are snooped by the ELANSC520 microcontroller. 3-8 ElanTMSC520 Microcontroller Register Set Manual Reset Generation Registers System Control Port A (SYSCTLA) Direct-Mapped I/O Address 0092h 7 Bit Reset R/W 6 5 Reserved 4 3 2 1 A20G_CTL 0 CPU_RST 0 R/W 0 0 0 RSV 0 0 0 0 R/W Register Description This register is used for fast, alternative control of the CPU soft reset and the a20 signal. Bit Definitions Bit 7-2 1 Name Reserved A20G_CTL Function Reserved This bit field should be written to 0 for normal system operation. A20 Gate Control This bit can be used to cause the same type of masking of the CPU a20 signal that was historically performed by an external system control processor (SCP) in a PC/AT-compatible system, but much faster: 0 = Internal a20 propagation is disabled (address space wraps at 1 Mbyte). 1 = Internal a20 propagation is enabled (addresses above 1 Mbyte can be accessed). This bit (A20G_CTL) provides one of two sources of a20 gate control. The other source is the A20_GATE bit in the SCPDATA register (see page 3-7). A logical OR of these two sources is used to drive the Am5x86 CPU a20m signal. Therefore, a20 propagates if either source enables a20 to propagate. Note that this bit (A20G_CTL) defaults to disabling a20 propagation. However, because the default state of the A20_GATE bit enables a20 propagation, a20 propagates by default. 0 CPU_RST Alternate CPU Core Reset Control Writing a 1 to this bit pulses the internal CPU sreset signal. This causes the same type of CPU soft reset to occur that was historically performed by an external system control processor (SCP) in a PC/AT-compatible system, but much faster. The Am5x86 CPU cache state and ELANSC520 microcontroller MMCR, indexed, and directmapped registers are not affected by this soft reset, with the exception that the NMI_ENB bit in the PICICR register is cleared (see page 12-4). Clearing the NMI_ENB bit allows software to initialize the stack pointer before setting the NMI_ENB bit again after a soft reset. Following the reset, this bit (CPU_RST) remains set until software clears it. This feature can be used by the BIOS as an indication that this bit generated the reset. However, writing a 1 to the CPU_RST bit always generates a soft reset, even if the bit was not cleared after a previous reset. 0 = Do not generate a soft reset to the CPU core. 1 = Pulse the internal CPU sreset signal. Programming Notes Using a read-modify-write operation to change the A20G_CTL bit can cause an unintended soft reset. This happens if the CPU_RST bit has been previously set and not cleared by software. Always write 0 to the CPU_RST bit unless a soft reset is desired. ElanTMSC520 Microcontroller Register Set Manual 3-9 Reset Generation Registers 3-10 ElanTMSC520 Microcontroller Register Set Manual CHAPTER 4 4.1 Am5X86(R) CPU REGISTERS OVERVIEW This chapter describes the Am5x86(R) CPU configuration registers of the ELANSC520 microcontroller. Am5x86 CPU includes a 16-Kbyte unified write-back cache and an integrated floating-point unit (FPU). The Am5x86 CPU operates at 100 or 133 MHz. The Am5x86 CPU configuration register set consists of two memory-mapped configuration region (MMCR) registers used to control some of the Am5x86 CPU features and read the ELANSC520 microcontroller revision ID. See the ElanTMSC520 Microcontroller User's Manual, order #22004, for details about the Am5x86 CPU. Table 4-1 lists the Am5x86 CPU configuration registers in offset order, with the corresponding description's page number. This chapter does not document Am5x86 processor registers. 4.2 Table 4-1 REGISTERS Am5x86(R) CPU MMCR Registers Register Name Am5x86(R) CPU Control Mnemonic CPUCTL MMCR Offset 00h 02h Page Number page 4-2 page 4-3 ELANSC520 Microcontroller Revision ID REVID ElanTMSC520 Microcontroller Register Set Manual 4-1 Am5x86(R) CPU Registers ElanTMSC520 Microcontroller Revision ID (REVID) Memory-Mapped MMCR Offset 00h 15 Bit Reset R/W 14 13 12 11 10 9 8 PRODUCT_ID[7-0] 0 0 0 0 R 7 6 5 4 3 2 1 0 0 0 0 0 Bit Reset R/W MAJORSTEP[3-0] x x R x x x MINORSTEP[3-0] x R x x Register Description This register provides bit fields that identify the AMD microcontroller and its version. These values are hard-wired in the device. Different revisions of a product can be distinguished by the MAJORSTEP and MINORSTEP bit fields. Bit Definitions Bit 15-8 7-4 Name PRODUCT_ID [7-0] MAJORSTEP [3-0] Function Product Type of ElanTMSC520 Microcontroller 00000000 = Identifies the product as the ELANSC520 microcontroller. Major Stepping Level This bit field represents the microcontroller's major revision level. A different MAJORSTEP bit field value is assigned to each major revision of the microcontroller. Minor Stepping Level This bit field represents the microcontroller's minor revision level. A larger MINORSTEP bit field value indicates a later revision within a particular MAJORSTEP bit field level. 3-0 MINORSTEP [3-0] Programming Notes The value that is read back depends on the current major and minor revision level of the specific ELANSC520 microcontroller. Contact your AMD representative for information about available revision levels. 4-2 ElanTMSC520 Microcontroller Register Set Manual Am5x86(R) CPU Registers Am5x86(R) CPU Control (CPUCTL) Memory-Mapped MMCR Offset 02h 7 Bit Reset R/W 6 Reserved 5 4 CACHE_ WR_MODE 3 Reserved 0 RSV 2 1 0 CPU_CLK_SPD[1-0] 0 0 R/W 1 0 0 RSV 0 0 R/W Register Description This register controls the Am5x86 CPU's cache write-back mode and clock speed. Bit Definitions Bit 7-5 4 Name Reserved CACHE_WR_ MODE Function Reserved This bit field should be written to 0 for normal system operation. Cache Write Mode This bit enables the write-back mode of the Am5x86 CPU cache. 0 = Write-back mode (default). 1 =Write-through mode. If this bit is set, the cache operates in write-through mode regardless of the setting of the NW bit in the processor's internal CR0 register, or the PWT bit of the corresponding page table entry. 3-2 1-0 Reserved CPU_CLK_SPD [1-0] Reserved This bit field should be written to 0 for normal system operation. CPU Clock Speed This bit field specifies the clock speed at which the Am5x86 CPU runs. Note that there is a 1 ms delay for the Am5x86 CPU PLL to switch to the new frequency after this bit field is changed. 00 = Reserved 01 = 100 MHz (default) 10 = 133 MHz 11 = Reserved Programming Notes The Am5x86 CPU core is reset during a hard reset, and the Am5x86 CPU core clock frequency defaults to 100 MHz. The Am5x86 CPU core clock frequency remains the same and the cache state and policy are unaffected by a soft reset. See the ElanTMSC520 Microcontroller User's Manual, order #22004, for details about hard and soft resets. Table 3-3 on page 3-6 provides a summary of ELANSC520 microcontroller reset sources and effects. ElanTMSC520 Microcontroller Register Set Manual 4-3 Am5x86(R) CPU Registers 4-4 ElanTMSC520 Microcontroller Register Set Manual CHAPTER 5 5.1 SYSTEM ARBITRATION REGISTERS OVERVIEW This chapter describes the system arbiter registers of the ELANSC520 microcontroller. The ELANSC520 microcontroller's system arbiter controls access to the PCI bus and the internal CPU bus. The system arbiter register set consists of four memory-mapped configuration region (MMCR) registers that provide control and status functions. See the ElanTMSC520 Microcontroller User's Manual, order #22004, for details about the system arbiter. Table 5-1 lists the system arbiter registers in offset order, with the corresponding description's page number. 5.2 Table 5-1 REGISTERS System Arbiter MMCR Registers Register Name System Arbiter Control PCI Bus Arbiter Status System Arbiter Master Enable Arbiter Priority Control Mnemonic SYSARBCTL PCIARBSTA SYSARBMENB ARBPRICTL MMCR Offset 70h 71h 72h 74h Page Number page 5-2 page 5-3 page 5-4 page 5-6 ElanTMSC520 Microcontroller Register Set Manual 5-1 System Arbitration Registers System Arbiter Control (SYSARBCTL) Memory-Mapped MMCR Offset 70h 7 Bit 6 5 Reserved 4 3 2 BUS_ PARK_SEL 1 CNCR_ MODE_ ENB 0 R/W 0 GNT_TO_ INT_ENB 0 R/W Reset R/W 0 0 0 RSV 0 0 0 R/W Register Description This register contains control bits for the CPU bus arbiter and the PCI bus arbiter. Bit Definitions Bit 7-3 2 Name Reserved BUS_PARK_ SEL Function Reserved This bit field should be written to 0 for normal system operation. PCI Bus Arbiter Bus Park This bit controls which PCI master the PCI bus arbiter parks on when the PCI bus is idle. 0 = Park the PCI bus on the Am5x86 CPU. 1 = Park the PCI bus on the last PCI master that acquired the bus. This bit must be 0 when operating in nonconcurrent mode. The BUS_PARK_SEL bit must not be changed except when the PCI bus is currently parked on the Am5x86 CPU. This is the default state after a system reset. See the ElanTMSC520 Microcontroller User's Manual, order #22004, for information about system arbiter initialization. 1 CNCR_MODE_ ENB System Arbiter Concurrent Mode Enable This bit enables the system arbiter to operate in concurrent mode. When operating in nonconcurrent mode, the BUS_PARK_SEL bit must be configured to park on the Am5x86 CPU. 0 = The system arbiter operates in nonconcurrent mode. 1 = The system arbiter operates in concurrent mode. The CNCR_MODE_ENB bit must not be changed except during system arbiter initialization after a system reset. See the ElanTMSC520 Microcontroller User's Manual, order #22004, for information about system arbiter initialization. 0 GNT_TO_INT_ ENB PCI Bus Arbiter Grant Time-Out Interrupt Enable This bit is used to enable interrupts that are generated when the PCI bus arbiter detects a grant time-out. 0 = Disable PCI bus arbiter interrupts. 1 = Enable PCI bus arbiter interrupts. Note that the GNT_TO_STA bit of the PCIARBSTA register (see page 5-3) is set on PCI bus arbiter grant time-outs regardless of the GNT_TO_INT_ENB bit value. This interrupt source shares the interrupt controller input used by any host bridge interrupts enabled in the HBTGTIRQCTL and HBMSTIRQCTL registers (see page 6-5 and page 6-9). Before the GNT_TO_INT_ENB bit is set, the PCIHOSTMAP register (see page 12-17) must be configured to route the interrupt to the appropriate interrupt request level and priority. Programming Notes 5-2 ElanTMSC520 Microcontroller Register Set Manual System Arbitration Registers PCI Bus Arbiter Status (PCIARBSTA) Memory-Mapped MMCR Offset 71h 7 Bit Reset R/W 6 5 Reserved 4 3 2 1 0 GNT_TO_ STA 0 R/W! 0 GNT_TO_ID[3-0] 0 1 1 R 1 1 0 RSV Register Description This register provides grant time-out status of the PCI bus arbiter. Bit Definitions Bit 7 Name GNT_TO_STA Function PCI Bus Arbiter Grant Time-Out Status This bit is set when the PCI bus arbiter detects a grant time-out (transaction not started within 16 clocks of the PCI bus going idle). The GNT that was asserted when this condition occurs can be read in the GNT_TO_ID bit field. 0 = Grant time-out has not occurred. 1 = Grant time-out has occurred. This bit (GNT_TO_STA) is cleared by writing a 1. This bit operates regardless of the corresponding interrupt enable bit (GNT_TO_INT_ENB in the SYSARBCTL register, see page 5-2). When enabled as an interrupt, this source shares the interrupt controller input used by any host bridge interrupts enabled in the HBTGTIRQCTL and HBMSTIRQCTL registers (see page 6-5 and page 6-9). 6-4 3-0 Reserved GNT_TO_ID [3-0] Reserved This bit field should be written to 0 for normal system operation. PCI Bus Arbiter Grant Time-Out Identification This bit field identifies which GNT was asserted when the PCI arbiter detected a grant timeout. This bit field is reset to ones by writing a one to the GNT_TO_STA bit. 0000 = GNT0 was asserted when a grant time-out was detected. 0001 = GNT1 was asserted when a grant time-out was detected. 0010 = GNT2 was asserted when a grant time-out was detected. 0011 = GNT3 was asserted when a grant time-out was detected. 0100 = GNT4 was asserted when a grant time-out was detected. 0101-1101 = Reserved 1110 = The Am5x86 CPU GNT was asserted when a grant time-out was detected. 1111 = No grant time-out was detected, or GNT was asserted when a grant time-out was detected but not latched. Programming Notes ElanTMSC520 Microcontroller Register Set Manual 5-3 System Arbitration Registers System Arbiter Master Enable (SYSARBMENB) Memory-Mapped MMCR Offset 72h 15 Bit Reset R/W 14 13 12 Reserved 11 10 9 8 0 0 0 0 RSV 0 0 0 0 7 Bit Reset R/W 6 Reserved 5 4 3 2 1 0 REQ4_ENB REQ3_ENB REQ2_ENB REQ1_ENB REQ0_ENB 0 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 0 RSV Register Description This register selects the masters that are enabled for arbitration. Bit Definitions Bit 15-5 4 Name Reserved REQ4_ENB Function Reserved This bit field should be written to 0 for normal system operation. PCI Bus Arbiter Request #4 Enable This bit enables the PCI master request connected to the REQ4 pin. If this request is disabled, the PCI bus arbiter does not assert GNT4 to allow the PCI master connected to REQ4 and GNT4 to access the PCI bus. 0 = The PCI master request connected to the REQ4 pin is disabled. 1 = The PCI master request connected to the REQ4 pin is enabled. PCI Bus Arbiter Request #3 Enable This bit enables the PCI master request connected to the REQ3 pin. If this request is disabled, the PCI bus arbiter does not assert GNT3 to allow the PCI master connected to the REQ3 and GNT3 pins to access the PCI bus. 0 = The PCI master request connected to the REQ3 pin is disabled. 1 = The PCI master request connected to the REQ3 pin is enabled. PCI Bus Arbiter Request #2 Enable This bit enables the PCI master request connected to the REQ2 pin. If this request is disabled, the PCI bus arbiter does not assert GNT2 to allow the PCI master connected to the REQ2 and GNT2 pins to access the PCI bus. 0 = The PCI master request connected to the REQ2 pin is disabled. 1 = The PCI master request connected to the REQ2 pin is enabled. PCI Bus Arbiter Request #1 Enable This bit enables the PCI master request connected to the REQ1 pin. If this request is disabled, the PCI bus arbiter does not assert GNT1 to allow the PCI master connected to the REQ1 and GNT1 pins to access the PCI bus. 0 = The PCI master request connected to the REQ1 pin is disabled. 1 = The PCI master request connected to the REQ1 pin is enabled. 3 REQ3_ENB 2 REQ2_ENB 1 REQ1_ENB 5-4 ElanTMSC520 Microcontroller Register Set Manual System Arbitration Registers Bit 0 Name REQ0_ENB Function PCI Bus Arbiter Request #0 Enable This bit enables the PCI master request connected to the REQ0 pin. If this request is disabled, the PCI bus arbiter does not assert GNT0 to allow the PCI master connected to the REQ0 and GNT0 pins to access the PCI bus. 0 = The PCI master request connected to the REQ0 pin is disabled. 1 = The PCI master request connected to the REQ0 pin is enabled. Programming Notes ElanTMSC520 Microcontroller Register Set Manual 5-5 System Arbitration Registers Arbiter Priority Control (ARBPRICTL) Memory-Mapped MMCR Offset 74h 31 Bit Reset R/W 30 29 28 27 Reserved 26 25 24 CPU_PRI[1-0] 0 R/W 23 22 21 20 Reserved 0 0 0 0 RSV 15 14 Reserved 0 0 RSV 7 6 Reserved 0 0 RSV 0 0 1 5 4 0 0 1 13 12 11 0 19 1 0 0 0 0 RSV 18 0 0 17 16 Bit Reset R/W 0 0 0 10 9 8 Bit Reset R/W HI_PRI_1_SEL[3-0] 1 R/W 2 1 R/W 1 1 R/W 0 R/W 3 Bit Reset R/W HI_PRI_0_SEL[3-0] 1 R/W 1 R/W 1 R/W R/W Register Description This register defines priorities for the PCI bus arbiter. Bit Definitions Bit 31-30 Name CPU_PRI[1-0] Function PCI Bus Arbiter CPU Priority This bit field defines the relative Am5x86 CPU PCI master priority. 00 = Reserved. 01 = The Am5x86 CPU is granted the PCI Bus after every one external PCI master cycle. 10 = The Am5x86 CPU is granted the PCI Bus after every two external PCI master cycles. 11 = The Am5x86 CPU is granted the PCI Bus after every three external PCI master cycles. 29-12 Reserved Reserved This bit field should be written to 0 for normal system operation. 5-6 ElanTMSC520 Microcontroller Register Set Manual System Arbitration Registers Bit 11-8 Name HI_PRI_1_SEL [3-0] Function PCI Bus Arbiter High Priority 1 This bit defines which PCI master is in position 1 of the high-priority queue. 0000 = PCI master connected to REQ0 and GNT0 is in position 1 of the high-priority queue. 0001 = PCI master connected to REQ1 and GNT1 is in position 1 of the high-priority queue. 0010 = PCI master connected to REQ2 and GNT2 is in position 1 of the high-priority queue. 0011 = PCI master connected to REQ3 and GNT3 is in position 1 of the high-priority queue. 0100 = PCI master connected to REQ4 and GNT4 is in position 1 of the high-priority queue. 0101-1110 = Reserved. 1111 = No master is in position 1 of the high-priority queue. 7-4 3-0 Reserved HI_PRI_0_SEL [3-0] Reserved This bit field should be written to 0 for normal system operation. PCI Bus Arbiter High Priority 0 This bit defines which PCI master is in position 0 of the high-priority queue. 0000 = PCI master connected to REQ0 and GNT0 is in position 0 of the high-priority queue. 0001 = PCI master connected to REQ1 and GNT1 is in position 0 of the high-priority queue. 0010 = PCI master connected to REQ2 and GNT2 is in position 0 of the high-priority queue. 0011 = PCI master connected to REQ3 and GNT3 is in position 0 of the high-priority queue. 0100 = PCI master connected to REQ4 and GNT4 is in position 0 of the high-priority queue. 0101-1110 = Reserved. 1111 = No master is in position 0 of the high-priority queue. Programming Notes ElanTMSC520 Microcontroller Register Set Manual 5-7 System Arbitration Registers 5-8 ElanTMSC520 Microcontroller Register Set Manual CHAPTER 6 6.1 PCI BUS HOST BRIDGE REGISTERS OVERVIEW This chapter describes the PCI bus host bridge controller registers of the ELANSC520 microcontroller. The ELANSC520 microcontroller includes an integrated PCI bus host bridge controller. The host bridge allows the Am5x86 CPU to generate PCI bus master cycles and allows PCI bus masters to access the ELANSC520 microcontroller's SDRAM. The host bridge register set includes three groups of registers: s Six memory-mapped configuration region (MMCR) registers are used to configure and control most functions specific to the ELANSC520 microcontroller host bridge. s Two direct-mapped I/O addresses are used to access the PCI bus configuration space for both the host bridge and for any other devices present on the PCI bus. s Five host bridge-specific PCI bus indexed registers in the PCI bus configuration space provide the mandatory header registers that are required for any PCI bus device, plus the Master Retry Time-Out register. In addition to the host bridge, the PCI bus can contain several other devices, each with its own PCI configuration space that is also accessed via the two PCI direct-mapped registers. Access from other PCI bus masters to the host bridge registers is not supported. The host bridge implements only those configuration registers that are related to the host bridge functions. See the ElanTMSC520 Microcontroller User's Manual, order #22004, for details about the host bridge controller. Table 6-1, Table 6-2 on page 6-2, and Table 6-3 on page 6-2 list each type of host bridge controller register in offset order with the corresponding description's page number. 6.2 Table 6-1 REGISTERS PCI Bus Host Bridge MMCR Registers Register Name Host Bridge Control Host Bridge Target Interrupt Control Host Bridge Target Interrupt Status Host Bridge Master Interrupt Control Host Bridge Master Interrupt Status Host Bridge Master Interrupt Address Mnemonic HBCTL HBTGTIRQCTL HBTGTIRQSTA HBMSTIRQCTL HBMSTIRQSTA MSTINTADD MMCR Offset 60h 62h 64h 66h 68h 6Ch Page Number page 6-3 page 6-5 page 6-7 page 6-9 page 6-12 page 6-14 ElanTMSC520 Microcontroller Register Set Manual 6-1 PCI Bus Host Bridge Registers Table 6-2 PCI Bus Host Bridge Direct-Mapped Registers Register Name PCI Configuration Address PCI Configuration Data Mnemonic PCICFGADR PCICFGDATA I/O Address 0CF8h 0CFCh Page Number page 6-15 page 6-17 Table 6-3 PCI Bus Host Bridge Indexed Registers Register Name Device/Vendor ID Status/Command Class Code/Revision ID Header Type Master Retry Time-Out Mnemonic PCIDEVID PCISTACMD PCICCREVID PCIHEADTYPE PCIMRETRYTO I/O Address 0CF8h/0CFCh 0CF8h/0CFCh 0CF8h/0CFCh 0CF8h/0CFCh 0CF8h/0CFCh PCI Index Page Number 00h 04h 08h 0Eh 41h page 6-18 page 6-19 page 6-22 page 6-23 page 6-24 6-2 ElanTMSC520 Microcontroller Register Set Manual PCI Bus Host Bridge Registers Host Bridge Control (HBCTL) Memory-Mapped MMCR Offset 60h 15 Bit Reset R/W 14 13 Reserved 12 11 10 T_PURGE_ RD_ENB 9 8 PCI_RST 0 R/W! 7 6 Reserved 0 0 RSV 0 5 0 0 T_DLYTR_ENB[1-0] 0 R/W 1 Reserved 0 0 0 RSV 4 0 0 R/W 3 M_ WPOST_ ENB 2 Bit Reset R/W 0 0 R/W 0 0 RSV 0 Register Description This register contains bit fields for configuring the host bridge controller. Bit Definitions Bit 15 Name PCI_RST Function PCI Bus Reset This bit controls the PCI bus RST signal pin. Reading this bit returns the value that was written to it. 0 = Deassert the PCI bus reset signal. 1 = Assert the PCI bus reset signal. Note that a PCI bus reset affects the host bridge-specific registers in the PCI configuration space. See the PCI-indexed register descriptions beginning on page 6-18. The PCI_RST bit must be cleared only in accordance with the PCI bus specification. 14-11 10 Reserved T_PURGE_ RD_ENB Reserved This bit field should be written to 0 for normal system operation. Target FIFO Purge Enable This bit is provided for data coherency. It forces the host bridge target controller to snoop the target read FIFOs when a PCI bus write transaction occurs. 0 = The target read FIFOs are not snooped during write transactions. 1 = The target read FIFOs are snooped during PCI bus write transactions. The target controller purges any data in the read FIFOs when the write transaction falls within the same cache line for a read or read-line command, or within the same 64 doublewords for a read-multiple command. The T_PURGE_RD_ENB bit must not be changed except during PCI bus initialization after a system reset. See the ElanTMSC520 Microcontroller User's Manual, order #22004, for information about PCI bus initialization. ElanTMSC520 Microcontroller Register Set Manual 6-3 PCI Bus Host Bridge Registers Bit 9-8 Name T_DLYTR_ENB [1-0] Function Automatic Delayed Transaction Enable This bit forces all PCI bus master reads of microcontroller SDRAM to be treated as delayed transactions unless the host bridge has already completed the transaction from a previous request. Setting this bit allows unused PCI bus bandwidth to be used by other PCI bus masters while the read transaction from the first master is being serviced. 00 = PCI bus reads to SDRAM are not automatically retried as delayed transactions. Instead, the originating PCI bus master is held in wait states while the host bridge begins the SDRAM read transaction. If 32 PCI bus clock cycles pass before the first doubleword has been read from SDRAM by the host bridge target controller, the bridge then issues a retry (as required for PCI compliance). 01 = All PCI bus reads to SDRAM are automatically retried as delayed transactions unless the host bridge has already completed the transaction from a previous request. This occurs when a PCI bus master has already issued the transaction previously, and was issued a retry by the host bridge target controller. 10 = Reserved 11 = Reserved 7-4 3 Reserved M_WPOST_ ENB Reserved This bit field should be written to 0 for normal system operation. Master Controller Write Posting Enable This bit enables Am5x86 CPU-to-PCI bus memory write cycles to be posted writes. 0 = Disables Am5x86 CPU-to-PCI bus write posting. 1 = Enables Am5x86 CPU-to-PCI bus write posting. Note that this bit should not be set while the microcontroller is configured for non-concurrent arbitration mode (i.e., while the CNCR_MODE_ENB bit is clear in the SYSARBCTL register, see page page 5-2). 2-0 Reserved Reserved This bit field should be written to 0 for normal system operation. Programming Notes This register is reset by a system reset. The bits in this register are not affected by a PCI bus reset. A PCI bus reset is initiated by setting the PCI_RST bit. 6-4 ElanTMSC520 Microcontroller Register Set Manual PCI Bus Host Bridge Registers Host Bridge Target Interrupt Control (HBTGTIRQCTL) Memory-Mapped MMCR Offset 62h 15 Bit Reset R/W 14 13 Reserved 12 11 10 T_DLYTO_ IRQ_SEL 9 T_APER_ IRQ_SEL 0 R/W 1 T_APER_ IRQ_ENB 0 R/W 8 T_DPER_ IRQ_SEL 0 R/W 0 T_DPER_ IRQ_ENB 0 R/W 0 0 0 RSV 0 0 0 R/W 7 Bit Reset R/W 6 5 Reserved 4 3 2 T_DLYTO_ IRQ_ENB 0 0 0 RSV 0 0 0 R/W Register Description This register contains bit fields for configuring and enabling host bridge target interrupts. Bit Definitions Bit 15-11 10 Name Reserved T_DLYTO_ IRQ_SEL Function Reserved This bit field should be written to 0 for normal system operation. Target Delayed Transaction Time-Out Interrupt Select This bit allows delayed transaction time-outs to generate an NMI instead of a maskable interrupt. 0 = Delayed transaction time-outs generate a maskable interrupt. 1 = Delayed transaction time-outs generate an NMI. Target Address Parity Interrupt Select This bit allows address parity errors detected by the target controller to generate an NMI instead of a maskable interrupt. 0 = Address parity errors generate a maskable interrupt. 1 = Address parity errors generate an NMI. Target Data Parity Interrupt Select This bit allows data parity errors detected by the target controller to generate an NMI instead of a maskable interrupt. 0 = Data parity errors generate a maskable interrupt. 1 = Data parity errors generate an NMI. Reserved This bit field should be written to 0 for normal system operation. Target Delayed Transaction Time-Out Interrupt Enable This bit allows delayed transaction time-outs to generate an interrupt. 0 = Delayed transaction time-outs do not generate an interrupt. 1 = Delayed transaction time-outs generate an interrupt. Target Address Parity Interrupt Enable This bit allows address parity errors detected by the target controller to generate an interrupt. 0 = Address parity errors do not generate an interrupt. 1 = Address parity errors generate an interrupt. 9 T_APER_ IRQ_SEL 8 T_DPER_ IRQ_SEL 7-3 2 Reserved T_DLYTO_ IRQ_ENB 1 T_APER_ IRQ_ENB ElanTMSC520 Microcontroller Register Set Manual 6-5 PCI Bus Host Bridge Registers Bit 0 Name T_DPER_ IRQ_ENB Function Target Data Parity Interrupt Enable This bit allows data parity errors detected by the target controller to generate an interrupt. 0 = Data parity errors do not generate an interrupt. 1 = Data parity errors generate an interrupt. Programming Notes This register is reset by a system reset. The bits in this register are not affected by a PCI bus reset. A PCI bus reset is initiated by setting the PCI_RST bit in the HBCTL register (see page 6-3). Interrupt status bits are set whenever the associated event occurs regardless of the corresponding interrupt enable bit. For a host bridge NMI to propagate to the CPU, host bridge NMIs must be enabled via the PCI_NMI_ENB bit in the PCIHOSTMAP register (see page 12-17), and NMIs must be enabled via the NMI_ENB bit in the PICICR register (see page 12-4). Before host bridge interrupts are enabled, the PCIHOSTMAP register (see page 12-17) must be configured to route the interrupt to the appropriate interrupt request level and priority. The interrupt enabled via the GNT_TO_INT_ENB bit in the SYSARBCTL register (see page 5-2) shares the interrupt controller input used by host bridge interrupts. 6-6 ElanTMSC520 Microcontroller Register Set Manual PCI Bus Host Bridge Registers Host Bridge Target Interrupt Status (HBTGTIRQSTA) Memory-Mapped MMCR Offset 64h 15 Bit Reset R/W 14 Reserved 13 12 11 10 9 8 T_IRQ_ID[3-0] 0 0 1 1 R 5 4 3 2 T_DLYTO_ IRQ_STA 0 0 0 R/W! 1 T_APER_ IRQ_STA 0 R/W! 0 T_DPER_ IRQ_STA 0 R/W! 1 1 0 0 RSV 7 Bit Reset R/W 6 Reserved 0 0 0 RSV Register Description This register contains the host bridge target interrupt status bits and active master identification. Bit Definitions Bit 15-12 11-8 Name Reserved T_IRQ_ID[3-0] Function Reserved This bit field should be written to 0 for normal system operation. Target Interrupt Identification This bit field reports which PCI bus master was active when the target controller detected an error condition (delay transaction time-out, address parity error, data parity error). This bit field is only valid when an interrupt status bit is set. It is reset to 1111b when the interrupt status is cleared. 0000 = PCI bus master 0 was active when the error was detected. 0001 = PCI bus master 1 was active when the error was detected. 0010 = PCI bus master 2 was active when the error was detected. 0011 = PCI bus master 3 was active when the error was detected. 0100 = PCI bus master 4 was active when the error was detected. 1111 = No error was detected or the bus master value was not latched. For example, a bus master value is not latched if multiple interrupts are pending and one interrupt status was cleared. Other =Reserved. When multiple interrupts are pending, this bit field represents the PCI bus master active when the first interrupt occurred, but there is no way for software to detect which interrupt this is. 7-3 2 Reserved T_DLYTO_ IRQ_STA Reserved This bit field should be written to 0 for normal system operation. Target Delayed Transaction Time-Out Interrupt Status This bit is set when the target controller issues a delayed transaction retry, the PCI bus master does not retry the transaction within 2 15 clocks, and the target controller is idle (i.e., no PCI-toSDRAM transaction is active on the PCI bus). 0 = Delayed transaction time-out has not occurred. 1 = Delayed transaction time-out has occurred. This bit is cleared by writing a 1. The target controller discards the delayed transaction request when this bit is set. This bit operates regardless of the corresponding interrupt enable bit (T_DLYTO_IRQ_ENB in the HBTGTIRQCTL register, see page 6-5). ElanTMSC520 Microcontroller Register Set Manual 6-7 PCI Bus Host Bridge Registers Bit 1 Name T_APER_ IRQ_STA Function Target Address Parity Interrupt Status This bit is set when the target controller detects an address parity error. 0 = Address parity error has not occurred. 1 = Address parity error has occurred. This bit is cleared by writing a 1. This bit operates regardless of the corresponding interrupt enable bit (T_APER_IRQ_ENB in the HBTGTIRQCTL register, see page 6-5), or the Parity Error Response bit (PERR_RES in the PCISTACMD register, see page 6-21). 0 T_DPER_ IRQ_STA Target Data Parity Interrupt Status This bit is set when the target controller detects a data parity error. 0 = Data parity error has not occurred. 1 = Data parity error has occurred. This bit is cleared by writing a 1. This bit operates regardless of the corresponding interrupt enable bit (T_DPER_IRQ_ENB in the HBTGTIRQCTL register, see page 6-6), or the Parity Error Response bit (PERR_RES in the PCISTACMD register, see page 6-21). Programming Notes This register is reset by a system reset. The bits in this register are not affected by a PCI bus reset. A PCI bus reset is initiated by setting the PCI_RST bit in the HBCTL register (see page 6-3). 6-8 ElanTMSC520 Microcontroller Register Set Manual PCI Bus Host Bridge Registers Host Bridge Master Interrupt Control (HBMSTIRQCTL) Memory-Mapped MMCR Offset 66h 15 Bit Reset R/W 14 Reserved 13 12 11 10 9 M_RPER_ IRQ_SEL 0 R/W 1 M_RPER_ IRQ_ENB 0 R/W 8 M_DPER_ IRQ_SEL 0 R/W 0 M_DPER_ IRQ_ENB 0 R/W M_RTRTO_ M_TABRT_ M_MABRT_ M_SERR_ IRQ_SEL IRQ_SEL IRQ_SEL IRQ_SEL 0 0 R/W 6 5 0 R/W 4 0 R/W 3 0 R/W 2 0 RSV 7 Bit Reset R/W Reserved 0 RSV 0 M_RTRTO_ M_TABRT_ M_MABRT_ M_SERR_ IRQ_ENB IRQ_ENB IRQ_ENB IRQ_ENB 0 R/W 0 R/W 0 R/W 0 R/W Register Description This register contains bit fields for configuring and enabling host bridge master interrupts. Bit Definitions Bit 15-14 13 Name Reserved M_RTRTO_ IRQ_SEL Function Reserved This bit field should be written to 0 for normal system operation. Master Retry Time-Out Interrupt Select This bit allows master retry time-outs to generate an NMI instead of a maskable interrupt. 0 = Master retry time-outs generate a maskable interrupt. 1 = Master retry time-outs generate an NMI. Master Target Abort Interrupt Select This bit allows master controller transactions that are terminated with a target abort to generate an NMI instead of a maskable interrupt. 0 = Master transactions that are terminated with a master abort generate a maskable interrupt. 1 = Master transactions that are terminated with a master abort generate an NMI. Master Abort Interrupt Select This bit allows master controller transactions that are terminated with a master abort to generate an NMI instead of a maskable interrupt. 0 = Master transactions that are terminated with a master abort generate a maskable interrupt. 1 = Master transactions that are terminated with a master abort generate an NMI. Master System Error Interrupt Select This bit allows the assertion of the system error signal (SERR) to generate an NMI instead of a maskable interrupt. 0 = Assertion of the system error signal generates a maskable interrupt. 1 = Assertion of the system error signal generates an NMI. 12 M_TABRT_ IRQ_SEL 11 M_MABRT_ IRQ_SEL 10 M_SERR_ IRQ_SEL ElanTMSC520 Microcontroller Register Set Manual 6-9 PCI Bus Host Bridge Registers Bit 9 Name M_RPER_ IRQ_SEL Function Master Received Parity Error Interrupt Select This bit allows the assertion of the parity error signal (PERR) during a master controller write transaction or during the address phase of a master controller read transaction to generate an NMI instead of a maskable interrupt. 0 = Master write transactions or master read address phase cycles that detect the parity error signal asserted generate a maskable interrupt. 1 = Master write transactions or master read address phase cycles that detect the parity error signal asserted generate an NMI. 8 M_DPER_ IRQ_SEL Master Detected Parity Error Interrupt Select This bit allows parity errors detected by the master controller during a read transaction to generate an NMI instead of a maskable interrupt. 0 = Master read transactions that detect a parity error generate a maskable interrupt. 1 = Master read transactions that detect a parity error generate an NMI. 7-6 5 Reserved M_RTRTO_ IRQ_ENB Reserved This bit field should be written to 0 for normal system operation. Master Retry Time-Out Interrupt Enable This bit allows master retry time-outs to generate an interrupt. 0 = Master retry time-outs do not generate an interrupt. 1 = Master retry time-outs generate an interrupt. 4 M_TABRT_ IRQ_ENB Master Target Abort Interrupt Enable This bit allows master controller transactions that are terminated with a target abort to generate an interrupt. 0 = Master transactions that are terminated with a target abort do not generate an interrupt. 1 = Master transactions that are terminated with a target abort generate an interrupt. 3 M_MABRT_ IRQ_ENB Master Abort Interrupt Enable This bit allows master controller transactions that are terminated with a master abort to generate an interrupt. 0 = Master transactions that are terminated with a master abort do not generate an interrupt. 1 = Master transactions that are terminated with a master abort generate an interrupt. 2 M_SERR_ IRQ_ENB Master System Error Interrupt Enable This bit allows the assertion of the system error signal (SERR) by a PCI bus agent to generate an interrupt. 0 = Assertion of the system error signal does not generate an interrupt. 1 = Assertion of the system error signal generates an interrupt. 1 M_RPER_ IRQ_ENB Master Received Parity Error Interrupt Enable This bit allows the assertion of the parity error signal (PERR) during a master controller write transaction or during the address phase of a master controller read transaction to generate an interrupt. 0 = Master write transactions or master read address phase cycles that detect the parity error signal asserted do not generate an interrupt. 1 = Master write transactions or master read address phase cycles that detect the parity error signal asserted generate an interrupt. 0 M_DPER_ IRQ_ENB Master Detected Parity Error Interrupt Enable This bit allows parity errors detected by the master controller during a read transaction to generate an interrupt. 0 = Master read transactions that detect a parity error do not generate an interrupt. 1 = Master read transactions that detect a parity error generate an interrupt. Programming Notes This register is reset by a system reset. The bits in this register are not affected by a PCI bus reset. A PCI bus reset is initiated by setting the PCI_RST bit in the HBCTL register (see page 6-3). Interrupt status bits are set whenever the associated event occurs regardless of the corresponding interrupt enable bit. 6-10 ElanTMSC520 Microcontroller Register Set Manual PCI Bus Host Bridge Registers For a host bridge NMI to propagate to the CPU, host bridge NMIs must be enabled via the PCI_NMI_ENB bit in the PCIHOSTMAP register (see page 12-17), and NMIs must be enabled via the NMI_ENB bit in the PICICR register (see page 12-4). Before host bridge interrupts are enabled, the PCIHOSTMAP register (see page 12-17) must be configured to route the interrupt to the appropriate interrupt request level and priority. The interrupt enabled via the GNT_TO_INT_ENB bit in the SYSARBCTL register (see page 5-2) shares the interrupt controller input used by host bridge interrupts. ElanTMSC520 Microcontroller Register Set Manual 6-11 PCI Bus Host Bridge Registers Host Bridge Master Interrupt Status (HBMSTIRQSTA) Memory-Mapped MMCR Offset 68h 15 Bit Reset R/W 14 Reserved 13 12 11 10 9 8 M_CMD_IRQ_ID[3-0] 0 0 0 0 R 5 4 3 2 1 M_RPER_ IRQ_STA 0 R/W! 0 M_DPER_ IRQ_STA 0 R/W! 0 0 0 0 RSV 7 Bit Reset R/W 6 Reserved M_RTRTO_ M_TABRT_ M_MABRT_ M_SERR_ IRQ_STA IRQ_STA IRQ_STA IRQ_STA 0 0 R/W! 0 R/W! 0 R/W! 0 R/W! 0 RSV Register Description This register contains host bridge master controller interrupt status bits and command interrupt identification. Bit Definitions Bit 15-12 11-8 Name Reserved M_CMD_ IRQ_ID[3-0] Function Reserved This bit field should be written to 0 for normal system operation. Master Command Interrupt Identification This bit field reports the command of the transaction during which the master controller detected an error condition. This bit field is valid only when an interrupt status bit is set. It is cleared when the interrupt status is cleared. 0000 = The command was not latched. For example, the command is not latched if multiple interrupts are pending and one interrupt status was cleared. 0001 = Special Cycle (not used by the ELANSC520 microcontroller). 0010 = I/O Read. 0011 = I/O Write. 0100-0101 = Reserved. 0110 = Memory Read. 0111 = Memory Write. 1000-1001 = Reserved. 1010 = Configuration Read. 1011 = Configuration Write. 1100 = Memory Read Multiple (not used by the ELANSC520 microcontroller). 1101 = Dual-Address Cycle (not used by the ELANSC520 microcontroller). 1110 = Memory Read Line (not used by the ELANSC520 microcontroller). 1111 = Memory Write and Invalidate (not used by the ELANSC520 microcontroller). If multiple errors are detected, only the command of the first error is latched. When multiple error interrupts are pending, there is no indication of which interrupt the command corresponds to. The MSTINTADD register (see page 6-14) contains the address of the transaction during which the master controller detected an error condition. 7-6 Reserved Reserved This bit field should be written to 0 for normal system operation. 6-12 ElanTMSC520 Microcontroller Register Set Manual PCI Bus Host Bridge Registers Bit 5 Name M_RTRTO_ IRQ_STA Function Master Retry Time-Out Interrupt Status This bit is set when the master controller retry time-out counter expires. 0 = Master retry time-out has not occurred. 1 = Master retry time-out has occurred. This bit is cleared by writing a 1. This bit operates regardless of the corresponding interrupt enable bit (M_RTRTO_IRQ_ENB in the HBMSTIRQCTL register, see page 6-10). 4 M_TABRT_ IRQ_STA Master Target Abort Interrupt Status This bit is set when a master controller transaction is terminated with a target abort. 0 = Master controller transaction has not been terminated with a target abort. 1 = Master controller transaction has been terminated with a target abort. This bit is cleared by writing a 1. This bit operates regardless of the corresponding interrupt enable bit (M_TABRT_IRQ_ENB in the HBMSTIRQCTL register, see page 6-10). 3 M_MABRT_ IRQ_STA Master Abort Interrupt Status This bit is set when a master controller transaction is terminated with a master abort. 0 = Master controller transaction has not been terminated with a master abort. 1 = Master controller transaction has been terminated with a master abort. This bit is cleared by writing a 1. This bit operates regardless of the corresponding interrupt enable bit (M_MABRT_IRQ_ENB in the HBMSTIRQCTL register, see page 6-10). 2 M_SERR_ IRQ_STA Master System Error Interrupt Status This bit is set when the master controller detects the system error signal asserted. 0 = Master controller has not detected the system error signal asserted. 1 = Master controller has detected the system error signal asserted. This bit is cleared by writing a 1. This bit operates regardless of the corresponding interrupt enable bit (M_SERR_IRQ_ENB in the HBMSTIRQCTL register, see page 6-10). 1 M_RPER_ IRQ_STA Master Received Parity Error Interrupt Status This bit is set when the master controller detects the parity error signal asserted during a master controller write transaction or during the address phase of a master controller read transaction. 0 = Master controller has not detected the parity error signal asserted. 1 = Master controller has detected the parity error signal asserted. This bit is cleared by writing a 1. This bit operates regardless of the corresponding interrupt enable bit (M_RPER_IRQ_ENB in the HBMSTIRQCTL register, see page 6-10). 0 M_DPER_ IRQ_STA Master Detected Parity Error Interrupt Status This bit is set when the master controller detects a parity error during a master controller read transaction. 0 = Master controller has not detected a parity error. 1 = Master controller has detected a parity error. This bit is cleared by writing a 1. This bit operates regardless of the corresponding interrupt enable bit (M_DPER_IRQ_ENB in the HBMSTIRQCTL register, see page 6-10). Programming Notes This register is reset by a system reset. The bits in this register are not affected by a PCI bus reset. A PCI bus reset is initiated by setting the PCI_RST bit in the HBCTL register (see page 6-3). ElanTMSC520 Microcontroller Register Set Manual 6-13 PCI Bus Host Bridge Registers Host Bridge Master Interrupt Address (MSTINTADD) Memory-Mapped MMCR Offset 6Ch 31 Bit Reset R/W 30 29 28 27 26 25 24 M_AD_IRQ_ID[31-24] 0 0 0 0 R 23 22 21 20 19 18 17 16 0 0 0 0 Bit Reset R/W M_AD_IRQ_ID[23-16] 0 0 0 0 R 15 14 13 12 11 10 9 8 0 0 0 0 Bit Reset R/W M_AD_IRQ_ID[15-8] 0 0 0 0 R 7 6 5 4 3 2 1 0 0 0 0 0 Bit Reset R/W M_AD_IRQ_ID[7-0] 0 0 0 0 R 0 0 0 0 Register Description This bit field reports the address of the transaction during which the master controller detected an error condition. Bit Definitions Bit 31-0 Name M_AD_IRQ_ID [31-0] Function Master Address Interrupt Identification This bit field reports the address of the transaction during which the master controller detected an error condition. If multiple errors are detected, only the address of the first error is latched. This bit field is only valid when an interrupt status bit is set. It is cleared when any interrupt status bit is cleared. A value of 00000000h means the address was not latched (unless the error happened to occur at address 00000000h). For example, the address is not latched if multiple interrupts are pending and one interrupt status was cleared. When multiple interrupts are pending, there is no indication of which interrupt the address corresponds to. The M_CMD_IRQ_ID bit field in the HBMSTIRQSTA register (see page 6-12) contains the command of the transaction during which the master controller detected an error condition. Programming Notes This register is reset by a system reset. The bits in this register are not affected by a PCI bus reset. A PCI bus reset is initiated by setting the PCI_RST bit in the HBCTL register (see page 6-3). 6-14 ElanTMSC520 Microcontroller Register Set Manual PCI Bus Host Bridge Registers PCI Configuration Address (PCICFGADR) Direct-Mapped I/O Address 0CF8h 31 Bit Reset R/W 30 29 28 27 Reserved 26 25 24 ENABLE 0 R/W! 23 22 21 20 0 0 0 0 RSV 19 0 0 0 18 17 16 Bit Reset R/W BUS_NUM[7-0] 0 0 0 0 R/W! 15 14 13 DEVICE_NUM[4-0] 0 0 0 R/W! 7 6 5 4 3 2 0 0 0 12 11 10 9 FUNCTION_NUM[2-0] 0 R/W! 1 Reserved 0 0 0 RSV! 0 0 0 8 0 0 0 0 Bit Reset R/W Bit Reset R/W REGISTER_NUM[5-0] 0 0 0 R/W! 0 Register Description This register is used to specify the information to be driven out during the address phase of the next configuration cycle, which is initiated by a subsequent read or write of the PCICFGDATA register (see page 6-17). Bit Definitions Bit 31 Name ENABLE Function Enable 0 = Accesses to the PCICFGDATA register (see page 6-17) are not converted to configuration cycles on the PCI bus. They remain normal I/O cycles. 1 = Accesses to the PCICFGDATA register are converted to configuration cycles on the PCI bus. 30-24 23-16 Reserved BUS_NUM[7-0] Reserved This bit field should be written to 0 for normal system operation. Bus Number This bit field specifies the PCI bus number to which the configuration cycle is addressed. 00h = Specifies the PCI bus that is connected to the ELANSC520 microcontroller's host bridge. This causes the host bridge to perform a type zero configuration cycle. Other values = The host bridge performs a type one configuration cycle. In a type one configuration cycle, the contents of this bit field (BUS_NUM) are driven unchanged on the PCI bus during the address phase of the cycle. If the BUS_NUM and DEVICE_NUM bit fields are both 0, the configuration cycle does not appear on the PCI bus because this combination addresses the internal PCI-indexed registers of the host bridge. ElanTMSC520 Microcontroller Register Set Manual 6-15 PCI Bus Host Bridge Registers Bit 15-11 Name DEVICE_NUM [4-0] Function Device Number This bit field specifies the device to address on the bus that is specified by the BUS_NUM bit field. For type zero configuration cycles (if the BUS_NUM bit field is 00h), the DEVICE_NUM bit field value selects one of the following bit patterns to be driven on the PCI bus AD31-AD11 pins during the address phase of the cycle: 00d = Address the ELANSC520 microcontroller's host bridge (if the BUS_NUM bit field is 00h). The cycle is not visible on the PCI bus. (I.e., no bit pattern is driven externally.) 01d = The AD12 pin is driven High, and the other pins of AD31-AD11 are driven Low. 02d = The AD13 pin is driven High, and the other pins of AD31-AD11 are driven Low. 03d = The AD14 pin is driven High, and the other pins of AD31-AD11 are driven Low. ..... 19d = The AD30 pin is driven High, and the other pins of AD31-AD11 are driven Low. 20d = The AD31 pin is driven High, and the other pins of AD31-AD11 are driven Low. 21-31d = All pins AD31-AD11 are driven Low (to 0); but the host bridge does not accept configuration accesses using these DEVICE_NUM bit field values, so configuration reads or writes with these values result in a Master Abort. Performing a configuration read with these values returns FFFFh in the data. In a typical system design, one of the address pins AD31-AD12 is resistively coupled to each PCI bus device's IDSEL input, so a DEVICE_NUM bit field value in the range 1-20d selects the corresponding PCI bus device during a type zero configuration cycle. For type one configuration cycles (if the BUS_NUM bit field is not 00h), the contents of this bit field are driven unchanged on the PCI bus during the address phase of the cycle. 10-8 FUNCTION_ NUM[2-0] Function Number This bit field specifies the function number within the device specified by the DEVICE_NUM bit field. For host bridge configuration cycles (if the BUS_NUM and DEVICE_NUM bit fields are both 0), the function number is ignored because the host bridge is a single-function device. For all other configuration cycles (type zero or type one), the contents of this bit field are driven unchanged on the PCI bus during the address phase of the configuration cycle. Register Number This bit field specifies the register number within the function specified by the FUNCTION_NUM bit field. For host bridge configuration cycles (if the BUS_NUM and DEVICE_NUM bit fields are both 0), the REGISTER_NUM bit field is used to address the host bridge PCI-indexed registers (see the descriptions beginning on page 6-18). REGISTER_NUM bits 5-0 are used as bits 7-2 of the PCI index address to address doublewords in the configuration space. Byte locations within a doubleword are addressed by accessing the corresponding bytes of the PCICFGDATA register (see page 6-17). For all other configuration cycles (type zero or type one), the contents of this bit field are driven unchanged on the PCI bus during the address phase of the configuration cycle. Reserved This bit field is ignored during writes to this register. It always returns 0 when read. During the address phase of a configuration cycle, address pins AD1-AD0 are driven to 00b to indicate a type zero configuration cycle, or to 01b to indicate a type one configuration cycle, depending on value of the BUS_NUM bit field. 7-2 REGISTER_ NUM[5-0] 1-0 Reserved Programming Notes After this register (PCICFGADR) is written with the requisite information, an access must be made to the PCICFGDATA register (see page 6-17) to cause the PCI bus configuration cycle to occur on the PCI bus. This register is reset by a system reset. The bits in this register are not affected by a PCI bus reset. A PCI bus reset is initiated by setting the PCI_RST bit in the HBCTL register (see page 6-3). This register must be accessed as a doubleword. Accesses that are less than a doubleword in width are treated as normal PCI bus I/O or (if so mapped) GP bus I/O accesses. No configuration cycles are generated if the access is not to the entire doubleword. In the ELANSC520 microcontroller, the doubleword starting at 0CF8h must not be mapped to the GP bus. The ELANSC520 microcontroller does not generate special cycles. In other words, setting the BUS_NUM bit field to 00h, the DEVICE_NUM bit field to 11111b, the FUNCTION_NUM bit field to 111b, and the REGISTER_NUM field to 00000b does not generate a special cycle. Instead, this setup generates a PCI bus configuration write cycle. 6-16 ElanTMSC520 Microcontroller Register Set Manual PCI Bus Host Bridge Registers PCI Configuration Data (PCICFGDATA) Direct-Mapped I/O Address 0CFCh 31 Bit Reset R/W 30 29 28 27 26 25 24 CFG_DATA[31-24] x x x x R/W 23 22 21 20 19 18 17 16 x x x x Bit Reset R/W CFG_DATA[23-16] x x x x R/W 15 14 13 12 11 10 9 8 x x x x Bit Reset R/W CFG_DATA[15-8] x x x x R/W 7 6 5 4 3 2 1 0 x x x x Bit Reset R/W CFG_DATA[7-0] x x x x R/W x x x x Register Description Software reads or writes this register to initiate a PCI bus configuration cycle after setting up the PCICFGADR register (see page 6-15). Bit Definitions Bit 31-0 Name CFG_DATA [31-0] Function Configuration Data This bit field contains the data for the configuration access cycle (read or write). Programming Notes The ENABLE bit must be set in the PCICFGADR register for an access to this register (PCICFGDATA) to result in a PCI bus configuration cycle. Otherwise the cycle accesses the PCI bus I/O space. This register can be accessed as a doubleword, word, or byte. The appropriate CBEx signal combinations are driven on the PCI bus during the data phase of the configuration cycle. In the ELANSC520 microcontroller, the doubleword starting at 0CFCh must not be mapped to the GP bus. ElanTMSC520 Microcontroller Register Set Manual 6-17 PCI Bus Host Bridge Registers Device/Vendor ID (PCIDEVID) I/O Address 0CF8h/0CFCh PCI Index 00h 31 Bit Reset R/W 30 29 28 27 26 25 24 DEV_ID[15-8] 0 0 1 1 R 23 22 21 20 19 18 17 16 0 0 0 0 Bit Reset R/W DEV_ID[7-0] 0 0 0 0 R 15 14 13 12 11 10 9 8 0 0 0 0 Bit Reset R/W VDR_ID[15-8] 0 0 0 1 R 7 6 5 4 3 2 1 0 0 0 0 0 Bit Reset R/W VDR_ID[7-0] 0 0 1 0 R 0 0 1 0 Register Description This register contains the PCI configuration header space vendor and device identification for the ELANSC520 microcontroller host bridge. Bit Definitions Bit 31-16 15-0 Name DEV_ID[15-0] VDR_ID[15-0] Function Device ID 3000h = This bit field identifies the ELANSC520 microcontroller host bridge PCI bus device. Vendor ID 1022h = This bit field identifies Advanced Micro Devices, Inc., as the vendor of the ELANSC520 microcontroller host bridge PCI bus device. Programming Notes This register (PCIDEVID) is register number 0 in the host bridge-specific PCI configuration space. 6-18 ElanTMSC520 Microcontroller Register Set Manual PCI Bus Host Bridge Registers Status/Command (PCISTACMD) I/O Address 0CF8h/0CFCh PCI Index 04h 31 Bit Reset R/W 30 29 R_MST_ ABT 0 R/W! 21 66M_CAP 0 R 13 28 R_TGT_ ABT 0 R/W! 20 27 S_TGT_ ABT 0 R/W! 19 26 25 24 D_PERR_ DET 0 R/W! 16 PERR_DET SIG_SERR 0 R/W! 23 0 R 22 UDFS 0 R 14 S_DVSL_TIM[1-0] 0 R 18 Reserved 1 R 17 Bit Reset R/W FBTB 1 R 15 0 0 0 RSV 0 0 12 Reserved 11 10 9 8 SERR_ENB Bit Reset R/W 0 0 0 0 RSV 0 0 0 0 R 7 Bit Reset R/W 6 PERR_RES 0 R/W 5 4 Reserved 3 2 BUS_MAS 1 MEM_ENB 0 R/W 0 IO_ENB 0 R Reserved 0 RSV 0 0 RSV 0 1 R Register Description This register contains the PCI configuration header space command and status register bits. Bit Definitions Bit 31 Name PERR_DET Function Parity Error Detected This bit is set when a parity error is detected by the host bridge master or target controller. 0 = Parity error not detected. 1 = Parity error detected. This bit is cleared by writing a 1. 30 SIG_SERR Signaled System Error This bit is normally used to indicate that the PCI bus agent has asserted the SERR pin, however the host bridge does not drive SERR because the interrupt logic is integrated within the ELANSC520 microcontroller. 0 = SERR pin not asserted by the host bridge. This bit is internally fixed to 0. ElanTMSC520 Microcontroller Register Set Manual 6-19 PCI Bus Host Bridge Registers Bit 29 Name R_MST_ABT Function Received Master Abort This bit is set by the host bridge master controller when its transaction is terminated with a master abort. 0 = Transaction was not terminated with a master abort. 1 = Transaction was terminated with a master abort. This bit is cleared by writing a 1. 28 R_TGT_ABT Received Target Abort This bit is set by the host bridge master controller when its transaction is terminated with a target abort. 0 = Transaction was not terminated with a target abort. 1 = Transaction was terminated with a target abort. This bit is cleared by writing a 1. 27 S_TGT_ABT Signaled Target Abort This bit is set by the host bridge target controller when it terminates a transaction with a target abort. The host bridge responds with a target abort when an address parity error is detected. 0 = Target controller did not end a transaction with a target abort. 1 = Target controller ended a transaction with a target abort. This bit is cleared by writing a 1. 26-25 S_DVSL_TIM [1-0] Device Select (DEVSEL) Timing These read only bits define the slowest DEVSEL timing for the host bridge target controller. 01 = The host bridge target controller always uses medium DEVSEL timing. This bit field is internally fixed to 01b. 24 D_PERR_DET Data Parity Reported This bit is set by the host bridge master controller when, during a host bridge master controller PCI bus cycle, PERR is asserted by the host bridge or a PCI bus target, and the Parity Error Response bit (PERR_RES in the PCISTACMD register, see page 6-21) is also set. 0 = The master controller did not detect parity error. 1 = The master controller detect parity error. This bit is cleared by writing a 1. 23 FBTB Fast Back-to-Back Capable This read-only bit indicates the host bridge target controller is capable of fast back-to-back transactions. 1 = The host bridge target controller is capable of fast back-to-back transactions. UDF Supported This read-only bit indicates the host bridge does not support user-definable features. 0 = The host bridge does not support user-definable features. 66 MHz Capable This-read only bit indicates the host bridge is not 66-MHz capable. 0 = The host bridge is not 66-MHz capable. Reserved This bit field should be written to 0 for normal system operation. SERR Enable This bit is normally used to enable the PCI bus agent to drive the SERR pin, however the host bridge does not drive the SERR pin because all interrupt control is integrated within the ELANSC520 microcontroller. 0 = The SERR pin is not driven by the ELANSC520 microcontroller. This bit is internally fixed to 0. 7 Reserved Reserved This bit field should be written to 0 for normal system operation. 22 UDFS 21 66M_CAP 20-9 8 Reserved SERR_ENB 6-20 ElanTMSC520 Microcontroller Register Set Manual PCI Bus Host Bridge Registers Bit 6 Name PERR_RES Function Parity Error Response This bit controls the host bridge's response to parity errors. 0 = The host bridge master and target controllers ignore parity errors. The host bridge treats transactions that have a parity error (address or data) as normal transactions. In other words, it behaves as if nothing is wrong. The D_PERR_DET bit (see page 6-20) is not set for data parity errors, and a target abort is not issued for address parity errors. 1 = The host bridge master and target controllers report parity errors. The host bridge responds to data parity errors by setting the D_PERR_DET bit. The host bridge target controller responds to address parity errors by terminating the transaction with a target abort. The PERR_RES bit must not be changed except during PCI bus initialization after a system reset. See the ElanTMSC520 Microcontroller User's Manual, order #22004, for information about PCI bus initialization. 5-3 2 Reserved BUS_MAS Reserved This bit field should be written to 0 for normal system operation. Master Enable This enables the host bridge master controller to generate cycles on the PCI bus. 1 = The host bridge master controller is always enabled. This bit is internally fixed to 1. 1 MEM_ENB Memory Access Enable This bit enables the host bridge target controller to respond to PCI bus master memory cycles. 0 = The host bridge target controller is disabled. 1 = The host bridge target controller is enabled to respond to PCI bus master memory cycles. The MEM_ENB bit must not be changed except during PCI bus initialization after a system reset. See the ElanTMSC520 Microcontroller User's Manual, order #22004, for information about PCI bus initialization. 0 IO_ENB I/O Space Enable This bit is normally used to enable the host bridge target controller to respond to PCI bus master I/O cycles, however the ELANSC520 microcontroller host bridge ignores all I/O cycles from PCI bus masters. 0 = The host bridge does not respond to PCI bus I/O cycles. This bit is internally fixed to 0. Programming Notes This register is reset by a system reset or by a PCI bus reset. A PCI bus reset is initiated by setting the PCI_RST bit in the HBCTL register (see page 6-3). This register (PCISTACMD) is register number 1 in the host bridge-specific PCI configuration space. The PCI Local Bus Specification, Revision 2.2, defines four bit fields in the Status/Command register that are reserved in the ELANSC520 microcontroller. These PCI bus functions do not apply to the host bridge controller: s Wait cycle control (bit 7): the host bridge controller does not support address/data stepping. s VGA palette snoop enable (bit 5): the host bridge is not a graphics device. s Memory write and invalidate enable (bit 4): the host bridge does not generate memory write and invalidate commands as a PCI bus master. s Special cycle recognition (bit 3): the host bridge ignores PCI bus special cycles. ElanTMSC520 Microcontroller Register Set Manual 6-21 PCI Bus Host Bridge Registers Class Code/Revision ID (PCICCREVID) I/O Address 0CF8h/0CFCh PCI Index 08h 31 Bit Reset R/W 30 29 28 27 26 25 24 CL_CD[7-0] 0 0 0 0 R 23 22 21 20 19 18 17 16 0 1 1 0 Bit Reset R/W SBCL_CD[7-0] 0 0 0 0 R 15 14 13 12 11 10 9 8 0 0 0 0 Bit Reset R/W PRG_IF[7-0] 0 0 0 0 R 7 6 5 4 3 2 1 0 0 0 0 0 Bit Reset R/W REV_ID[7-0] 0 0 0 0 R 0 0 0 0 Register Description This register contains the PCI configuration header space class code, program interface and revision identification. Bit Definitions Bit 31-24 Name CL_CD[7-0] Function Base Class Code This bit field defines the PCI bus base class code of the host bridge. 06h = Bridge Device Sub Class Code This bit field defines the PCI bus sub-class code for the host bridge. 00h = Host-PCI bridge Program Interface This bit field defines the PCI bus program interface type of the host bridge. 00h = Host-PCI bridge Revision I.D. This bit field defines the host bridge revision number. 00h = Revision number 23-16 SBCL_CD [7-0] PRG_IF[7-0] 15-8 7-0 REV_ID[7-0] Programming Notes This register (PCICCREVID) is register number 2 in the host bridge-specific PCI configuration space. 6-22 ElanTMSC520 Microcontroller Register Set Manual PCI Bus Host Bridge Registers Header Type (PCIHEADTYPE) I/O Address 0CF8h/0CFCh PCI Index 0Eh 7 Bit Reset R/W 6 5 4 3 2 1 0 HDR_TYP[7-0] 0 0 0 0 R 0 0 0 0 Register Description This register contains the PCI configuration header space header type. Bit Definitions Bit 7-0 Name HDR_TYP [7-0] Function Header Type This bit field defines the PCI configuration space header format. 00h = Single-function device, not PCI-to-PCI bridge Programming Notes This register (PCIHEADTYPE) is byte 2 of register number 3 in the host bridge-specific PCI configuration space. ElanTMSC520 Microcontroller Register Set Manual 6-23 PCI Bus Host Bridge Registers Master Retry Time-Out (PCIMRETRYTO) I/O Address 0CF8h/0CFCh PCI Index 41h 3 2 1 0 7 Bit Reset R/W 6 5 4 M_RETRY_TO[7-0] 0 0 0 0 R 0 0 0 0 Register Description This register contains the PCI master retry time-out. Bit Definitions Bit 7-0 Name M_RETRY_TO [7-0] Function Master Retry Time-Out This bit field defines the number of times the master controller retries a transaction before aborting the cycle. For read transactions that are aborted due to a time-out, a data value of FFFFFFFFh is returned to the Am5x86 CPU. 00h = Retry time-out disabled. The master controller continues to retry the transaction until the target responds. This is the default value. Other = The master controller continues to retry the transaction for the number of times programmed into this bit field. For example, if this bit field is set to 80h, the number of retries is 128. Therefore the total number of attempts (including the initial attempt) is the number of retries programmed in this bit field plus 1. Programming Notes This register is reset by a system reset or by a PCI bus reset. A PCI bus reset is initiated by setting the PCI_RST bit in the HBCTL register (see page 6-3). This register (PCIMRETRYTO) is byte 1 of register number 16d in the host bridge-specific PCI configuration space. This register must not be changed except when there is no outstanding CPU-to-PCI bus transaction pending. This is the default state after a system reset. See the ElanTMSC520 Microcontroller User's Manual, order #22004, for information about PCI bus initialization. 6-24 ElanTMSC520 Microcontroller Register Set Manual CHAPTER 7 7.1 SDRAM CONTROLLER REGISTERS OVERVIEW This chapter describes the synchronous dynamic random-access memory (SDRAM) controller registers of the ELANSC520 microcontroller. The ELANSC520 microcontroller includes an integrated SDRAM controller. The following are some of the SDRAM controller's main features: s Synchronous DRAM support s Support for up to 4 banks s Up to 256 Megabytes of SDRAM s ECC (single-bit correction/multiple-bit detection) support The SDRAM controller register set consists of ten memory-mapped configuration region (MMCR) registers used for configuration, control, and status. See the ElanTMSC520 Microcontroller User's Manual, order #22004, for details about using the SDRAM controller. Table 7-1 lists the SDRAM controller registers in offset order, with the corresponding description's page number. 7.2 Table 7-1 REGISTERS SDRAM Controller MMCR Registers Register Name SDRAM Control SDRAM Timing Control SDRAM Bank Configuration SDRAM Bank 0-3 Ending Address ECC Control ECC Status ECC Check Bit Position ECC Check Code Test ECC Single-Bit Error Address ECC Multi-Bit Error Address Mnemonic DRCCTL DRCTMCTL DRCCFG DRCBENDADR ECCCTL ECCSTA ECCCKBPOS ECCCKTEST ECCSBADD ECCMBADD MMCR Offset 10h 12h 14h 18h 20h 21h 22h 23h 24h 28h Page Number page 7-2 page 7-4 page 7-5 page 7-7 page 7-9 page 7-10 page 7-11 page 7-12 page 7-14 page 7-15 ElanTMSC520 Microcontroller Register Set Manual 7-1 SDRAM Controller Registers SDRAM Control (DRCCTL) Memory-Mapped MMCR Offset 10h 7 Bit Reset R/W 6 Reserved 0 RES 5 4 3 RFSH_ENB 0 R/W 2 1 OPMODE_SEL[2-0] 0 WB_TST_ ENB 0 R/W! RFSH_SPD[1-0] 0 R/W 1 0 0 R/W 0 Register Description This register controls various features of the SDRAM controller. Note: A programmable reset preserves this register's state. See the PRG_RST_ENB bit description on page 3-3. Bit Definitions Bit 7 Name WB_TST_ ENB Function Write Buffer Test Mode Enable This bit selects the source of the debugging information available on the three system test pins. 0 = Write buffer test mode is disabled. (System test mode.) The three system test pins function as CF_DRAM, DATASTRB and CF_ROM_GPCS pins. 1 = Write buffer test mode is enabled. The three system test pins function as WBMSTR2- WBMSTR0 for write buffer master trace purposes. If the write buffer is enabled (WB_ENB is set in the DBCTL register, see page 8-3), the WBMSTR2-WBMSTR0 signals provide write buffer master trace information during write cycles from the write buffer to SDRAM. Master trace information specifies which masters contributed to the level (rank) that is currently being written to SDRAM from the write buffer. Contributing masters can be one or more of: Am5x86 CPU, PCI, or GP bus DMA. If the write buffer is disabled, or during read cycles if the write buffer is enabled, the WBMSTR2-WBMSTR0 signals reflect the master that is currently requesting SDRAM access. Software writes to this bit are ignored when the AMDebugTM technology mode is active. This ensures that microcontroller software cannot remove control of the pins from the software driving the AMDebug technology port. If AMDebug technology mode is not active, software can write to this bit. Refer to the ElanTMSC520 Microcontroller User's Manual, order #22004, for more information about system test mode and write buffer test mode. 6 5-4 Reserved RFSH_SPD [1-0] Reserved This bit field should be written to 0 for normal system operation. SDRAM Refresh Request Speed These two bits determine the SDRAM refresh request rate. 00 = 7.8 ms 01 = 15.6 ms (default) 10 = 31.2 ms 11 = 62.5 ms 3 RFSH_ENB Refresh Enable 0 = SDRAM refresh is disabled. This mode should be used for SDRAM detection and sizing algorithms. Disabling SDRAM refresh should not be done in normal operation. 1 = SDRAM refresh is enabled. Note: Refresh cycles are not generated to SDRAM banks that are not enabled via the BNKx_ENB bits in the DRCBENDADR register (see page 7-7). 7-2 ElanTMSC520 Microcontroller Register Set Manual SDRAM Controller Registers 2-0 OPMODE_SEL [2-0] SDRAM Operation Mode Select These commands are used in the SDRAM initialization and detection algorithm. 000 = Normal SDRAM mode. 001 = NOP command enabled. 010 = CPU-to-SDRAM cycles are converted to All Banks Precharge commands. 011 = CPU-to-SDRAM cycles are converted to a Load Mode Register command. The data to be loaded is driven on MA12-MA0. 100 = Auto refresh enabled. 101-111 = Reserved. When specifying NOP, All Banks Precharge, Load Mode Register, or Auto Refresh commands, the command is not actually applied to the SDRAM devices until a CPU access to SDRAM occurs (either a read or write cycle). The specified command is issued to the SDRAM devices during the CPU access rather than the typical SDRAM read or write access. Before using a write cycle to apply any of these SDRAM commands, make sure the WB_ENB bit is clear in the DBCTL register (see page 8-3). Because the command is not issued to the SDRAM until the CPU accesses SDRAM, code executing out of ROM must specifically access SDRAM after selecting a command in the OPMODE_SEL bit field to properly configure the SDRAM device. The Load Mode Register command must be issued to the SDRAM for the setting of the CAS_LAT bit of the DRCTMCTL register to take effect (see page 7-4). In addition to setting the CAS latency as programmed in the CAS_LAT bit, the following fixed parameters are also written to the SDRAM device's mode register when a Load Mode Register command is issued. s Burst length: always read burst 4. s s s Burst type: follow non-linear burst. Operating mode: standard operation. Write burst mode: single mode. After a command is issued, the OPMODE_SEL bit field must be cleared to 000b (normal SDRAM mode) before any further SDRAM access. Programming Notes SDRAM refresh cycles should only be enabled (via the RFSH_ENB bit) when the OPMODE_SEL bit is 000b. This register (DRCCTL) should be modified only when the write buffer and the read-ahead feature of the read buffer are disabled in the DBCTL register (see page 8-3). ElanTMSC520 Microcontroller Register Set Manual 7-3 SDRAM Controller Registers SDRAM Timing Control (DRCTMCTL) Memory-Mapped MMCR Offset 12h 7 Bit Reset R/W 6 Reserved 5 4 CAS_LAT 3 2 1 0 RAS_PCHG_DLY[1-0] 1 R/W 0 RAS_CAS_DLY[1-0] 1 R/W 0 0 0 RSV 0 1 R/W Register Description This register controls the SDRAM device timing. Note: A programmable reset preserves this register's state. See the PRG_RST_ENB bit description on page 3-3. Bit Definitions Bit 7-5 4 Name Reserved CAS_LAT Function Reserved This bit field should be written to 0 for normal system operation. SDRAM CAS Latency This bit controls the SCASx signal latency timing to all the SDRAM banks. 0 = Cycle latency is 2T. 1 = Cycle latency is 3T (default). Where T is 15 ns (one half of the 33-MHz clock cycle). To make the CAS_LAT bit setting take effect, a Load Mode Register command must be issued to the SDRAM devices via the OPMODE_SEL bit field of the DRCCTL register (see page 7-3). Incorrect operation can occur if the CAS_LAT bit is modified and the Load Mode Register command is not issued to the SDRAM devices. 3-2 RAS_PCHG_ DLY[1-0] SDRAM RAS Precharge Delay This bit field determines the SRASx signal precharge delay. 00 = 2T 01 = 3T 10 = 4T (default) 11 = 6T Where T is 15 ns (one half of the 33-MHz clock cycle). 1-0 RAS_CAS_ DLY[1-0] SDRAM RAS-to-CAS Delay This bit field determines the SRASx-to-SCASx delay. 00 = 2T 01 = 3T 10 = 4T (default) 11 = Reserved Where T is 15 ns (one half of the 33-MHz clock cycle). Programming Notes This register (DRCTMCTL) should be modified only when the write buffer and the read-ahead feature of the read buffer are disabled in the DBCTL register (see page 8-3). 7-4 ElanTMSC520 Microcontroller Register Set Manual SDRAM Controller Registers SDRAM Bank Configuration (DRCCFG) Memory-Mapped MMCR Offset 14h 15 Bit Reset R/W 14 Reserved 0 RSV 6 Reserved 0 RSV 13 12 11 BNK2_ BNK_CNT 0 R/W 10 Reserved 0 RSV 2 Reserved 0 RSV 9 8 BNK3_ BNK_CNT 0 R/W 7 BNK3_COLWDTH[1-0] 0 R/W 5 4 0 BNK2_COLWDTH[1-0] 0 R/W 1 0 0 3 BNK0_ BNK_CNT 0 R/W Bit Reset R/W BNK1_ BNK_CNT 0 R/W BNK1_COLWDTH[1-0] 0 R/W 0 BNK0_COLWDTH[1-0] 0 R/W 0 Register Description This register controls the address column width configuration and SDRAM internal bank count for devices installed in each bank. Note: A programmable reset preserves this register's state.See the PRG_RST_ENB bit description on page 3-3. Bit Definitions Bit 15 Name BNK3_BNK_ CNT Function Bank 3 Internal SDRAM Bank Count This bit specifies the number of internal banks supported by the SDRAM devices. 0 = 2-bank device 1 = 4-bank device Reserved This bit field should be written to 0 for normal system operation. Bank 3 Column Address Width These two bits specify the column address width of the SDRAM devices populated in Bank 3. 00 = 8-bit column address 01 = 9-bit column address 10 = 10-bit column address 11 = 11-bit column address 14 13-12 Reserved BNK3_ COLWDTH[1-0] 11 BNK2_BNK_ CNT Bank 2 Internal SDRAM Bank Count This bit specifies the number of internal banks supported by the SDRAM devices. 0 = 2-bank device 1 = 4-bank device Reserved This bit field should be written to 0 for normal system operation. Bank 2 Column Address Width These two bits specify the column address width of the SDRAM devices populated in Bank 2. 00 = 8-bit column address 01 = 9-bit column address 10 = 10-bit column address 11 = 11-bit column address 10 9-8 Reserved BNK2_ COLWDTH[1-0] ElanTMSC520 Microcontroller Register Set Manual 7-5 SDRAM Controller Registers Bit 7 Name BNK1_BNK_ CNT Function Bank 1 Internal SDRAM Bank Count This bit specifies the number of internal banks supported by the SDRAM devices. 0 = 2-bank device 1 = 4-bank device 6 5-4 Reserved BNK1_ COLWDTH[1-0] Reserved This bit field should be written to 0 for normal system operation. Bank 1 Column Address Width These two bits specify the column address width of the SDRAM devices populated in Bank 1. 00 = 8-bit column address 01 = 9-bit column address 10 = 10-bit column address 11 = 11-bit column address 3 BNK0_BNK_ CNT Bank 0 Internal SDRAM Bank Count This bit specifies the number of internal banks supported by the SDRAM devices. 0 = 2-bank device 1 = 4-bank device 2 1-0 Reserved BNK0_ COLWDTH[1-0] Reserved This bit field should be written to 0 for normal system operation. Bank 0 Column Address Width These two bits specify the column address width of the SDRAM devices populated in Bank 0. 00 = 8-bit column address 01 = 9-bit column address 10 = 10-bit column address 11 = 11-bit column address Programming Notes This register (DRCCFG) should be modified only when the write buffer and the read-ahead feature of the read buffer are disabled in the DBCTL register (see page 8-3). Before changing the BNKx_BNK_CNT or BNKx_COLWDTH bit fields, software must issue an All Banks Precharge command to the SDRAM devices via the OPMODE_SEL bit field in the DBCCTL register (see page 7-3). This command returns the SDRAM devices to an idle state and also clears the SDRAM controller's page table entries. 7-6 ElanTMSC520 Microcontroller Register Set Manual SDRAM Controller Registers SDRAM Bank 0-3 Ending Address (DRCBENDADR) Memory-Mapped MMCR Offset 18h 31 Bit Reset R/W 30 29 28 27 BNK3_END[28-22] 26 25 24 BNK3_ENB 0 R/W 23 22 21 20 0 0 0 0 R/W 19 BNK2_END[28-22] 0 0 0 18 17 16 Bit Reset R/W BNK2_ENB 0 R/W 15 14 13 12 0 0 0 0 R/W 11 BNK1_END[28-22] 0 0 0 10 9 8 Bit Reset R/W BNK1_ENB 0 R/W 7 6 5 4 0 0 0 0 R/W 3 BNK0_END[28-22] 0 0 0 2 1 0 Bit Reset R/W BNK0_ENB 0 R/W 0 0 0 0 R/W 0 0 0 Register Description This register controls the SDRAM bank enable and bank ending address that specifies the boundary between the banks. Note: A programmable reset preserves this register's state.See the PRG_RST_ENB bit description on page 3-3. Bit Definitions Bit 31 Name BNK3_ENB Function Bank 3 Enable This bit enables Bank 3. 0 = Disabled 1 = Enabled Bank 3 Ending Address This bit field determines the Bank 3 boundary, defined in 4-Mbyte increments. This value is compared to physical address bits 28-22 during an SDRAM request to select a bank. Bank 3 is selected if physical address bits 28-22 are less than the BNK3_END bit field value, but greater than or equal to the value specified by the BNK2_END bit field (or the next lower enabled bank's end value if Bank 2 is disabled). 30-24 BNK3_END [28-22] 23 BNK2_ENB Bank 2 Enable This bit enables Bank 2. 0 = Disabled 1 = Enabled ElanTMSC520 Microcontroller Register Set Manual 7-7 SDRAM Controller Registers Bit 22-16 Name BNK2_END [28-22] Function Bank 2 Ending Address This bit field determines the Bank 2 boundary, defined in 4-Mbyte increments. This value is compared to physical address bits 28-22 during an SDRAM request to select a bank. Bank 2 is selected if physical address bits 28-22 are less than the BNK2_END bit field value but greater than or equal to the value specified by the BNK1_END bit field (or the next lower enabled bank's end value if Bank 1 is disabled. 15 BNK1_ENB Bank 1 Enable This bit enables Bank 1. 0 = Disabled 1 = Enabled 14-8 BNK1_END [28-22] Bank 1 Ending Address This bit field determines the Bank 1 boundary, defined in 4-Mbyte increments. This value is compared to physical address bits 28-22 during an SDRAM request to select a bank. Bank 1 is selected if physical address bits 28-22 are less than the BNK1_END bit field value but greater than or equal to the value specified by the BNK0_END bit field (or 0 if Bank 0 is disabled). 7 BNK0_ENB Bank 0 Enable This bit enables Bank 0. 0 = Disabled 1 = Enabled 6-0 BNK0_END [28-22] Bank 0 Ending Address This bit field determines the Bank 0 boundary, defined in 4-Mbyte increments. This value is compared to physical address bits 28-22 during an SDRAM request to select a bank. Bank 0 is selected if physical address bits 28-22 are less than the BNK0_END bit field value. Programming Notes This register (DRCBENDADR) should be modified only when the write buffer and the read-ahead feature of the read buffer are disabled in the DBCTL register (see page 8-3). The value specified in each BNKx_END bit field determines the upper address boundary of the corresponding SDRAM bank in 4Mbyte increments. Each bank's lower boundary is determined by the end of the next-lower enabled bank, so the addressable SDRAM space is the concatenation of the enabled banks. The top of the highest configured bank is the top of memory. If any particular bank is disabled (via its BNKx_ENB bit), the associated BNKx_END bit field value has no effect. Banks do not have to be enabled contiguously. Figure 7-1 gives a few examples of SDRAM bank configuration. Figure 7-1 Examples of Bank Ending Address Configuration Example 1 1FFFFFFh Bank 3 Bank 2 Bank 1 Bank 0 Total (8 Mbytes) BNK3_END Example 2 37FFFFFh (32 Mbytes) BNK3_END Example 3 BFFFFFFh (64 Mbytes) BNK3_END 1800000h 17FFFFFh (8 Mbytes) = 08h BNK2_END 1800000h Disabled (BNK2_ENB = 0) = 0Eh BNK2_END = "Don't Care" 8000000h 7FFFFFFh (64 Mbytes) = 30h BNK2_END 1000000h FFFFFFh (8 Mbytes) = 06h BNK1_END 17FFFFFh (8 Mbytes) BNK1_END 4000000h 3FFFFFFh (32 Mbytes) = 20h BNK1_END 800000h 7FFFFFh (8 Mbytes) = 04h BNK0_END 1000000h FFFFFFh (16 Mbytes) = 06h BNK0_END 2000000h 1FFFFFFh (32 Mbytes) = 10h BNK0_END 000000h = 02h 000000h = 04h 0000000h = 08h 32 Mbytes 56 Mbytes 192 Mbytes 7-8 ElanTMSC520 Microcontroller Register Set Manual SDRAM Controller Registers ECC Control (ECCCTL) Memory-Mapped MMCR Offset 20h 7 Bit Reset R/W 6 5 Reserved 4 3 2 1 0 ECC_ENB 0 R/W MULT_INT_ SGL_INT_ ENB ENB 0 0 0 R/W 0 R/W 0 0 0 RSV Register Description This register controls all the error correction code (ECC) functions. Note: A programmable reset preserves this register's state.See the PRG_RST_ENB bit description on page 3-3. Bit Definitions Bit 7-3 2 Name Reserved MULT_INT_ ENB Function Reserved This bit field should be written to 0 for normal system operation. Enable Multi-Bit Interrupt This bit enables the ECC non-maskable interrupt (NMI) source to go active on the detection of a multi-bit error. 0 = Disabled 1 = Enabled The ECC NMI source must also be enabled via the ECC_NMI_ENB bit in the ECCMAP register (see page 12-19). 1 SGL_INT_ ENB Enable Single-bit Interrupt This bit enables the ECC maskable interrupt source to go active on the detection of a singlebit error. 0 = Disabled 1 = Enabled The ECC single-bit interrupt source must also be mapped to an interrupt channel via the ECC_IRQ_MAP bit field in the ECCMAP register (see page 12-20). 0 ECC_ENB ECC Enable for All Four Banks This bit enables ECC for all four banks. 0 = Disabled 1 = Enabled When ECC is enabled, writes to SDRAM include a write of the error correction code (ECC) to the SDRAM device's ECC location, and reads from SDRAM are checked for a correct ECC. Any ECC mismatch is reported in the appropriate registers and the appropriate interrupt is generated if enabled via the MULT_INT_ENB and SGL_INT_ENB bits. Programming Notes This register (ECCCTL) should be modified only when the write buffer and the read-ahead feature of the read buffer are disabled in the DBCTL register (see page 8-3). Before ECC multi-bit or single-bit interrupts are enabled, the ECCMAP register (see page 12-19) must be configured to route the interrupt to the appropriate interrupt request level and priority. ElanTMSC520 Microcontroller Register Set Manual 7-9 SDRAM Controller Registers ECC Status (ECCSTA) Memory-Mapped MMCR Offset 21h 7 Bit Reset R/W 6 5 Reserved 4 3 2 1 MBIT_ERR 0 SBIT_ERR 0 R/W! 0 0 0 RSV 0 0 0 0 R/W! Register Description This register maintains status of the ECC functions if ECC is enabled. Note: A programmable reset does not preserve this register's state. Bit Definitions Bit 7-2 1 Name Reserved MBIT_ERR Function Reserved This bit field should be written to 0 for normal system operation. Multi-Bit Error Detected 0 = The event has not occurred, or software cleared this bit by writing a 1. 1 = A multi-bit ECC error has occurred. Software must write a 1 to clear this bit and rearm the logic that captures the physical address where the multi-bit error occurred. The multi-bit error physical address can be read from the ECCMBADD register (see page 7-15). 0 SBIT_ERR Single-bit ECC Error 0 = The event has not occurred, or software cleared this bit by writing a 1. 1 = A single-bit ECC error has occurred. Software must write a 1 to clear this bit and rearm the logic that captures the physical address and bit position where the single-bit error occurred. The single-bit error physical address can be read from the ECCSBADD register (see page 7-14). The single-bit error bit position can be read from the ECCCKBPOS register (see page 7-11). Programming Notes Software should write to this register (ECCSTA) only to clear the error status, and only after a status bit was read as 1. 7-10 ElanTMSC520 Microcontroller Register Set Manual SDRAM Controller Registers ECC Check Bit Position (ECCCKBPOS) Memory-Mapped MMCR Offset 22h 7 Bit Reset R/W 6 Reserved 5 4 3 2 1 0 ECC_CHK_POS[5-0] 0 0 0 0 R 0 0 0 0 RSV Register Description This register indicates the particular bit in the 32-bit data word or 7-bit check word that caused the single-bit error. Note: A programmable reset does not preserve this register's state. Bit Definitions Bit 7-6 5-0 Name Reserved ECC_CHK_ POS[5-0] Function Reserved This bit field should be written to 0 for normal system operation. ECC Data Bit Position This bit field reports the bit location of the single-bit ECC error in either the check bit or data bit field. The bit position is captured upon the detection of a single-bit error, and the bit field is inhibited from capturing subsequent error positions until the SBIT_ERR bit in the ECCSTA register is cleared by writing a 1 (see page 7-10). The data bit field is 32 bits in length and the check bit field is 7 bits in length. Combined, these two bit fields form a 39-bit word. The ECC_CHK_POS bit field contains the numbered bit position in this 39-bit word of the bit that caused the single-bit error. Figure 7-2 relates the encoded bit position to the data and check bit fields. Programming Notes Figure 7-2 shows the concatenated check and data bit fields, and the corresponding ECC_CHK_POS values. Bit 5 of THE ECC_CHK_POS bit field can be used to identify whether the check bit field or the data bit field contains the bit error. If bit 5 is 0, the error is in the data bit field. If bit 5 is 1, the error is in the check bit field. Figure 7-2 ECC Check Bit and Data Bit Positions Check Bits (7-bit) Data Bits (32-bit) 6 0 31 0 0 38 32 31 ECC_CHK_POS Values ElanTMSC520 Microcontroller Register Set Manual 7-11 SDRAM Controller Registers ECC Check Code Test (ECCCKTEST) Memory-Mapped MMCR Offset 23h 7 Bit Reset R/W 6 5 4 3 FRC_BAD_CHK[6-0] 2 1 0 BAD_CHK_ ENB 0 R/W! 0 0 0 0 R/W 0 0 0 Register Description This register provides user control of the ECC check code that is written during an SDRAM write cycle. This feature is to be used for test and error-handler development. Note: A programmable reset does not preserve this register's state. Bit Definitions Bit 7 Name BAD_CHK_ ENB Function Enable Bad ECC Check Bits This bit can be used by test software to enable the FRC_BAD_CHK bit field to replace the correct ECC codes generated by the ELANSC520 microcontroller ECC logic for only the next single write cycle to SDRAM. 0 = The FRC_BAD_CHK bit field does not replace the generated check bits. The binary pattern in the FRC_BAD_CHK bit field has no effect on the ECC codes written to SDRAM during a write cycle. 1 = The FRC_BAD_CHK bit field replaces the generated check bits for the next SDRAM write. The binary pattern written to the FRC_BAD_CHK bit field is written out as the 7-bit ECC code during the next write cycle to SDRAM. This bit is automatically reset after the FRC_BAD_CHK bit field value is written to the ECC SDRAM during the following write cycle. If this bit (BAD_CHK_ENB) was previously set, then reading 1 from this bit implies that a write cycle to SDRAM did not occur yet, and so the FRC_BAD_CHK bit field value was not yet applied. If the BAD_CHK_ENB bit is read as a 0 after it was previously set, then a write cycle did occur in which the FRC_BAD_CHK bit field value was applied. 6-0 FRC_BAD_ CHK[6-0] Force Bad ECC Check Bits This register provides a way for users to specify their own ECC code for error test purposes. During write cycles to SDRAM, a 7-bit encoded ECC check code (sometimes referred to as a syndrome code) that represents the associated write data is written to ECC SDRAM. This code is automatically generated by the ELANSC520 microcontroller when ECC is enabled. If the BAD_CHK_ENB bit is set, the pattern in the FRC_BAD_CHK bit field is written to the ECC storage location on the following write cycle to SDRAM. Note: The write buffer should be disabled and the write access should not be cacheable in the Am5x86 CPU write-back cache during this procedure to ensure that the write cycle is propagated to the SDRAM when intended. The write buffer is disabled via the WB_ENB bit in the DBCTL register (see page 8-3).The write can be made non-cacheable, among other ways, by putting the cache in write-through mode or by disabling the cache completely. Programming Notes During a master write access to SDRAM, the ELANSC520 microcontroller generates an ECC check code (sometimes referred to as a syndrome code) that is written to the ECC SDRAM devices. During a read cycle, the requested data is read from SDRAM along with the stored ECC check code. A new check code is then generated from the read data and compared to the read ECC check code. 7-12 ElanTMSC520 Microcontroller Register Set Manual SDRAM Controller Registers If there is an ECC mismatch, either a single-bit or multiple-bit error has been detected. Single-bit errors are corrected as data is returned to the requesting master (and an interrupt is generated if enabled). Multi-bit errors are not corrected, but an NMI is generated if enabled. This register (ECCCKTEST) provides a way for the user to alter the ECC check code that is written to the ECC SDRAM. If the ECC check code is altered so that it reflects a single-bit or multiple-bit error, it is detected by the ELANSC520 microcontroller when that location is read (if ECC is enabled). This feature can be used for test purposes and also for ECC error-handler development. Because the write buffer decouples master write requests from the actual SDRAM access, it is advisable to disable the write buffer when using the feature provided by this register. Otherwise, the ECC check code specified in this register might be applied to a write-buffer write access to SDRAM and not the particular access intended. In addition, care should be taken to ensure that the Am5x86 CPU cache allows the write cycle to propagate to the SDRAM. So that test software need not reproduce the ECC algorithm, Table 7-2 provides a few example ECC check codes that are correct for the associated data. Table 7-2 Example ECC Check Codes and Associated Data 32-Bit Data Write (Hexadecimal) 00000000 FFFFFFFF 000000BC A5A5A5A5 C0C0C0C0 00AB0000 00BC0000 Correct ECC Check Code (Binary) 0000000 0000000 1111111 1100011 0101110 1001100 0100000 ElanTMSC520 Microcontroller Register Set Manual 7-13 SDRAM Controller Registers ECC Single-Bit Error Address (ECCSBADD) Memory-Mapped MMCR Offset 24h 31 Bit Reset R/W 30 Reserved 29 28 27 26 25 24 SB_ADDR[27-24] 0 0 0 0 R 21 20 19 18 17 16 0 0 0 0 RSV 23 Bit Reset R/W 22 SB_ADDR[23-16] 0 0 0 0 R 15 14 13 12 11 10 9 8 0 0 0 0 Bit Reset R/W SB_ADDR[15-8] 0 0 0 0 R 7 6 5 4 3 2 1 Reserved 0 0 0 RSV 0 0 0 0 0 0 Bit Reset R/W SB_ADDR[7-2] 0 0 0 R 0 Register Description This register contains the physical address of the location in SDRAM that caused a single-bit ECC error. Note: A programmable reset does not preserve this register's state. Bit Definitions Bit 31-28 27-2 Name Reserved SB_ADDR [27-2] Function Reserved This bit field should be written to 0 for normal system operation. ECC Single-bit Error Address This bit field contains the physical address (bits 27-2) of the location where a single-bit error occurred. The address is captured upon the detection of a single-bit error, and the bit field is inhibited from capturing subsequent error addresses until the SBIT_ERR bit in the ECCSTA register is cleared by writing a 1 (see page 7-10). Note: This register does not include byte enables (BE) from the requesting master, therefore only doubleword resolution is provided by the indication. Use the ECCCKBPOS register to determine which bit was in error (see page 7-11). Reserved This bit field should be written to 0 for normal system operation. 1-0 Reserved Programming Notes 7-14 ElanTMSC520 Microcontroller Register Set Manual SDRAM Controller Registers ECC Multi-Bit Error Address (ECCMBADD) Memory-Mapped MMCR Offset 28h 31 Bit Reset R/W 30 Reserved 29 28 27 26 25 24 MB_ADDR[27-24] 0 0 0 0 R 21 20 19 18 17 16 0 0 0 0 RSV 23 Bit Reset R/W 22 MB_ADDR[23-16] 0 0 0 0 R 15 14 13 12 11 10 9 8 0 0 0 0 Bit Reset R/W MB_ADDR[15-8] 0 0 0 0 R 7 6 5 4 3 2 1 Reserved 0 0 0 RSV 0 0 0 0 0 0 Bit Reset R/W MB_ADDR[7-2] 0 0 0 R 0 Register Description This register contains the physical address of the location in SDRAM that caused a multi-bit ECC error. Note: A programmable reset does not preserve this register's state. Bit Definitions Bit 31-28 27-2 Name Reserved MB_ADDR [27-2] Function Reserved This bit field should be written to 0 for normal system operation. ECC Multi-Bit Error Address This register contains the physical address (bits 27-2) of the location where a multi-bit error occurred. The address is captured upon the detection of a multi-bit error, and the bit field is inhibited from capturing subsequent error addresses until the MBIT_ERR bit in the ECCSTA register is cleared by writing a 1 (see page 7-10). Note: This register does not include byte enables (BE) from the requesting master, therefore only doubleword resolution is provided in the indication. Reserved This bit field should be written to 0 for normal system operation. 1-0 Reserved Programming Notes ElanTMSC520 Microcontroller Register Set Manual 7-15 SDRAM Controller Registers 7-16 ElanTMSC520 Microcontroller Register Set Manual CHAPTER 8 8.1 WRITE BUFFER AND READ BUFFER REGISTER OVERVIEW This chapter describes the write buffer and read buffer register of the ELANSC520 microcontroller. The write buffer and read buffer are two buffering techniques integrated in the ELANSC520 microcontroller to increase SDRAM system performance. Although both of these features are tightly integrated with the SDRAM controller, the write buffer and the read buffer's readahead feature can be independently enabled via the SDRAM Buffer Control (DBCTL) register. The write buffer and read buffer register set consists of one memory-mapped configuration region (MMCR) register. See the ElanTMSC520 Microcontroller User's Manual, order #22004, for details about the write buffer and read buffer. Table 8-1 lists the DBCTL register and the corresponding description's page number. 8.2 Table 8-1 REGISTER Write Buffer and Read Buffer MMCR Register Register Name SDRAM Buffer Control Mnemonic DBCTL MMCR Offset 40h Page Number page 8-2 ElanTMSC520 Microcontroller Register Set Manual 8-1 Write Buffer and Read Buffer Register SDRAM Buffer Control (DBCTL) Memory-Mapped MMCR Offset 40h 7 Bit Reset R/W 6 Reserved 5 4 RAB_ENB 3 2 1 WB_FLUSH 0 R/W! 0 WB_ENB 0 R/W WB_WM[1-0] 0 R/W 0 0 0 RSV 0 0 R/W Register Description This register controls all the read buffer read-ahead and write buffer functions. Note: A programmable reset does not preserve this register's state. Bit Definitions Bit 7-5 4 Name Reserved RAB_ENB Function Reserved This bit field should be written to 0 for normal system operation. Read-Ahead Feature Enable This bit is used to enable the read-ahead feature of the read buffer. 0 = The read-ahead feature is disabled. 1 = The read-ahead feature is enabled. If the master request is a burst cycle (two or more doublewords), when the current cache line is fetched from SDRAM and stored in the read buffer, the following cache line is also prefetched to take advantage of space locality. If the master request is not a burst cycle, only the rest of the current cache line is fetched from SDRAM into the read buffer. When enabled, the read-ahead feature applies for all bursted read requests from either the Am5x86 CPU or the PCI bus. (The GP bus DMA controller does not perform bursted reads.) During SDRAM sizing or test, disabling the read-ahead feature might improve performance of the sizing or test algorithm. Because most such algorithms test various non-contiguous points in SDRAM, excessive read-ahead thrashing can result. Although this does not result in false indications, it can result in a slight performance degradation of the test algorithm. After the SDRAM sizing or test process is complete, the user is free to enable the read-ahead feature of the read buffer when desired. 3-2 WB_WM[1-0] Write Buffer Watermark This bit field specifies the write buffer's watermark setting (i.e., the amount of allocated buffer space above which the write buffer initiates a write to SDRAM). 00 = 28 doublewords (default) 01 = 24 doublewords 10 = 16 doublewords 11 = 8 doublewords As data is written into the write buffer, a new rank of storage is allocated unless the written data can be merged or collapsed into previous ranks. When a write cycle results in a rank allocation that exceeds the watermark setting, the write buffer requests service from the SDRAM controller to initiate write transfers to SDRAM. A higher watermark setting allows the write buffer to fill higher (acquire more master write data) before requesting SDRAM service, resulting in a greater chance of write data merging or collapsing. This is desirable if a large amount of incomplete doubleword writes (i.e., byte, word or three-byte writes) is expected from either the Am5x86 CPU, PCI bus, or GP bus DMA. A lower watermark setting can be used if more complete doublewords are expected, and so merging or collapsing of data is less likely. A lower watermark causes the write buffer to request SDRAM service at a lower threshold, reducing the chance of filling the write buffer. 8-2 ElanTMSC520 Microcontroller Register Set Manual Write Buffer and Read Buffer Register Bit 1 Name WB_FLUSH Function Write Buffer Flush This bit provides manual control over flushing of the write buffer. 0 = Writing 0 has no effect. Reading 0 after first writing 1 indicates that the flush has completed. 1 = Writing 1 causes the write buffer to flush. Reading 1 indicates that the write buffer is still in the process of being flushed. Flushing the write buffer implies that all write buffer data is written out to SDRAM as a high priority before any other SDRAM write or read cycle activity is allowed to take place. 0 WB_ENB Write Buffer Enable This bit is used to enable the write buffer. 0 = The write buffer is disabled. 1 = The write buffer is enabled. The write buffer buffers all write activity from either the Am5x86 CPU, PCI bus, or GP bus DMA. When enabled, the write buffer merges or collapses write data during write cycles and merges read data during read cycles. During SDRAM sizing or test, the write buffer must be disabled to prevent an invalid SDRAM size indicator or false "pass" status during an SDRAM test algorithm. A false pass is possible because the write buffer supports read merging, so that previously written data is returned (read merged) from the write buffer if the read-back occurs before the data has migrated to SDRAM. This can appear as though SDRAM exists even though it might not. If ECC memory is used, the write buffer must also be disabled while the SDRAM initialization software initializes ECC memory by writing to each SDRAM location. After the SDRAM sizing or test process is complete, the user is free to enable the write buffer when desired. Programming Notes Software must disable the write buffer (i.e., clear the WB_ENB bit) before changing the write buffer watermark (WB_WM bit field). ElanTMSC520 Microcontroller Register Set Manual 8-3 Write Buffer and Read Buffer Register 8-4 ElanTMSC520 Microcontroller Register Set Manual CHAPTER 9 9.1 ROM/FLASH CONTROLLER REGISTERS OVERVIEW This chapter describes the read-only memory (ROM) or Flash memory controller registers of the ELANSC520 microcontroller. The ROM/Flash controller supports up to three ROM device chip select signals, which can be separately enabled. Note that a bank of ROM devices can be accessed with a single chip select (e.g., for building a 32-bit ROM space from four 8-bit ROM devices). The ROM controller register set consists of three memory-mapped configuration region (MMCR) registers used to configure the ROM controller by programming details about the connected ROM devices' operation mode, device width, device location, and timing. Configuration information is provided for each chip select. See the ElanTMSC520 Microcontroller User's Manual, order #22004, for details about the ROM controller. Table 9-1 lists the ROM controller registers in offset order, with the corresponding description's page number. 9.2 Table 9-1 REGISTERS ROM Controller MMCR Registers Register Name BOOTCS Control ROMCS1 Control ROMCS2 Control Mnemonic BOOTCSCTL ROMCS1CTL ROMCS2CTL MMCR Offset 50h 54h 56h Page Number page 9-2 page 9-4 page 9-6 ElanTMSC520 Microcontroller Register Set Manual 9-1 ROM/Flash Controller Registers BOOTCS Control (BOOTCSCTL) Memory-Mapped MMCR Offset 50h 15 Bit Reset R/W 14 Reserved 13 12 DGP 11 10 9 MODE 0 R/W 8 Reserved 0 RSV 0 WIDTH[1-0] ? R 3 Reserved 0 RSV 1 2 ? 0 0 RSV 0 ? R 7 Bit Reset R/W 6 Reserved 5 4 1 FIRST_DLY[2-0] 1 R/W SUB_DLY[1-0] 0 1 R/W 1 0 RSV 1 Register Description This register contains configuration information about the location (i.e., SDRAM bus or GP bus), width, operation mode, and timing of the boot ROM that is attached to the ELANSC520 microcontroller BOOTCS signal. Bit Definitions Bit 15-13 12 Name Reserved DGP Function Reserved This bit field should be written to 0 for normal system operation BOOTCS Device SDRAM/GP Bus Select This bit reflects the location of the boot ROM device that is enabled with the BOOTCS signal. This bit's value is latched from the CFG2 pinstrap when the PWRGOOD pin is asserted. The ROM can be connected to either the SDRAM data bus or to the GP bus. 0 = ROM is on the GP bus. 1 = ROM is on the SDRAM data bus. BOOTCS Device Width Select This bit field reflects the width of the boot ROM. This bit field's value is latched from the CFG1-CFG0 pinstraps when the PWRGOOD pin is asserted. 00 = ROM is 8 bits wide. 01 = ROM is 16 bits wide. 10 = ROM is 32 bits wide. 11 = ROM is 32 bits wide (same as 10b). 11-10 WIDTH[1-0] 9 MODE BOOTCS Device Mode This bit is used to configure the mode of the boot ROM device. 0 = ROM is non-page mode. 1 = ROM is page mode. Reserved This bit field should be written to 0 for normal system operation BOOTCS Device Delay for Subsequent Access This bit field is used to configure the number of wait states for all page-mode accesses to the ROM that are subsequent to the first access. This bit field applies only if the MODE bit is 1. 00 = 0 wait states 01 = 1 wait state 10 = 2 wait states 11 = 3 wait states 8-6 5-4 Reserved SUB_DLY[1-0] 9-2 ElanTMSC520 Microcontroller Register Set Manual ROM/Flash Controller Registers Bit 3 2-0 Name Reserved FIRST_DLY [2-0] Function Reserved This bit field should be written to 0 for normal system operation. BOOTCS Device Delay for First Access This bit field is used to configure the number of wait states for the first access to the ROM, and for subsequent accesses if the MODE bit is 0. 000 = 0 wait states 001 = 1 wait state 010 = 2 wait states 011 = 3 wait states 100 = 4 wait states 101 = 5 wait states 110 = 6 wait states 111 = 7 wait states Programming Notes The device attached to the BOOTCS chip select signal is used as the boot device. Therefore, upon reset this device's DGP and WIDTH bit field values must be delivered to the ROM controller via the CFG2-CFG0 pinstraps. For all other ROM devices, this configuration information is programmed by the initialization software. ElanTMSC520 Microcontroller Register Set Manual 9-3 ROM/Flash Controller Registers ROMCS1 Control (ROMCS1CTL) Memory-Mapped MMCR Offset 54h 15 Bit Reset R/W 14 Reserved 13 12 DGP 11 10 9 MODE 0 R/W 8 Reserved 0 RSV 0 WIDTH[1-0] 0 R/W 3 Reserved 0 RSV 1 2 0 0 0 RSV 0 0 R/W 7 Bit Reset R/W 6 Reserved 5 4 1 FIRST_DLY[2-0] 1 R/W SUB_DLY[1-0] 0 1 R/W 1 0 RSV 1 Register Description This register contains configuration information about the location (i.e., SDRAM bus or GP bus), width, operation mode, and timing of the ROM devices that are attached to the ELANSC520 microcontroller ROMCS1 signal. Bit Definitions Bit 15-13 12 Name Reserved DGP Function Reserved This bit field should be written to 0 for normal system operation. Chip Select 1 Device SDRAM/GP Bus Select This bit is used to configure the location of the ROM devices that are enabled by ROMCS1. The ROM can be connected either to the SDRAM data bus or to the GP bus. 0 = ROM is on the GP bus. 1 = ROM is on the SDRAM data bus. Chip Select 1 Device Width Select This bit field is used to configure the width of the ROM selected by ROMCS1. 00 = ROM is 8 bits wide. 01 = ROM is 16 bits wide. 10 = ROM is 32 bits wide. 11 = ROM is 32 bits wide. 11-10 WIDTH[1-0] 9 MODE Chip Select 1 Device Mode This bit is used to configure the mode of the ROM selected by ROMCS1. 0 = ROM is non-page mode. 1 = ROM is page mode. Reserved This bit field should be written to 0 for normal system operation. Chip Select 1 Device Delay for Subsequent Accesses This bit field is used to configure the number of wait states for all page-mode accesses to the ROM that are subsequent to the first access. This bit field applies only if the MODE bit is 1. 00 = 0 wait states 01 = 1 wait state 10 = 2 wait states 11 = 3 wait states 8-6 5-4 Reserved SUB_DLY[1-0] 3 Reserved Reserved This bit field should be written to 0 for normal system operation. 9-4 ElanTMSC520 Microcontroller Register Set Manual ROM/Flash Controller Registers Bit 2-0 Name FIRST_DLY [2-0] Function Chip Select 1 Device Delay for First Access This bit field is used to configure the number of wait states for the first access to the ROM, and for subsequent accesses if the MODE bit is 0. 000 = 0 wait states 001 = 1 wait state 010 = 2 wait states 011 = 3 wait states 100 = 4 wait states 101 = 5 wait states 110 = 6 wait states 111 = 7 wait states Programming Notes ElanTMSC520 Microcontroller Register Set Manual 9-5 ROM/Flash Controller Registers ROMCS2 Control (ROMCS2CTL) Memory-Mapped MMCR Offset 56h 15 Bit Reset R/W 14 Reserved 13 12 DGP 11 10 9 MODE 0 R/W 8 Reserved 0 RSV 0 WIDTH[1-0] 0 R/W 3 Reserved 0 RSV 1 2 0 0 0 RSV 0 0 R/W 7 Bit Reset R/W 6 Reserved 5 4 1 FIRST_DLY[2-0] 1 R/W SUB_DLY[1-0] 0 1 R/W 1 0 RSV 1 Register Description This register contains configuration information about the location (i.e., SDRAM bus or GP bus), width, operation mode, and timing of the ROM devices that are attached to the ELANSC520 microcontroller ROMCS2 signal. Bit Definitions Bit 15-13 12 Name Reserved DGP Function Reserved This bit field should be written to 0 for normal system operation. Chip Select 2 Device SDRAM/GP Bus Select This bit is used to configure the location of the ROM devices that are enabled by ROMCS2. The ROM can be connected either to the SDRAM data bus or to the GP bus. 0 = ROM is on the GP bus. 1 = ROM is on the SDRAM data bus. Chip Select 2 Device Width Select This bit field is used to configure the width of the ROM selected by ROMCS2. 00 = ROM is 8 bits wide. 01 = ROM is 16 bits wide. 10 = ROM is 32 bits wide. 11 = ROM is 32 bits wide. 11-10 WIDTH[1-0] 9 MODE Chip Select 2 Device Mode This bit is used to configure the mode of the ROM selected by ROMCS2. 0 = ROM is non-page mode. 1 = ROM is page mode. Reserved This bit field should be written to 0 for normal system operation. Chip Select 2 Device Delay for Subsequent Accesses This bit field is used to configure the number of wait states for all page-mode accesses to the ROM that are subsequent to the first access. This bit field applies only if the MODE bit is 1. 00 = 0 wait states 01 = 1 wait state 10 = 2 wait states 11 = 3 wait states 8-6 5-4 Reserved SUB_DLY[1-0] 3 Reserved Reserved This bit field should be written to 0 for normal system operation. 9-6 ElanTMSC520 Microcontroller Register Set Manual ROM/Flash Controller Registers Bit 2-0 Name FIRST_DLY [2-0] Function Chip Select 2 Device Delay for First Access This bit field is used to configure the number of wait states for the first access to the ROM, and for subsequent accesses if the MODE bit is 0. 000 = 0 wait states 001 = 1 wait state 010 = 2 wait states 011 = 3 wait states 100 = 4 wait states 101 = 5 wait states 110 = 6 wait states 111 = 7 wait states Programming Notes ElanTMSC520 Microcontroller Register Set Manual 9-7 ROM/Flash Controller Registers 9-8 ElanTMSC520 Microcontroller Register Set Manual CHAPTER 10 10.1 GENERAL-PURPOSE BUS CONTROLLER REGISTERS OVERVIEW This chapter describes the general-purpose (GP) bus registers of the ELANSC520 microcontroller. The GP bus is used for glueless connection of 8- and 16-bit devices to the ELANSC520 microcontroller. To provide the glueless interface, the GP bus interface timing and data bus width is programmable. The GP bus register set consists of 12 memory-mapped configuration region (MMCR) registers used to configure the GP bus timing and data bus width. See the ElanTMSC520 Microcontroller User's Manual, order #22004, for details about the GP bus. Table 10-1 lists the GP bus registers in offset order, with the corresponding description's page number. 10.2 Table 10-1 REGISTERS GP Bus MMCR Registers Register Name GP Echo Mode GP Chip Select Data Width GP Chip Select Qualification GP Chip Select Recovery Time GP Chip Select Pulse Width GP Chip Select Offset GP Read Pulse Width GP Read Offset GP Write Pulse Width GP Write Offset GPALE Pulse Width GPALE Offset Mnemonic GPECHO GPCSDW GPCSQUAL GPCSRT GPCSPW GPCSOFF GPRDW GPRDOFF GPWRW GPWROFF GPALEW GPALEOFF MMCR Offset C00h C01h C02h C08h C09h C0Ah C0Bh C0Ch C0Dh C0Eh C0Fh C10h Page Number page 10-2 page 10-3 page 10-5 page 10-7 page 10-8 page 10-9 page 10-10 page 10-11 page 10-12 page 10-13 page 10-14 page 10-15 ElanTMSC520 Microcontroller Register Set Manual 10-1 General-Purpose Bus Controller Registers GP Echo Mode (GPECHO) Memory-Mapped MMCR Offset C00h 7 Bit Reset R/W 6 5 4 Reserved 3 2 1 0 GP_ECHO_ ENB 0 0 0 0 RSV 0 0 0 0 R/W Register Description This register is used to enable the GP bus echo mode. Bit Definitions Bit 7-1 0 Name Reserved GP_ECHO_ ENB Function Reserved This field should be written to 0 for normal system operation. GP Bus Echo Mode Enable This bit is used to enable the echo mode of GP bus. 0 = Echo mode is disabled. 1 = Echo mode is enabled. Accesses to the microcontroller's integrated peripherals are echoed to the external GP bus Programming Notes While echo mode is enabled, the access timing to internal peripherals is modified to adhere to the external timings programmed by the user. This ensures that external peripherals connected to the GP bus still work as programmed by the user. Thus it is possible that access to internal peripherals are slower in echo mode than in normal mode. While echo mode is enabled, the system designer must ensure that the GP bus timing is not faster than that shown in Table 10-2. The table shows the minimum GP bus timing register values allowed in echo mode. See the corresponding register descriptions beginning on page 10-7. : Table 10-2 GP Bus Echo Mode Minimum Timing Signal Type GP Chip Select GP Read GP Write GPALE Offset Register Value1 1 1 1 0 Pulse Width Register Value1 3 3 3 0 Recovery Time Register Value1 1 -- -- -- Notes: 1. The actual time value is the register value plus one. Times are in units of one internal (33-MHz) clock period. 10-2 ElanTMSC520 Microcontroller Register Set Manual General-Purpose Bus Controller Registers GP Chip Select Data Width (GPCSDW) Memory-Mapped MMCR Offset C01h 7 Bit Reset R/W 6 GPCS6_ DW 0 R/W 5 GPCS5_ DW 0 R/W 4 GPCS4_ DW 0 R/W 3 GPCS3_ DW 0 R/W 2 GPCS2_ DW 0 R/W 1 GPCS1_ DW 0 R/W 0 GPCS0_ DW 0 R/W GPCS7_ DW 0 R/W Register Description This register is used to select the default data width for each of the eight GP bus chip selects. Bit Definitions Bit 7 Name GPCS7_DW Function Data Width Select for GPCS7 This bit is used to select the default data width for the GP bus chip select 7 signal. 0 = 8-bit data 1 = 16-bit data Data Width Select for GPCS6 This bit is used to select the default data width for the GP bus chip select 6 signal. 0 = 8-bit data 1 = 16-bit data Data Width Select for GPCS5 This bit is used to select the default data width for the GP bus chip select 5 signal. 0 = 8-bit data 1 = 16-bit data Data Width Select for GPCS4 This bit is used to select the default data width for the GP bus chip select 4 signal. 0 = 8-bit data 1 = 16-bit data Data Width Select for GPCS3 This bit is used to select the default data width for the GP bus chip select 3 signal. 0 = 8-bit data 1 = 16-bit data Data Width Select for GPCS2 This bit is used to select the default data width for the GP bus chip select 2 signal. 0 = 8-bit data 1 = 16-bit data Data Width Select for GPCS1 This bit is used to select the default data width for the GP bus chip select 1 signal. 0 = 8-bit data 1 = 16-bit data Data Width Select for GPCS0 This bit is used to select the default data width for the GP bus chip select 0 signal. 0 = 8-bit data 1 = 16-bit data 6 GPCS6_DW 5 GPCS5_DW 4 GPCS4_DW 3 GPCS3_DW 2 GPCS2_DW 1 GPCS1_DW 0 GPCS0_DW ElanTMSC520 Microcontroller Register Set Manual 10-3 General-Purpose Bus Controller Registers Programming Notes The GPCSx_DW bits are ignored if the GPIOCS16 signal is asserted during an I/O access, or if the GPMEMCS16 signal is asserted during a memory access. The GPIOCS16 signal is ignored if it is asserted during a memory access. Similarly, the GPMEMCS16 signal is ignored if it is asserted during an I/O access. Before using one of the GPCS7-GPCS0 signals, software must set the corresponding GPCSx_SEL bit in the CSPFS register (see page 20-7). 10-4 ElanTMSC520 Microcontroller Register Set Manual General-Purpose Bus Controller Registers GP Chip Select Qualification (GPCSQUAL) Memory-Mapped MMCR Offset C02h 15 Bit Reset R/W 14 13 12 11 10 9 8 GPCS7_RW[1-0] 0 R/W 7 6 0 GPCS6_RW[1-0] 0 R/W 5 4 0 GPCS5_RW[1-0] 0 R/W 3 2 0 GPCS4_RW[1-0] 0 R/W 1 0 0 Bit Reset R/W GPCS3_RW[1-0] 0 R/W 0 GPCS2_RW[1-0] 0 R/W 0 GPCS1_RW[1-0] 0 R/W 0 GPCS0_RW[1-0] 0 R/W 0 Register Description This register is used to qualify the GP bus chip selects with GPIORD, GPIOWR, GPMEMRD or GPMEMWR. The qualifiers that can be used depend on the TARGET bit field in the PARx register for the addressed region (see page 2-6). If the TARGET bit field selects GP bus I/O, the GP bus chip selects can be qualified with GPIORD or GPIOWR. If the TARGET bit field selects GP bus memory, the GP bus chip selects can be qualified with GPMEMRD or GPMEMWR. Bit Definitions Bit 15-14 Name GPCS7_RW [1-0] Function GPCS7 Qualifier Selection This field is used to qualify the GP bus chip select 7 with GPIORD, GPIOWR, GPMEMRD or GPMEMWR. 00 = No qualification. 01 = Qualify the chip select with write strobes (GPIOWR or GPMEMWR) 10 = Qualify the chip select with read strobes (GPIORD or GPMEMRD) 11 = Qualify the chip select with both strobes (GPIORD and GPIOWR, or GPMEMRD and GPMEMWR) 13-12 GPCS6_RW [1-0] GPCS6 Qualifier Selection This field is used to qualify the GP bus chip select 6 with GPIORD, GPIOWR, GPMEMRD or GPMEMWR. 00 = No qualification. 01 = Qualify the chip select with write strobes (GPIOWR or GPMEMWR) 10 = Qualify the chip select with read strobes (GPIORD or GPMEMRD) 11 = Qualify the chip select with both strobes (GPIORD and GPIOWR, or GPMEMRD and GPMEMWR) 11-10 GPCS5_RW [1-0] GPCS5 Qualifier Selection This field is used to qualify the GP bus chip select 5 with GPIORD, GPIOWR, GPMEMRD or GPMEMWR. 00 = No qualification. 01 = Qualify the chip select with write strobes (GPIOWR or GPMEMWR) 10 = Qualify the chip select with read strobes (GPIORD or GPMEMRD) 11 = Qualify the chip select with both strobes (GPIORD and GPIOWR, or GPMEMRD and GPMEMWR) ElanTMSC520 Microcontroller Register Set Manual 10-5 General-Purpose Bus Controller Registers Bit 9-8 Name GPCS4_RW [1-0] Function GPCS4 Qualifier Selection This field is used to qualify the GP bus chip select 4 with GPIORD, GPIOWR, GPMEMRD or GPMEMWR. 00 = No qualification. 01 = Qualify the chip select with write strobes (GPIOWR or GPMEMWR) 10 = Qualify the chip select with read strobes (GPIORD or GPMEMRD) 11 = Qualify the chip select with both strobes (GPIORD and GPIOWR, or GPMEMRD and GPMEMWR) 7-6 GPCS3_RW [1-0] GPCS3 Qualifier Selection This field is used to qualify the GP bus chip select 3 with GPIORD, GPIOWR, GPMEMRD or GPMEMWR. 00 = No qualification. 01 = Qualify the chip select with write strobes (GPIOWR or GPMEMWR) 10 = Qualify the chip select with read strobes (GPIORD or GPMEMRD) 11 = Qualify the chip select with both strobes (GPIORD and GPIOWR, or GPMEMRD and GPMEMWR) 5-4 GPCS2_RW [1-0] GPCS2 Qualifier Selection This field is used to qualify the GP bus chip select 2 with GPIORD, GPIOWR, GPMEMRD or GPMEMWR. 00 = No qualification. 01 = Qualify the chip select with write strobes (GPIOWR or GPMEMWR) 10 = Qualify the chip select with read strobes (GPIORD or GPMEMRD) 11 = Qualify the chip select with both strobes (GPIORD and GPIOWR, or GPMEMRD and GPMEMWR) 3-2 GPCS1_RW [1-0] GPCS1 Qualifier Selection This field is used to qualify the GP bus chip select 1 with GPIORD, GPIOWR, GPMEMRD or GPMEMWR. 00 = No qualification. 01 = Qualify the chip select with write strobes (GPIOWR or GPMEMWR) 10 = Qualify the chip select with read strobes (GPIORD or GPMEMRD) 11 = Qualify the chip select with both strobes (GPIORD and GPIOWR, or GPMEMRD and GPMEMWR) 1-0 GPCS0_RW [1-0] GPCS0 Qualifier Selection This field is used to qualify the GP bus chip select 0 with GPIORD, GPIOWR, GPMEMRD or GPMEMWR. 00 = No qualification. 01 = Qualify the chip select with write strobes (GPIOWR or GPMEMWR) 10 = Qualify the chip select with read strobes (GPIORD or GPMEMRD) 11 = Qualify the chip select with both strobes (GPIORD and GPIOWR, or GPMEMRD and GPMEMWR) Programming Notes When this register (GPCSQUAL) is used to qualify a GP bus chip select signal, the external timing relationship between the qualifier and the chip select is not guaranteed. For example, deassertion of the chip select signal could precede the qualifier's deassertion on the external GP bus. If a single qualifier type (only read or only write) is used to qualify a GP bus chip select signal, the corresponding chip select is not asserted for accesses of the other type. For example, if the GPCS0_RW bit field is set to 01b to qualify GP Chip Select 0 with write strobes only, GP Chip Select 0 is not asserted for read accesses. Before using one of the GPCS7-GPCS1 signals, software must set the corresponding GPCSx_SEL bit in the CSPFS register (see page 20-7). Before using the GPCS0 signal, software must set the PIO27_SEL bit in the PIOPFS31- 16 register (see page 20-5). 10-6 ElanTMSC520 Microcontroller Register Set Manual General-Purpose Bus Controller Registers GP Chip Select Recovery Time (GPCSRT) Memory-Mapped MMCR Offset C08h 7 Bit Reset R/W 6 5 4 3 2 1 0 GPCS_RECOVR[7-0] 0 0 0 0 R/W 0 0 0 0 Register Description This register is used to program the chip select recovery time for all GP bus cycles. Bit Definitions Bit 7-0 Name GPCS_ RECOVR[7-0] Function Chip Select Recovery Time This field adjusts the recovery time for all the GP bus chip selects. The resolution of this parameter is one internal (33-MHz) clock period. The recovery time used is (GPCS_RECOVR + 1) internal clock periods; i.e., if GPCS_RECOVR is 0, the recovery time is one clock period. Programming Notes Before using one of the GPCS7-GPCS1 signals, software must set the corresponding GPCSx_SEL bit in the CSPFS register (see page 20-7). Before using the GPCS0 signal, software must set the PIO27_SEL bit in the PIOPFS31- 16 register (see page 20-5). Figure 10-1 shows the relationships between the various adjustable GP bus timing parameters. Figure 10-1 GP Bus Signal Timing Adjustment Address Valid GPA25-GPA0 GPCSx GPCSOFF + 1 GPMEMRD or GPIORD GPCSPW + 1 GPCSRT + 1 GPRDOFF + 1 GPMEMWR or GPIOWR GPWROFF + 1 GPALE GPALEOFF + 1 Beginning of a Bus Cycle Bus Cycle Duration GPRDW + 1 GPWRW + 1 GPALEW + 1 Notes: 1. Timing parameter values are in units of one internal (33-MHz) clock period. 2. Timing parameters in the diagram can be adjusted via the corresponding GP bus registers. 3. GPCSOFF + GPCSPW + GPCSRT must be greater than or equal to GPRDOFF + GPRDW, GPWROFF + GPWRW, and GPALEOFF + GPALEW. 4. Very long GP bus cycles can cause the PCI Host Bridge target controller to violate the 10 s memory write maximum completion time limit set in the PCI Local Bus Specification, Revision 2.2. In PCI bus 2.2-compliant designs, software must limit the length of GP bus cycles. ElanTMSC520 Microcontroller Register Set Manual 10-7 General-Purpose Bus Controller Registers GP Chip Select Pulse Width (GPCSPW) Memory-Mapped MMCR Offset C09h 7 Bit Reset R/W 6 5 4 3 2 1 0 GPCS_WIDTH[7-0] 0 0 0 0 R/W 0 0 0 0 Register Description This register is used to program the pulse width for all the GP bus chip selects. Bit Definitions Bit 7-0 Name GPCS_WIDTH [7-0] Function Signal Width for the GP Bus Chip Selects This field adjusts the signal pulse width (time) of all the GP bus chip selects. The resolution of this parameter is one internal (33-MHz) clock period. The width used is (GPCS_WIDTH + 1) internal clock periods; i.e., if GPCS_WIDTH is 0, the pulse is one clock period wide. Programming Notes Before using one of the GPCS7-GPCS1 signals, software must set the corresponding GPCSx_SEL bit in the CSPFS register (see page 20-7). Before using the GPCS0 signal, software must set the PIO27_SEL bit in the PIOPFS31- 16 register (see page 20-5). Figure 10-1 on page 10-7 shows the relationships between the various adjustable GP bus timing parameters. 10-8 ElanTMSC520 Microcontroller Register Set Manual General-Purpose Bus Controller Registers GP Chip Select Offset (GPCSOFF) Memory-Mapped MMCR Offset C0Ah 7 Bit Reset R/W 6 5 4 3 2 1 0 GPCS_OFF[7-0] 0 0 0 0 R/W 0 0 0 0 Register Description This register is used to program the offset time from the beginning of a GP bus cycle for all the GP bus chip selects. Bit Definitions Bit 7-0 Name GPCS_OFF [7-0] Function Offset Time for the GP Bus Chip Select This field adjusts the offset time of all the GP bus chip selects. The resolution of this parameter is one internal (33-MHz) clock period. The offset time used is (GPCS_OFF + 1) internal clock periods; i.e., if GPCS_OFF is 0, the offset time is one clock period. Programming Notes Before using one of the GPCS7-GPCS1 signals, software must set the corresponding GPCSx_SEL bit in the CSPFS register (see page 20-7). Before using the GPCS0 signal, software must set the PIO27_SEL bit in the PIOPFS31- 16 register (see page 20-5). Figure 10-1 on page 10-7 shows the relationships between the various adjustable GP bus timing parameters. ElanTMSC520 Microcontroller Register Set Manual 10-9 General-Purpose Bus Controller Registers GP Read Pulse Width (GPRDW) Memory-Mapped MMCR Offset C0Bh 7 Bit Reset R/W 6 5 4 3 2 1 0 GP_RD_WIDTH[7-0] 0 0 0 0 R/W 0 0 0 0 Register Description This register is used to program the signal width for the read strobes (GPIORD and GPMEMRD). Bit Definitions Bit 7-0 Name GP_RD_ WIDTH[7-0] Function Signal Width for GPIORD and GPMEMRD This field adjusts the signal pulse width (time) of the GP bus read strobes. The resolution of this parameter is one internal (33-MHz) clock period. The width used is (GP_RD_WIDTH + 1) internal clock periods; i.e., if GP_RD_WIDTH is 0, the pulse is one clock period wide. Programming Notes Figure 10-1 on page 10-7 shows the relationships between the various adjustable GP bus timing parameters. 10-10 ElanTMSC520 Microcontroller Register Set Manual General-Purpose Bus Controller Registers GP Read Offset (GPRDOFF) Memory-Mapped MMCR Offset C0Ch 7 Bit Reset R/W 6 5 4 3 2 1 0 GP_RD_OFF[7-0] 0 0 0 0 R/W 0 0 0 0 Register Description This register is used to program the offset time from beginning of a GP bus cycle for GPIORD and GPMEMRD. Bit Definitions Bit 7-0 Name GP_RD_OFF [7-0] Function Offset Time for GPIORD and GPMEMRD This field adjusts the offset time of the GP bus read strobes. The resolution of this parameter is one internal (33-MHz) clock period. The offset time used is (GP_RD_OFF + 1) internal clock periods; i.e., if GP_RD_OFF is 0, the offset time is one clock period. Programming Notes Figure 10-1 on page 10-7 shows the relationships between the various adjustable GP bus timing parameters. ElanTMSC520 Microcontroller Register Set Manual 10-11 General-Purpose Bus Controller Registers GP Write Pulse Width (GPWRW) Memory-Mapped MMCR Offset C0Dh 7 Bit Reset R/W 6 5 4 3 2 1 0 GP_WR_WIDTH[7-0] 0 0 0 0 R/W 0 0 0 0 Register Description This register is used to program the pulse width for the write strobes (GPIOWR and GPMEMWR). Bit Definitions Bit 7-0 Name GP_WR_ WIDTH[7-0] Function Signal Width for (GPIOWR and GPMEMWR) This field adjusts the signal pulse width (time) of the GP bus write strobes. The resolution of this parameter is one internal (33-MHz) clock period. The width used is (GP_WR_WIDTH + 1) internal clock periods; i.e., if GP_WR_WIDTH is 0, the pulse is one clock period wide. Programming Notes Figure 10-1 on page 10-7 shows the relationships between the various adjustable GP bus timing parameters. 10-12 ElanTMSC520 Microcontroller Register Set Manual General-Purpose Bus Controller Registers GP Write Offset (GPWROFF) Memory-Mapped MMCR Offset C0Eh 7 Bit Reset R/W 6 5 4 3 2 1 0 GP_WR_OFF[7-0] 0 0 0 0 R/W 0 0 0 0 Register Description This register is used to program the offset from beginning of a GP bus cycle for GPIOWR and GPMEMWR. Bit Definitions Bit 7-0 Name GP_WR_OFF [7-0] Function Offset Time for GPIOWR and GPMEMWR This field adjusts the offset time of the GP bus write strobes. The resolution of this parameter is one internal (33-MHz) clock period. The offset time used is (GP_WR_OFF + 1) internal clock periods; i.e., if GP_WR_OFF is 0, the offset time is one clock period. Programming Notes Figure 10-1 on page 10-7 shows the relationships between the various adjustable GP bus timing parameters. ElanTMSC520 Microcontroller Register Set Manual 10-13 General-Purpose Bus Controller Registers GPALE Pulse Width (GPALEW) Memory-Mapped MMCR Offset C0Fh 7 Bit Reset R/W 6 5 4 3 2 1 0 GP_ALE_WIDTH[7-0] 0 0 0 0 R/W 0 0 0 0 Register Description This register is used to program the signal width for GPALE. Bit Definitions Bit 7-0 Name GP_ALE_ WIDTH[7-0] Function Signal Width for GPALE This field adjusts the signal pulse width (time) of the GPALE signal. The resolution of this parameter is one internal (33-MHz) clock period. The width used is (GP_ALE_WIDTH + 1) internal clock periods; i.e., if GP_ALE_WIDTH is 0, the pulse is one clock period wide. Programming Notes Figure 10-1 on page 10-7 shows the relationships between the various adjustable GP bus timing parameters. 10-14 ElanTMSC520 Microcontroller Register Set Manual General-Purpose Bus Controller Registers GPALE Offset (GPALEOFF) Memory-Mapped MMCR Offset C10h 7 Bit Reset R/W 6 5 4 3 2 1 0 GP_ALE_OFF[7-0] 0 0 0 0 R/W 0 0 0 0 Register Description This register is used to program the offset from the beginning of a GP bus cycle for GPALE. Bit Definitions Bit 7-0 Name GP_ALE_OFF [7-0] Function Offset Time for GPALE This field adjusts the offset time of the GPALE signal. The resolution of this parameter is one internal (33-MHz) clock period. The offset time used is (GP_ALE_OFF + 1) internal clock periods; i.e., if GP_ALE_OFF is 0, the offset time is one clock period. Programming Notes Figure 10-1 on page 10-7 shows the relationships between the various adjustable GP bus timing parameters. ElanTMSC520 Microcontroller Register Set Manual 10-15 General-Purpose Bus Controller Registers 10-16 ElanTMSC520 Microcontroller Register Set Manual CHAPTER 11 11.1 GP DMA CONTROLLER REGISTERS OVERVIEW This chapter describes the general-purpose bus direct-memory access (GP bus DMA) registers of the ELANSC520 microcontroller. The ELANSC520 microcontroller's GP DMA controller consists of two cascaded DMA controller devices that provide a total of seven independent channels. Channels 0-3 are on the slave controller device, and Channels 5-7 are on the master controller device. (Channel 4 is used for cascading the two devices.) The GP bus DMA register set includes two groups of registers: s 35 memory-mapped configuration region (MMCR) registers are used to specify the extended page address and the operation of each channel in the enhanced mode. s 52 direct-mapped I/O registers are used to configure the operation of each DMA controller device (master and slave) within the DMA controller, and to set up the memory address and transfer count for each channel. See the ElanTMSC520 Microcontroller User's Manual, order #22004, for details about the GP bus DMA controller. Table 11-1 and Table 11-2 list each type of GP bus DMA register in offset order, with the corresponding description's page number. 11.2 Table 11-1 REGISTERS GP-DMA MMCR Registers Register Name GP-DMA Control GP-DMA Memory-Mapped I/O GP-DMA Resource Channel Map A GP-DMA Resource Channel Map B GP-DMA Channel 0 Extended Page GP-DMA Channel 1 Extended Page GP-DMA Channel 2 Extended Page GP-DMA Channel 3 Extended Page GP-DMA Channel 5 Extended Page GP-DMA Channel 6 Extended Page GP-DMA Channel 7 Extended Page GP-DMA Channel 3 Extended Transfer Count GP-DMA Channel 5 Extended Transfer Count Mnemonic GPDMACTL GPDMAMMIO GPDMAEXTCHMAPA GPDMAEXTCHMAPB GPDMAEXTPG0 GPDMAEXTPG1 GPDMAEXTPG2 GPDMAEXTPG3 GPDMAEXTPG5 GPDMAEXTPG6 GPDMAEXTPG7 GPDMAEXTTC3 GPDMAEXTTC5 Page MMCR Offset Number D80h D81h D82h D84h D86h D87h D88h D89h D8Ah D8Bh D8Ch D90h D91h page 11-4 page 11-5 page 11-6 page 11-8 page 11-10 page 11-11 page 11-12 page 11-13 page 11-14 page 11-15 page 11-16 page 11-17 page 11-18 ElanTMSC520 Microcontroller Register Set Manual 11-1 GP DMA Controller Registers Table 11-1 GP-DMA MMCR Registers (Continued) Register Name GP-DMA Channel 6 Extended Transfer Count GP-DMA Channel 7 Extended Transfer Count Buffer Chaining Control Buffer Chaining Status Buffer Chaining Interrupt Enable Buffer Chaining Valid GP-DMA Channel 3 Next Address Low GP-DMA Channel 3 Next Address High GP-DMA Channel 5 Next Address Low GP-DMA Channel 5 Next Address High GP-DMA Channel 6 Next Address Low GP-DMA Channel 6 Next Address High GP-DMA Channel 7 Next Address Low GP-DMA Channel 7 Next Address High Mnemonic GPDMAEXTTC6 GPDMAEXTTC7 GPDMABCCTL GPDMABCSTA GPDMABSINTENB GPDMABCVAL GPDMANXTADDL3 GPDMANXTADDH3 GPDMANXTADDL5 GPDMANXTADDH5 GPDMANXTADDL6 GPDMANXTADDH6 GPDMANXTADDL7 GPDMANXTADDH7 Page MMCR Offset Number D92h D93h D98h D99h D9Ah D9Bh DA0h DA2h DA4h DA6h DA8h DAAh DACh DAEh DB0h DB2h DB4h DB6h DB8h DBAh DBCh DBEh page 11-19 page 11-20 page 11-21 page 11-22 page 11-24 page 11-25 page 11-26 page 11-27 page 11-28 page 11-29 page 11-30 page 11-31 page 11-32 page 11-33 page 11-34 page 11-35 page 11-36 page 11-37 page 11-38 page 11-39 page 11-40 page 11-41 GP-DMA Channel 3 Next Transfer Count Low GPDMANXTTCL3 GP-DMA Channel 3 Next Transfer Count High GPDMANXTTCH3 GP-DMA Channel 5 Next Transfer Count Low GPDMANXTTCL5 GP-DMA Channel 5 Next Transfer Count High GPDMANXTTCH5 GP-DMA Channel 6 Next Transfer Count Low GPDMANXTTCL6 GP-DMA Channel 6 Next Transfer Count High GPDMANXTTCH6 GP-DMA Channel 7 Next Transfer Count Low GPDMANXTTCL7 GP-DMA Channel 7 Next Transfer Count High GPDMANXTTCH7 Table 11-2 GP-DMA Direct-Mapped Registers Register Name Slave DMA Channel 0 Memory Address Slave DMA Channel 0 Transfer Count Slave DMA Channel 1 Memory Address Slave DMA Channel 1 Transfer Count Slave DMA Channel 2 Memory Address Slave DMA Channel 2 Transfer Count Slave DMA Channel 3 Memory Address Slave DMA Channel 3 Transfer Count Slave DMA Channel 0-3 Status Slave DMA Channel 0-3 Control Slave Software DRQ(n) Request Slave DMA Channel 0-3 Mask Slave DMA Channel 0-3 Mode Slave DMA Clear Byte Pointer Mnemonic GPDMA0MAR GPDMA0TC GPDMA1MAR GPDMA1TC GPDMA2MAR GPDMA2TC GPDMA3MAR GPDMA3TC SLDMASTA SLDMACTL SLDMASWREQ SLDMAMSK SLDMAMODE SLDMACBP I/O Address 0000h 0001h 0002h 0003h 0004h 0005h 0006h 0007h 0008h 0008h 0009h 000Ah 000Bh 000Ch Page Number page 11-42 page 11-43 page 11-44 page 11-45 page 11-46 page 11-47 page 11-48 page 11-49 page 11-50 page 11-51 page 11-53 page 11-54 page 11-55 page 11-57 11-2 ElanTMSC520 Microcontroller Register Set Manual GP DMA Controller Registers Table 11-2 GP-DMA Direct-Mapped Registers (Continued) Register Name Slave DMA Controller Reset Slave DMA Controller Temporary Slave DMA Mask Reset Slave DMA General Mask General 0 Slave DMA Channel 2 Page Slave DMA Channel 3 Page Slave DMA Channel 1 Page General 1 General 2 General 3 Slave DMA Channel 0 Page General 4 Master DMA Channel 6 Page Master DMA Channel 7 Page Master DMA Channel 5 Page General 5 General 6 General 7 General 8 Master DMA Channel 4 Transfer Count Master DMA Channel 5 Transfer Count Master DMA Channel 6 Transfer Count Master DMA Channel 7 Transfer Count Master DMA Channel 4-7 Status Master DMA Channel 4-7 Control Master Software DRQ(n) Request Master DMA Channel 4-7 Mask Master DMA Channel 4-7 Mode Master DMA Clear Byte Pointer Master DMA Controller Reset Master DMA Controller Temporary Master DMA Mask Reset Master DMA General Mask Mnemonic SLDMARST SLDMATMP SLDMAMSKRST SLDMAGENMSK GPDMAGR0 GPDMA2PG GPDMA3PG GPDMA1PG GPDMAGR1 GPDMAGR2 GPDMAGR3 GPDMA0PG GPDMAGR4 GPDMA6PG GPDMA7PG GPDMA5PG GPDMAGR5 GPDMAGR6 GPDMAGR7 GPDMAGR8 GPDMA4TC GPDMA5TC GPDMA6TC GPDMA7TC MSTDMASTA MSTDMACTL MSTDMASWREQ MSTDMAMSK MSTDMAMODE MSTDMACBP MSTDMARST MSTDMATMP MSTDMAMSKRST MSTDMAGENMSK I/O Address 000Dh 000Dh 000Eh 000Fh 0080h 0081h 0082h 0083h 0084h 0085h 0086h 0087h 0088h 0089h 008Ah 008Bh 008Ch 008Dh 008Eh 008Fh 00C0h 00C2h 00C4h 00C6h 00C8h 00CAh 00CCh 00CEh 00D0h 00D0h 00D2h 00D4h 00D6h 00D8h 00DAh 00DAh 00DCh 00DEh Page Number page 11-58 page 11-59 page 11-60 page 11-61 page 11-62 page 11-63 page 11-64 page 11-65 page 11-66 page 11-67 page 11-68 page 11-69 page 11-70 page 11-71 page 11-72 page 11-73 page 11-74 page 11-75 page 11-76 page 11-77 page 11-78 page 11-79 page 11-80 page 11-81 page 11-82 page 11-83 page 11-84 page 11-85 page 11-86 page 11-87 page 11-89 page 11-90 page 11-91 page 11-93 page 11-94 page 11-95 page 11-96 page 11-97 Master DMA Channel 4 Memory Address GPDMA4MAR Master DMA Channel 5 Memory Address GPDMA5MAR Master DMA Channel 6 Memory Address GPDMA6MAR Master DMA Channel 7 Memory Address GPDMA7MAR ElanTMSC520 Microcontroller Register Set Manual 11-3 GP DMA Controller Registers GP-DMA Control (GPDMACTL) Memory-Mapped MMCR Offset D80h 7 Bit 6 CH6_ALT_ SIZE 0 R/W 5 CH5_ALT_ SIZE 0 R/W 4 CH3_ALT_ SIZE 0 R/W 3 2 1 Reserved 0 RSV 0 ENH_ MODE_ ENB 0 R/W CH7_ALT_ SIZE 0 R/W CLK_MODE 0 R/W 0 Reset R/W Register Description This register provides control for the enhanced mode and selects the clock frequency. Bit Definitions Bit 7 Name CH7_ALT_SIZE Function Alternate Size for Channel 7 0 = Channel 7 is 16 bits wide. 1 = Channel 7 is 8 bits wide. This bit field is ignored if the ENH_MODE_ENB bit is 0. 6 CH6_ALT_SIZE Alternate Size for Channel 6 0 = Channel 6 is 16 bits wide. 1 = Channel 6 is 8 bits wide. This bit field is ignored if the ENH_MODE_ENB bit is 0. 5 CH5_ALT_SIZE Alternate Size for Channel 5 0 = Channel 5 is 16 bits wide. 1 = Channel 5 is 8 bits wide. This bit field is ignored if the ENH_MODE_ENB bit is 0. 4 CH3_ALT_SIZE Alternate Size for Channel 3 0 = Channel 3 is 8 bits wide. 1 = Channel 3 is 16 bits wide. This bit field is ignored if the ENH_MODE_ENB bit is 0. Note that the Channel 3 default size differs from the Channel 5-7 default size. Do not set the CH3_ALT_SIZE bit if an internal UART is mapped to Channel 3 via the GPDMAEXTCHMAPB register (see page 11-8). 3-2 CLK_MODE Clock Mode 00 = Operate the GP bus DMA controller at 4 Mhz. 01 = Operate the GP bus DMA controller at 8 Mhz. 10 = Operate the GP bus DMA controller at 16 Mhz. 11 = Reserved. The frequencies shown here are nominal. The exact GP bus DMA frequency is derived by dividing the microcontroller's 33-MHz crystal input, which can be 33.000 or 33.333 MHz. 1 0 Reserved ENH_MODE_ ENB Reserved This bit field should be written to 0 for normal system operation. Enhanced Mode Enable 0 = Disable enhanced GP-DMA mode (use normal GP-DMA mode). 1 = Enable enhanced GP-DMA mode. Programming Notes 11-4 ElanTMSC520 Microcontroller Register Set Manual GP DMA Controller Registers GP-DMA Memory-Mapped I/O (GPDMAMMIO) Memory-Mapped MMCR Offset D81h 7 Bit Reset R/W 6 DMA6_ MMAP 0 R/W 5 DMA5_ MMAP 0 R/W 4 Reserved 0 RSV 3 DMA3_ MMAP 0 R/W 2 DMA2_ MMAP 0 R/W 1 DMA1_ MMAP 0 R/W 0 DMA0_ MMAP 0 R/W DMA7_ MMAP 0 R/W Register Description This register provides the selection of an I/O device (enabled by the GPIORD and GPIOWR signals) or a memorymapped I/O device (enabled by the GPMEMRD or GPMEMWR signals) for each channel. Bit Definitions Bit 7 Name DMA7_MMAP Function Memory-Mapped Device for DMA Channel 7 0 = DMA Channel 7 connects to a direct-mapped I/O device. 1 = DMA Channel 7 connects to a memory-mapped device. Memory-Mapped Device for DMA Channel 6 0 = DMA Channel 6 connects to a direct-mapped I/O device. 1 = DMA Channel 6 connects to a memory-mapped device. Memory-Mapped Device for DMA Channel 5 0 = DMA Channel 5 connects to a direct-mapped I/O device. 1 = DMA Channel 5 connects to a memory-mapped device. Reserved This bit field should be written to 0 for normal system operation. Memory-Mapped Device for DMA Channel 3 0 = DMA Channel 3 connects to a direct-mapped I/O device. 1 = DMA Channel 3 connects to a memory-mapped device. Memory-Mapped Device for DMA Channel 2 0 = DMA Channel 2 connects to a direct-mapped I/O device. 1 = DMA Channel 2 connects to a memory-mapped device. Memory-Mapped Device for DMA Channel 1 0 = DMA Channel 1 connects to a direct-mapped I/O device. 1 = DMA Channel 1 connects to a memory-mapped device. Memory-Mapped Device for DMA Channel 0 0 = DMA Channel 0 connects to a direct-mapped I/O device. 1 = DMA Channel 0 connects to a memory-mapped device. 6 DMA6_MMAP 5 DMA5_MMAP 4 3 Reserved DMA3_MMAP 2 DMA2_MMAP 1 DMA1_MMAP 0 DMA0_MMAP Programming Notes A bit field in this register (GPDMAMMIO) is ignored if the corresponding channel is mapped to an internal UART via the GPDMAEXTCHMAPB register (see page 11-8). ElanTMSC520 Microcontroller Register Set Manual 11-5 GP DMA Controller Registers GP-DMA Resource Channel Map A (GPDMAEXTCHMAPA) Memory-Mapped MMCR Offset D82h 15 Bit Reset R/W 14 13 12 11 10 9 8 GPDRQ3_CHSEL[3-0] 1 1 R/W 7 6 5 4 3 1 1 1 GPDRQ2_CHSEL[3-0] 1 R/W 2 1 0 1 1 Bit Reset R/W GPDRQ1_CHSEL[3-0] 1 1 R/W 1 1 1 GPDRQ0_CHSEL[3-0] 1 R/W 1 1 Register Description This register indicates the channel mapping for the GPDRQ3-GPDRQ0 and GPDACK3-GPDACK0 pins. Bit Definitions Bit 15-12 Name GPDRQ3_ CHSEL[3-0] Function GPDRQ3 Channel Mapping Map the GPDRQ3 and GPDACK3 pins to a GP-DMA channel: 0000 = Channel 0 0001 = Channel 1 0010 = Channel 2 0011 = Channel 3 0101 = Channel 5 0110 = Channel 6 0111 = Channel 7 All other values are treated as unconnected. 11-8 GPDRQ2_ CHSEL[3-0] GPDRQ2 Channel Mapping Map the GPDRQ2 and GPDACK2 pins to a GP-DMA channel: 0000 = Channel 0 0001 = Channel 1 0010 = Channel 2 0011 = Channel 3 0101 = Channel 5 0110 = Channel 6 0111 = Channel 7 All other values are treated as unconnected. 11-6 ElanTMSC520 Microcontroller Register Set Manual GP DMA Controller Registers Bit 7-4 Name GPDRQ1_ CHSEL[3-0] Function GPDRQ1 Channel Mapping Map the GPDRQ1 and GPDACK1 pins to a GP-DMA channel: 0000 = Channel 0 0001 = Channel 1 0010 = Channel 2 0011 = Channel 3 0101 = Channel 5 0110 = Channel 6 0111 = Channel 7 All other values are treated as unconnected. 3-0 GPDRQ0_ CHSEL[3-0] GPDRQ0 Channel Mapping Map the GPDRQ0 and GPDACK0 pins to a GP-DMA channel: 0000 = Channel 0 0001 = Channel 1 0010 = Channel 2 0011 = Channel 3 0101 = Channel 5 0110 = Channel 6 0111 = Channel 7 All other values are treated as unconnected. Programming Notes ElanTMSC520 Microcontroller Register Set Manual 11-7 GP DMA Controller Registers GP-DMA Resource Channel Map B (GPDMAEXTCHMAPB) Memory-Mapped MMCR Offset D84h 15 Bit Reset R/W 14 13 12 11 10 9 8 TXDRQ2_CHSEL[3-0] 1 1 R/W 7 6 5 4 3 1 1 1 TXDRQ1_CHSEL[3-0] 1 R/W 2 1 0 1 1 Bit Reset R/W RXDRQ2_CHSEL[3-0] 1 1 R/W 1 1 1 RXDRQ1_CHSEL[3-0] 1 R/W 1 1 Register Description This register indicates the channel mapping for the internal serial port request signals: txdrq2-txdrq1 and rxdrq2- rxdrq1. Bit Definitions Bit 15-12 Name TXDRQ2_ CHSEL[3-0] Function TXDRQ2 Channel Mapping Map the txdrq2 and txdack2 internal signals to a GP-DMA channel: 0000 = Channel 0 0001 = Channel 1 0010 = Channel 2 0011 = Channel 3 All other values are treated as unconnected. 11-8 TXDRQ1_ CHSEL[3-0] TXDRQ1 Channel Mapping Map the txdrq1 and txdack1 internal signals to a GP-DMA channel: 0000 = Channel 0 0001 = Channel 1 0010 = Channel 2 0011 = Channel 3 All other values are treated as unconnected. 7-4 RXDRQ2_ CHSEL[3-0] RXDRQ2 Channel Mapping Map rxdrq2 and rxdack2 internal signals to a GP-DMA channel: 0000 = Channel 0 0001 = Channel 1 0010 = Channel 2 0011 = Channel 3 All other values are treated as unconnected. 11-8 ElanTMSC520 Microcontroller Register Set Manual GP DMA Controller Registers Bit 3-0 Name RXDRQ1_ CHSEL[3-0] Function RXDRQ1 Channel Mapping Map the rxdrq1 and rxdack1 internal signals to a GP-DMA channel: 0000 = Channel 0 0001 = Channel 1 0010 = Channel 2 0011 = Channel 3 All other values are treated as unconnected. Programming Notes ElanTMSC520 Microcontroller Register Set Manual 11-9 GP DMA Controller Registers GP-DMA Channel 0 Extended Page (GPDMAEXTPG0) Memory-Mapped MMCR Offset D86h 7 Bit Reset R/W 6 Reserved 5 4 3 2 1 0 DMA0ADR[27-24] 0 0 0 0 R/W 0 0 0 0 RSV Register Description This register provides the extended page address for Channel 0. Bit Definitions Bit 7-4 3-0 Name Reserved DMA0ADR [27-24] Function Reserved This bit field should be written to 0 for normal system operation. DMA Channel 0 Extended Page Address This bit field specifies the highest four memory address bits (A27-A24) for Channel 0. Programming Notes The extended page address is used in conjunction with the memory address and the page address registers for the associated channel to make up a 28-bit address (A27-A0). The Channel 0 extended page address bit field (DMA0ADR[27-24]) does not increment or decrement during DMA because this channel does not support enhanced mode. 11-10 ElanTMSC520 Microcontroller Register Set Manual GP DMA Controller Registers GP-DMA Channel 1 Extended Page (GPDMAEXTPG1) Memory-Mapped MMCR Offset D87h 7 Bit Reset R/W 6 Reserved 5 4 3 2 1 0 DMA1ADR[27-24] 0 0 0 0 R/W 0 0 0 0 RSV Register Description This register provides the extended page address for Channel 1. Bit Definitions Bit 7-4 3-0 Name Reserved DMA1ADR [27-24] Function Reserved This bit field should be written to 0 for normal system operation. DMA Channel 1 Extended Page Address This bit field specifies the highest four memory address bits (A27-A24) for Channel 1. Programming Notes The extended page address is used in conjunction with the memory address and the page address registers for the associated channel to make up a 28-bit address (A27-A0). The Channel 1 extended page address bit field (DMA1ADR[27-24]) does not increment or decrement during DMA because this channel does not support enhanced mode. ElanTMSC520 Microcontroller Register Set Manual 11-11 GP DMA Controller Registers GP-DMA Channel 2 Extended Page (GPDMAEXTPG2) Memory-Mapped MMCR Offset D88h 7 Bit Reset R/W 6 Reserved 5 4 3 2 1 0 DMA2ADR[27-24] 0 0 0 0 R/W 0 0 0 0 RSV Register Description This register provides the extended page address for Channel 2. Bit Definitions Bit 7-4 3-0 Name Reserved DMA2ADR [27-24] Function Reserved This bit field should be written to 0 for normal system operation. DMA Channel 2 Extended Page Address This bit field specifies the highest four memory address bits (A27-A24) for Channel 2. Programming Notes The extended page address is used in conjunction with the memory address and the page address registers for the associated channel to make up a 28-bit address (A27-A0). The Channel 2 extended page address bit field (DMA2ADR[27-24]) does not increment or decrement during DMA because this channel does not support enhanced mode. 11-12 ElanTMSC520 Microcontroller Register Set Manual GP DMA Controller Registers GP-DMA Channel 3 Extended Page (GPDMAEXTPG3) Memory-Mapped MMCR Offset D89h 7 Bit Reset R/W 6 Reserved 5 4 3 2 1 0 DMA3ADR[27-24] 0 0 0 0 R/W! 0 0 0 0 RSV Register Description This register provides the extended page address for Channel 3. Bit Definitions Bit 7-4 3-0 Name Reserved DMA3ADR [27-24] Function Reserved This bit field should be written to 0 for normal system operation. DMA Channel 3 Extended Page Address This bit field specifies the highest four memory address bits (A27-A24) for Channel 3. Programming Notes The extended page address is used in conjunction with the memory address and the page address registers for the associated channel to make up a 28-bit address (A27-A0). In enhanced mode, the Channel 3 extended page address bit field (DMA3ADR[27-24]) increments or decrements if the memory address crosses the 16-Mbyte boundary. In normal mode, these bits remain constant during the DMA transfer. Enhanced mode is enabled by setting the ENH_MODE_ENB bit in the GPDMACTL register (see page 11-4). ElanTMSC520 Microcontroller Register Set Manual 11-13 GP DMA Controller Registers GP-DMA Channel 5 Extended Page (GPDMAEXTPG5) Memory-Mapped MMCR Offset D8Ah 7 Bit Reset R/W 6 Reserved 5 4 3 2 1 0 DMA5ADR[27-24] 0 0 0 0 R/W! 0 0 0 0 RSV Register Description This register provides the extended page address for Channel 5. Bit Definitions Bit 7-4 3-0 Name Reserved DMA5ADR [27-24] Function Reserved This bit field should be written to 0 for normal system operation. DMA Channel 5 Extended Page Address This bit field specifies the highest four memory address bits (A27-A24) for Channel 5. Programming Notes The extended page address is used in conjunction with the memory address and the page address registers for the associated channel to make up a 28-bit address (A27-A0). In enhanced mode, the Channel 5 extended page address bit field (DMA5ADR[27-24]) increments or decrements if the memory address crosses the 16-Mbyte boundary. In normal mode, these bits remain constant during the DMA transfer. Enhanced mode is enabled by setting the ENH_MODE_ENB bit in the GPDMACTL register (see page 11-4). 11-14 ElanTMSC520 Microcontroller Register Set Manual GP DMA Controller Registers GP-DMA Channel 6 Extended Page (GPDMAEXTPG6) Memory-Mapped MMCR Offset D8Bh 7 Bit Reset R/W 6 Reserved 5 4 3 2 1 0 DMA6ADR[27-24] 0 0 0 0 R/W! 0 0 0 0 RSV Register Description This register provides the extended page address for Channel 6. Bit Definitions Bit 7-4 3-0 Name Reserved DMA6ADR [27-24] Function Reserved This bit field should be written to 0 for normal system operation. DMA Channel 6 Extended Page Address This bit field specifies the highest four memory address bits (A27-A24) for Channel 6. Programming Notes The extended page address is used in conjunction with the memory address and the page address registers for the associated channel to make up a 28-bit address (A27-A0). In enhanced mode, the Channel 6 extended page address bit field (DMA6ADR[27-24]) increments or decrements if the memory address crosses the 16-Mbyte boundary. In normal mode, these bits remain constant during the DMA transfer. Enhanced mode is enabled by setting the ENH_MODE_ENB bit in the GPDMACTL register (see page 11-4). ElanTMSC520 Microcontroller Register Set Manual 11-15 GP DMA Controller Registers GP-DMA Channel 7 Extended Page (GPDMAEXTPG7) Memory-Mapped MMCR Offset D8Ch 7 Bit Reset R/W 6 Reserved 5 4 3 2 1 0 DMA7ADR[27-24] 0 0 0 0 R/W! 0 0 0 0 RSV Register Description This register provides the extended page address for Channel 7. Bit Definitions Bit 7-4 3-0 Name Reserved DMA7ADR [27-24] Function Reserved This bit field should be written to 0 for normal system operation. DMA Channel 7 Extended Page Address This bit field specifies the highest four memory address bits (A27-A24) for Channel 7. Programming Notes The extended page address is used in conjunction with the memory address and the page address registers for the associated channel to make up a 28-bit address (A27-A0). In enhanced mode, the Channel 7 extended page address bit field (DMA7ADR[27-24]) increments or decrements if the memory address crosses the 16-Mbyte boundary. In normal mode, these bits remain constant during the DMA transfer. Enhanced mode is enabled by setting the ENH_MODE_ENB bit in the GPDMACTL register (see page 11-4). 11-16 ElanTMSC520 Microcontroller Register Set Manual GP DMA Controller Registers GP-DMA Channel 3 Extended Transfer Count (GPDMAEXTTC3) Memory-Mapped MMCR Offset D90h 7 Bit Reset R/W 6 5 4 3 2 1 0 DMA3TC[23-16] 0 0 0 0 R/W! 0 0 0 0 Register Description This register provides extended transfer count bits for Channel 3. Bit Definitions Bit 7-0 Name DMA3TC [23-16] Function DMA Channel 3 Transfer Count Extension This bit field provides the higher 8 bits of the transfer count for DMA Channel 3. In enhanced mode, this bit field is used with the DMA3TC[15-0] bit field in the GPDMA3TC register (see page 11-49) to allow counts up to 16 M (16,777,216) transfers. In normal mode, the value of this bit field (DMA3TC[23-16]) is ignored. Programming Notes Enhanced mode is enabled by setting the ENH_MODE_ENB bit in the GPDMACTL register (see page 11-4). In PCI bus 2.2-compliant designs, software must limit the length of GP bus DMA demand- or block-mode transfers. Very large transfers could cause the PCI Host Bridge target controller to violate the 10-s memory write maximum completion time limit set in the PCI Local Bus Specification, Revision 2.2. ElanTMSC520 Microcontroller Register Set Manual 11-17 GP DMA Controller Registers GP-DMA Channel 5 Extended Transfer Count (GPDMAEXTTC5) Memory-Mapped MMCR Offset D91h 7 Bit Reset R/W 6 5 4 3 2 1 0 DMA5TC[23-16] 0 0 0 0 R/W! 0 0 0 0 Register Description This register provides the extended transfer count bits for Channel 5. Bit Definitions Bit 7-0 Name DMA5TC [23-16] Function DMA Channel 5 Transfer Count Extension This bit field provides the higher 8 bits of the transfer count for DMA Channel 5. In enhanced mode, this bit field is used with the DMA5TC[15-0] bit field in the GPDMA5TC register (see page 11-81) to allow counts up to 16 M (16,777,216) transfers. In normal mode, the value of this bit field (DMA5TC[23-16]) is ignored. Programming Notes Enhanced mode is enabled by setting the ENH_MODE_ENB bit in the GPDMACTL register (see page 11-4). In PCI bus 2.2-compliant designs, software must limit the length of GP bus DMA demand- or block-mode transfers. Very large transfers could cause the PCI Host Bridge target controller to violate the 10-s memory write maximum completion time limit set in the PCI Local Bus Specification, Revision 2.2. 11-18 ElanTMSC520 Microcontroller Register Set Manual GP DMA Controller Registers GP-DMA Channel 6 Extended Transfer Count (GPDMAEXTTC6) Memory-Mapped MMCR Offset D92h 7 Bit Reset R/W 6 5 4 3 2 1 0 DMA6TC[23-16] 0 0 0 0 R/W! 0 0 0 0 Register Description This register provides the extended transfer count bits for Channel 6. Bit Definitions Bit 7-0 Name DMA6TC [23-16] Function DMA Channel 6 Transfer Count Extension This bit field provides the higher 8 bits of the transfer count for DMA Channel 6. In enhanced mode, this bit field is used with the DMA6TC[15-0] bit field in the GPDMA6TC register (see page 11-83) to allow counts up to 16 M (16,777,216) transfers. In normal mode, the value of this bit field (DMA6TC[23-16]) is ignored. Programming Notes Enhanced mode is enabled by setting the ENH_MODE_ENB bit in the GPDMACTL register (see page 11-4). In PCI bus 2.2-compliant designs, software must limit the length of GP bus DMA demand- or block-mode transfers. Very large transfers could cause the PCI Host Bridge target controller to violate the 10-s memory write maximum completion time limit set in the PCI Local Bus Specification, Revision 2.2. ElanTMSC520 Microcontroller Register Set Manual 11-19 GP DMA Controller Registers GP-DMA Channel 7 Extended Transfer Count (GPDMAEXTTC7) Memory-Mapped MMCR Offset D93h 7 Bit Reset R/W 6 5 4 3 2 1 0 DMA7TC[23-16] 0 0 0 0 R/W! 0 0 0 0 Register Description This register provides the extended transfer count bits for Channel 7. Bit Definitions Bit 7-0 Name DMA7TC [23-16] Function DMA Channel 7 Transfer Count Extension This bit field provides the higher 8 bits of the transfer count for DMA Channel 7. In enhanced mode, this bit field is used with the DMA7TC[15-0] bit field in the GPDMA7TC register (see page 11-85) to allow counts up to 16 M (16,777,216) transfers. In normal mode, the value of this bit field (DMA7TC[23-16]) is ignored. Programming Notes Enhanced mode is enabled by setting the ENH_MODE_ENB bit in the GPDMACTL register (see page 11-4). In PCI bus 2.2-compliant designs, software must limit the length of GP bus DMA demand- or block-mode transfers. Very large transfers could cause the PCI Host Bridge target controller to violate the 10-s memory write maximum completion time limit set in the PCI Local Bus Specification, Revision 2.2. 11-20 ElanTMSC520 Microcontroller Register Set Manual GP DMA Controller Registers Buffer Chaining Control (GPDMABCCTL) Memory-Mapped MMCR Offset D98h 7 Bit Reset R/W 6 Reserved 5 4 3 2 1 0 CH7_ CH6_ CH5_ CH3_ BCHN_ENB BCHN_ENB BCHN_ENB BCHN_ENB 0 0 0 R/W 0 R/W 0 R/W 0 R/W 0 0 RSV Register Description This register controls the buffer chaining feature in enhanced mode. Bit Definitions Bit 7-4 3 Name Reserved CH7_BCHN_ ENB Function Reserved This bit field should be written to 0 for normal system operation. Buffer Chaining Enable for Channel 7 This bit enables buffer chaining via the Channel 7 Next Address and Channel 7 Next Transfer Count registers. See the register descriptions beginning on page 11-32 and page 11-40. When this bit is set, the CH7_CBUF_VAL bit in the in the GPDMABCVAL register becomes effective (see page 11-25). 0 = Disable buffer chaining. 1 = Enable buffer chaining (enhanced mode only). Buffer Chaining Enable for Channel 6 This bit enables buffer chaining via the Channel 6 Next Address and Channel 6 Next Transfer Count registers. See the register descriptions beginning on page 11-30 and page 11-38. When this bit is set, the CH6_CBUF_VAL bit in the in the GPDMABCVAL register becomes effective (see page 11-25). 0 = Disable buffer chaining. 1 = Enable buffer chaining (enhanced mode only). Buffer Chaining Enable for Channel 5 This bit enables buffer chaining via the Channel 5 Next Address and Channel 5 Next Transfer Count registers. See the register descriptions beginning on page 11-28 and page 11-36. When this bit is set, the CH5_CBUF_VAL bit in the in the GPDMABCVAL register becomes effective (see page 11-25). 0 = Disable buffer chaining. 1 = Enable buffer chaining (enhanced mode only). Buffer Chaining Enable for Channel 3 This bit enables buffer chaining via the Channel 3 Next Address and Channel 3 Next Transfer Count registers. See the register descriptions beginning on page 11-26 and page 11-34. When this bit is set, the CH3_CBUF_VAL bit in the in the GPDMABCVAL register becomes effective (see page 11-25). 0 = Disable buffer chaining. 1 = Enable buffer chaining (enhanced mode only). 2 CH6_BCHN_ ENB 1 CH5_BCHN_ ENB 0 CH3_BCHN_ ENB Programming Notes This register is ignored unless enhanced mode is enabled. Enhanced mode is enabled by setting the ENH_MODE_ENB bit in the GPDMACTL register (see page 11-4). ElanTMSC520 Microcontroller Register Set Manual 11-21 GP DMA Controller Registers Buffer Chaining Status (GPDMABCSTA) Memory-Mapped MMCR Offset D99h 7 Bit Reset R/W 6 Reserved 5 4 3 2 1 0 CH7_EOB_ CH6_EOB_ CH5_EOB_ CH3_EOB_ STA STA STA STA 0 0 0 R/W! 0 R/W! 0 R/W! 0 R/W! 0 0 RSV Register Description This register provides the status of channels 3, 5, 6, and 7 when buffer chaining is enabled. Bit Definitions Bit 7-4 3 Name Reserved CH7_EOB_ STA Function Reserved This bit field should be written to 0 for normal system operation. End of Current Buffer in Channel 7 This bit is set by the GP bus DMA controller when the current buffer transfer is completed. 0 = The event has not occurred, or software cleared this bit by writing a 1. 1= The current buffer transfer is completed. In addition, an interrupt is generated if bit CH7_INT_ENB is 1 in the GPDMABSINTENB register (see page 11-24). Software should write a 1 to this bit (CH7_EOB_STA) to acknowledge the transfer completion and clear the interrupt condition. This acknowledgment is usually done in the interrupt handling routine if the interrupt is enabled. Writing 0 to this bit has no effect. If this bit is 0, writing a 1 to it has no effect. This bit's value (when read) is meaningful only if buffer chaining is enabled. 2 CH6_EOB_ STA End of Current Buffer in Channel 6 This bit is set by the GP bus DMA controller when the current buffer transfer is completed. 0 = The event has not occurred, or software cleared this bit by writing a 1. 1= The current buffer transfer is completed. In addition, an interrupt is generated if bit CH6_INT_ENB is 1 in the GPDMABSINTENB register (see page 11-24). Software should write a 1 to this bit (CH6_EOB_STA) to acknowledge the transfer completion and clear the interrupt condition. This acknowledgment is usually done in the interrupt handling routine if the interrupt is enabled. Writing 0 to this bit has no effect. If this bit is 0, writing a 1 to it has no effect. This bit's value (when read) is meaningful only if buffer chaining is enabled. 1 CH5_EOB_ STA End of Current Buffer in Channel 5 This bit is set by the GP bus DMA controller when the current buffer transfer is completed. 0 = The event has not occurred, or software cleared this bit by writing a 1. 1= The current buffer transfer is completed. In addition, an interrupt is generated if bit CH5_INT_ENB is 1 in the GPDMABSINTENB register (see page 11-24). Software should write a 1 to this bit (CH5_EOB_STA) to acknowledge the transfer completion and clear the interrupt condition. This acknowledgment is usually done in the interrupt handling routine if the interrupt is enabled. Writing 0 to this bit has no effect. If this bit is 0, writing a 1 to it has no effect. This bit's value (when read) is meaningful only if buffer chaining is enabled. 11-22 ElanTMSC520 Microcontroller Register Set Manual GP DMA Controller Registers Bit 0 Name CH3_EOB_ STA Function End of Current Buffer in Channel 3 This bit is set by the GP bus DMA controller when the current buffer transfer is completed. 0 = The event has not occurred, or software cleared this bit by writing a 1. 1= The current buffer transfer is completed. In addition, an interrupt is generated if bit CH3_INT_ENB is 1 in the GPDMABSINTENB register (see page 11-24). Software should write a 1 to this bit (CH3_EOB_STA) to acknowledge the transfer completion and clear the interrupt condition. This acknowledgment is usually done in the interrupt handling routine if the interrupt is enabled. Writing 0 to this bit has no effect. If this bit is 0, writing a 1 to it has no effect. This bit's value (when read) is meaningful only if buffer chaining is enabled. Programming Notes The interrupt output is shared between the four channels 3, 5, 6, and 7. If more than one interrupt is asserted and software acknowledges one of the interrupts (by setting the corresponding CHx_EOB_STA bit), any other pending interrupts remain asserted. Software has the option of acknowledging all pending CHx_EOB_STA bits and handling all of the interrupts. Buffer chaining is enabled separately for each channel in the GPDMABCCTL register (see page 11-21). ElanTMSC520 Microcontroller Register Set Manual 11-23 GP DMA Controller Registers Buffer Chaining Interrupt Enable (GPDMABSINTENB) Memory-Mapped MMCR Offset D9Ah 7 Bit Reset R/W 6 Reserved 5 4 3 CH7_INT_ ENB 2 CH6_INT_ ENB 0 R/W 1 CH5_INT_ ENB 0 R/W 0 CH3_INT_ ENB 0 R/W 0 0 RSV 0 0 0 R/W Register Description This register provides the interrupt enable bits for the buffer chaining interrupts. An interrupt is generated when the GP bus DMA controller completes the transfer that is in progress. Software can use this interrupt to queue up a subsequent transfer. Bit Definitions Bit 7-4 3 Name Reserved CH7_INT_ ENB Function Reserved This bit field should be written to 0 for normal system operation. Interrupt Enable for Channel 7 This bit is applicable only if the Buffer Chaining feature is enabled for this channel. 0 = End-of-buffer interrupt for this channel is disabled. 1 = End-of-buffer interrupt for this channel is enabled. Interrupt Enable for Channel 6 This bit is applicable only if the Buffer Chaining feature is enabled for this channel. 0 = End-of-buffer interrupt for this channel is disabled. 1 = End-of-buffer interrupt for this channel is enabled. Interrupt Enable for Channel 5 This bit is applicable only if the Buffer Chaining feature is enabled for this channel. 0 = End-of-buffer interrupt for this channel is disabled. 1 = End-of-buffer interrupt for this channel is enabled. Interrupt Enable for Channel 3 This bit is applicable only if the Buffer Chaining feature is enabled for this channel. 0 = End-of-buffer interrupt for this channel is disabled. 1 = End-of-buffer interrupt for this channel is enabled. 2 CH6_INT_ ENB 1 CH5_INT_ ENB 0 CH3_INT_ ENB Programming Notes Before buffer chaining interrupts are enabled, the DMABCINTMAP register (see page 12-21) must be configured to route the interrupt to the appropriate interrupt request level and priority. Buffer chaining is enabled separately for each channel in the GPDMABCCTL register (see page 11-21). 11-24 ElanTMSC520 Microcontroller Register Set Manual GP DMA Controller Registers Buffer Chaining Valid (GPDMABCVAL) Memory-Mapped MMCR Offset D9Bh 7 Bit Reset R/W 6 Reserved 5 4 3 2 1 0 CH7_ CH6_ CH5_ CH3_ CBUF_VAL CBUF_VAL CBUF_VAL CBUF_VAL 0 0 0 R/W! 0 R/W! 0 R/W! 0 R/W! 0 0 RSV Register Description This register provides the operating interface with the buffer chaining feature. Bit Definitions Bit 7-4 3 Name Reserved CH7_CBUF_ VAL Function Reserved This bit field should be written to 0 for normal system operation. Chaining Buffer Valid for Channel 7 0 = The channel's Next Address registers and Next Transfer Count registers are not valid. Only hardware can clear this bit. Writing a 0 has no effect. 1 = Software sets this bit to indicate that the values of the channel's Next Address registers and Next Transfer Count registers are valid. 2 CH6_CBUF_ VAL Chaining Buffer Valid for Channel 6 0 = The channel's Next Address registers and Next Transfer Count registers are not valid. Only hardware can clear this bit. Writing a 0 has no effect. 1 = Software sets this bit to indicate that the values of the channel's Next Address registers and Next Transfer Count registers are valid. 1 CH5_CBUF_ VAL Chaining Buffer Valid for Channel 5 0 = The channel's Next Address registers and Next Transfer Count registers are not valid. Only hardware can clear this bit. Writing a 0 has no effect. 1 = Software sets this bit to indicate that the values of the channel's Next Address registers and Next Transfer Count registers are valid. 0 CH3_CBUF_ VAL Chaining Buffer Valid for Channel 3 0 = The channel's Next Address registers and Next Transfer Count registers are not valid. Only hardware can clear this bit. Writing a 0 has no effect. 1 = Software sets this bit to indicate that the values of the channel's Next Address registers and Next Transfer Count registers are valid. Programming Notes A channel's CHx_CBUF_VAL bit is ignored if buffer chaining is not enabled for the channel. Buffer chaining is enabled separately for each channel in the GPDMABCCTL register (see page 11-21). If buffer chaining is enabled for a channel, and if the channel's CHx_CBUF_VAL bit is set when the end of the buffer is reached (i.e., when the channel's Transfer Count register reaches 0), then the channel's Memory Address and Transfer Count registers are loaded with the values in the channel's Next Address and Next Count registers, respectively. Then the channel's CHx_CBUF_VAL bit is cleared by the GP bus DMA controller. An interrupt is also generated if the CHx_INT_ENB bit is set in the GPDMABSINTENB register (see page 11-24). If buffer chaining is enabled and software has not set the channel's CHx_CBUF_VAL bit before the end of the buffer is reached, then the GPTC signal is asserted. Note that software can only set the CHx_CBUF_VAL bit to indicate to the hardware that the Next Address and Transfer Count registers contain valid information. The CHx_CBUF_VAL bit can be cleared only by hardware. ElanTMSC520 Microcontroller Register Set Manual 11-25 GP DMA Controller Registers GP-DMA Channel 3 Next Address Low (GPDMANXTADDL3) Memory-Mapped MMCR Offset DA0h 15 Bit Reset R/W 14 13 12 11 10 9 8 DMA3_NXT_ADR[15-8] 0 0 0 0 R/W 7 6 5 4 3 2 1 0 0 0 0 0 Bit Reset R/W DMA3_NXT_ADR[7-0] 0 0 0 0 R/W 0 0 0 0 Register Description This register provides address bits A15-A0 of the next memory address for Channel 3 in buffer chaining mode. Bit Definitions Bit 15-0 Name DMA3_NXT_ ADR[15-0] Function DMA Channel 3 Next Address Low This bit field provides address bits A15-A0 of the next memory buffer to be used by Channel 3 in the buffer chaining mode. Programming Notes The value of this register is ignored if buffer chaining mode is not enabled for this channel in the GPDMABCCTL register (see page 11-21). Bit 0 of this register (GPDMANXTADDL3) is ignored for 16-bit mode transfers, so the buffer address used is always even in 16-bit mode. Software should ensure that 16-bit mode buffers always begin on an even word boundary. 11-26 ElanTMSC520 Microcontroller Register Set Manual GP DMA Controller Registers GP-DMA Channel 3 Next Address High (GPDMANXTADDH3) Memory-Mapped MMCR Offset DA2h 15 Bit Reset R/W 14 Reserved 13 12 11 10 9 8 DMA3_NXT_ADR[27-24] 0 0 0 0 R/W 5 4 3 2 1 0 0 0 0 0 RSV 7 Bit Reset R/W 6 DMA3_NXT_ADR[23-16] 0 0 0 0 R/W 0 0 0 0 Register Description This register provides address bits A27-A16 of the next memory address for Channel 3 in buffer chaining mode. Bit Definitions Bit 15-12 11-0 Name Reserved DMA3_NXT_ ADR[27-16] Function Reserved This bit field should be written to 0 for normal system operation. DMA Channel 3 Next Address High This bit field provides address bits A27-A16 of the next memory buffer to be used by Channel 3 in the buffer chaining mode. Programming Notes The value of this register is ignored if buffer chaining mode is not enabled for this channel in the GPDMABCCTL register (see page 11-21). ElanTMSC520 Microcontroller Register Set Manual 11-27 GP DMA Controller Registers GP-DMA Channel 5 Next Address Low (GPDMANXTADDL5) Memory-Mapped MMCR Offset DA4h 15 Bit Reset R/W 14 13 12 11 10 9 8 DMA5_NXT_ADR[15-8] 0 0 0 0 R/W 7 6 5 4 3 2 1 0 0 0 0 0 Bit Reset R/W DMA5_NXT_ADR[7-0] 0 0 0 0 R/W 0 0 0 0 Register Description This register provides address bits A15-A0 of the next memory address for Channel 5 in buffer chaining mode. Bit Definitions Bit 15-0 Name DMA5_NXT_ ADR[15-0] Function DMA Channel 5 Next Address Low This bit field provides address bits A15-A0 of the next memory buffer to be used by Channel 5 in the buffer chaining mode. Programming Notes The value of this register is ignored if buffer chaining mode is not enabled for this channel in the GPDMABCCTL register (see page 11-21). Bit 0 of this register (GPDMANXTADDL5) is ignored for 16-bit mode transfers, so the buffer address used is always even in 16-bit mode. Software should ensure that 16-bit mode buffers always begin on an even word boundary. 11-28 ElanTMSC520 Microcontroller Register Set Manual GP DMA Controller Registers GP-DMA Channel 5 Next Address High (GPDMANXTADDH5) Memory-Mapped MMCR Offset DA6h 15 Bit Reset R/W 14 Reserved 13 12 11 10 9 8 DMA5_NXT_ADR[27-24] 0 0 0 0 R/W 5 4 3 2 1 0 0 0 0 0 RSV 7 Bit Reset R/W 6 DMA5_NXT_ADR[23-16] 0 0 0 0 R/W 0 0 0 0 Register Description This register provides address bits A27-A16 of the next memory address for Channel 5 in buffer chaining mode. Bit Definitions Bit 15-12 11-0 Name Reserved DMA5_NXT_ ADR[27-16] Function Reserved This bit field should be written to 0 for normal system operation. DMA Channel 5 Next Address High This bit field provides address bits A27-A16 of the next memory buffer to be used by Channel 5 in the buffer chaining mode. Programming Notes The value of this register is ignored if buffer chaining mode is not enabled for this channel in the GPDMABCCTL register (see page 11-21). ElanTMSC520 Microcontroller Register Set Manual 11-29 GP DMA Controller Registers GP-DMA Channel 6 Next Address Low (GPDMANXTADDL6) Memory-Mapped MMCR Offset DA8h 15 Bit Reset R/W 14 13 12 11 10 9 8 DMA6_NXT_ADR[15-8] 0 0 0 0 R/W 7 6 5 4 3 2 1 0 0 0 0 0 Bit Reset R/W DMA6_NXT_ADR[7-0] 0 0 0 0 R/W 0 0 0 0 Register Description This register provides address bits A15-A0 of the next memory address for Channel 6 in buffer chaining mode. Bit Definitions Bit 15-0 Name DMA6_NXT_ ADR[15-0] Function DMA Channel 6 Next Address Low This bit field provides address bits A15-A0 of the next memory buffer to be used by Channel 6 in the buffer chaining mode. Programming Notes The value of this register is ignored if buffer chaining mode is not enabled for this channel in the GPDMABCCTL register (see page 11-21). Bit 0 of this register (GPDMANXTADDL6) is ignored for 16-bit mode transfers, so the buffer address used is always even in 16-bit mode. Software should ensure that 16-bit mode buffers always begin on an even word boundary. 11-30 ElanTMSC520 Microcontroller Register Set Manual GP DMA Controller Registers GP-DMA Channel 6 Next Address High (GPDMANXTADDH6) Memory-Mapped MMCR Offset DAAh 15 Bit Reset R/W 14 Reserved 13 12 11 10 9 8 DMA6_NXT_ADR[27-24] 0 0 0 0 R/W 5 4 3 2 1 0 0 0 0 0 RSV 7 Bit Reset R/W 6 DMA6_NXT_ADR[23-16] 0 0 0 0 R/W 0 0 0 0 Register Description This register provides address bits A27-A16 of the next memory address for Channel 6 in buffer chaining mode. Bit Definitions Bit 15-12 11-0 Name Reserved DMA6_NXT_ ADR[27-16] Function Reserved This bit field should be written to 0 for normal system operation. DMA Channel 6 Next Address High This bit field provides address bits A27-A16 of the next memory buffer to be used by Channel 6 in the buffer chaining mode. Programming Notes The value of this register is ignored if buffer chaining mode is not enabled for this channel in the GPDMABCCTL register (see page 11-21). ElanTMSC520 Microcontroller Register Set Manual 11-31 GP DMA Controller Registers GP-DMA Channel 7 Next Address Low (GPDMANXTADDL7) Memory-Mapped MMCR Offset DACh 15 Bit Reset R/W 14 13 12 11 10 9 8 DMA7_NXT_ADR[15-8] 0 0 0 0 R/W 7 6 5 4 3 2 1 0 0 0 0 0 Bit Reset R/W DMA7_NXT_ADR[7-0] 0 0 0 0 R/W 0 0 0 0 Register Description This register provides address bits A15-A0 of the next memory address for Channel 7 in buffer chaining mode. Bit Definitions Bit 15-0 Name DMA7_NXT_ ADR[15-0] Function DMA Channel 7 Next Address Low This bit field provides address bits A15-A0 of the next memory buffer to be used by Channel 7 in the buffer chaining mode. Programming Notes The value of this register is ignored if buffer chaining mode is not enabled for this channel in the GPDMABCCTL register (see page 11-21). Bit 0 of this register (GPDMANXTADDL7) is ignored for 16-bit mode transfers, so the buffer address used is always even in 16-bit mode. Software should ensure that 16-bit mode buffers always begin on an even word boundary. 11-32 ElanTMSC520 Microcontroller Register Set Manual GP DMA Controller Registers GP-DMA Channel 7 Next Address High (GPDMANXTADDH7) Memory-Mapped MMCR Offset DAEh 15 Bit Reset R/W 14 Reserved 13 12 11 10 9 8 DMA7_NXT_ADR[27-24] 0 0 0 0 R/W 5 4 3 2 1 0 0 0 0 0 RSV 7 Bit Reset R/W 6 DMA7_NXT_ADR[23-16] 0 0 0 0 R/W 0 0 0 0 Register Description This register provides address bits A27-A16 of the next memory address for Channel 7 in buffer chaining mode. Bit Definitions Bit 15-12 11-0 Name Reserved DMA7_NXT_ ADR[27-16] Function Reserved This bit field should be written to 0 for normal system operation. DMA Channel 7 Next Address High This bit field provides address bits A27-A16 of the next memory buffer to be used by Channel 7 in the buffer chaining mode. Programming Notes The value of this register is ignored if buffer chaining mode is not enabled for this channel in the GPDMABCCTL register (see page 11-21). ElanTMSC520 Microcontroller Register Set Manual 11-33 GP DMA Controller Registers GP-DMA Channel 3 Next Transfer Count Low (GPDMANXTTCL3) Memory-Mapped MMCR Offset DB0h 15 Bit Reset R/W 14 13 12 11 10 9 8 DMA3_NXT_TC[15-8] 0 0 0 0 R/W 7 6 5 4 3 2 1 0 0 0 0 0 Bit Reset R/W DMA3_NXT_TC[7-0] 0 0 0 0 R/W 0 0 0 0 Register Description This register provides bits 15-0 of the next transfer count for Channel 3 in buffer chaining mode. Bit Definitions Bit 15-0 Name DMA3_NXT_ TC[15-0] Function DMA Channel 3 Next Transfer Count Low This bit field provides bits 15-0 of the next transfer count to be used by Channel 3 in the buffer chaining mode. Programming Notes The value of this register is ignored if buffer chaining mode is not enabled for this channel in the GPDMABCCTL register (see page 11-21). In PCI bus 2.2-compliant designs, software must limit the length of GP bus DMA demand- or block-mode transfers. Very large transfers could cause the PCI Host Bridge target controller to violate the 10-s memory write maximum completion time limit set in the PCI Local Bus Specification, Revision 2.2. 11-34 ElanTMSC520 Microcontroller Register Set Manual GP DMA Controller Registers GP-DMA Channel 3 Next Transfer Count High (GPDMANXTTCH3) Memory-Mapped MMCR Offset DB2h 7 Bit Reset R/W 6 5 4 3 2 1 0 DMA3_NXT_TC[23-16] 0 0 0 0 R/W 0 0 0 0 Register Description This register provides bits 23-16 of the next transfer count for Channel 3 in buffer chaining mode. Bit Definitions Bit 7-0 Name DMA3_NXT_ TC[23-16] Function DMA Channel 3 Next Transfer Count High This bit field provides bits 23-16 of the next transfer count to be used by Channel 3 in the buffer chaining mode. Programming Notes The value of this register is ignored if buffer chaining mode is not enabled for this channel in the GPDMABCCTL register (see page 11-21). In PCI bus 2.2-compliant designs, software must limit the length of GP bus DMA demand- or block-mode transfers. Very large transfers could cause the PCI Host Bridge target controller to violate the 10-s memory write maximum completion time limit set in the PCI Local Bus Specification, Revision 2.2. ElanTMSC520 Microcontroller Register Set Manual 11-35 GP DMA Controller Registers GP-DMA Channel 5 Next Transfer Count Low (GPDMANXTTCL5) Memory-Mapped MMCR Offset DB4h 15 Bit Reset R/W 14 13 12 11 10 9 8 DMA5_NXT_TC[15-8] 0 0 0 0 R/W 7 6 5 4 3 2 1 0 0 0 0 0 Bit Reset R/W DMA5_NXT_TC[7-0] 0 0 0 0 R/W 0 0 0 0 Register Description This register provides bits 15-0 of the next transfer count for Channel 5 in buffer chaining mode. Bit Definitions Bit 15-0 Name DMA5_NXT_ TC[15-0] Function DMA Channel 5 Next Transfer Count Low This bit field provides bits 15-0 of the next transfer count to be used by Channel 5 in the buffer chaining mode. Programming Notes The value of this register is ignored if buffer chaining mode is not enabled for this channel in the GPDMABCCTL register (see page 11-21). In PCI bus 2.2-compliant designs, software must limit the length of GP bus DMA demand- or block-mode transfers. Very large transfers could cause the PCI Host Bridge target controller to violate the 10-s memory write maximum completion time limit set in the PCI Local Bus Specification, Revision 2.2. 11-36 ElanTMSC520 Microcontroller Register Set Manual GP DMA Controller Registers GP-DMA Channel 5 Next Transfer Count High (GPDMANXTTCH5) Memory-Mapped MMCR Offset DB6h 7 Bit Reset R/W 6 5 4 3 2 1 0 DMA5_NXT_TC[23-16] 0 0 0 0 R/W 0 0 0 0 Register Description This register provides bits 23-16 of the next transfer count for Channel 5 in buffer chaining mode. Bit Definitions Bit 7-0 Name DMA5_NXT_ TC[23-16] Function DMA Channel 5 Next Transfer Count High This bit field provides bits 23-16 of the next transfer count to be used by Channel 5 in the buffer chaining mode. Programming Notes The value of this register is ignored if buffer chaining mode is not enabled for this channel in the GPDMABCCTL register (see page 11-21). In PCI bus 2.2-compliant designs, software must limit the length of GP bus DMA demand- or block-mode transfers. Very large transfers could cause the PCI Host Bridge target controller to violate the 10-s memory write maximum completion time limit set in the PCI Local Bus Specification, Revision 2.2. ElanTMSC520 Microcontroller Register Set Manual 11-37 GP DMA Controller Registers GP-DMA Channel 6 Next Transfer Count Low (GPDMANXTTCL6) Memory-Mapped MMCR Offset DB8h 15 Bit Reset R/W 14 13 12 11 10 9 8 DMA6_NXT_TC[15-8] 0 0 0 0 R/W 7 6 5 4 3 2 1 0 0 0 0 0 Bit Reset R/W DMA6_NXT_TC[7-0] 0 0 0 0 R/W 0 0 0 0 Register Description This register provides bits 15-0 of the next transfer count for Channel 6 in buffer chaining mode. Bit Definitions Bit 15-0 Name DMA6_NXT_ TC[15-0] Function DMA Channel 6 Next Transfer Count Low This bit field provides bits 15-0 of the next transfer count to be used by Channel 6 in the buffer chaining mode. Programming Notes The value of this register is ignored if buffer chaining mode is not enabled for this channel in the GPDMABCCTL register (see page 11-21). In PCI bus 2.2-compliant designs, software must limit the length of GP bus DMA demand- or block-mode transfers. Very large transfers could cause the PCI Host Bridge target controller to violate the 10-s memory write maximum completion time limit set in the PCI Local Bus Specification, Revision 2.2. 11-38 ElanTMSC520 Microcontroller Register Set Manual GP DMA Controller Registers GP-DMA Channel 6 Next Transfer Count High (GPDMANXTTCH6) Memory-Mapped MMCR Offset DBAh 7 Bit Reset R/W 6 5 4 3 2 1 0 DMA6_NXT_TC[23-16] 0 0 0 0 R/W 0 0 0 0 Register Description This register provides bits 23-16 of the next transfer count for Channel 6 in buffer chaining mode. Bit Definitions Bit 7-0 Name DMA6_NXT_ TC[23-16] Function DMA Channel 6 Next Transfer Count High This bit field provides bits 23-16 of the next transfer count to be used by Channel 6 in the buffer chaining mode. Programming Notes The value of this register is ignored if buffer chaining mode is not enabled for this channel in the GPDMABCCTL register (see page 11-21). In PCI bus 2.2-compliant designs, software must limit the length of GP bus DMA demand- or block-mode transfers. Very large transfers could cause the PCI Host Bridge target controller to violate the 10-s memory write maximum completion time limit set in the PCI Local Bus Specification, Revision 2.2. ElanTMSC520 Microcontroller Register Set Manual 11-39 GP DMA Controller Registers GP-DMA Channel 7 Next Transfer Count Low (GPDMANXTTCL7) Memory-Mapped MMCR Offset DBCh 15 Bit Reset R/W 14 13 12 11 10 9 8 DMA7_NXT_TC[15-8] 0 0 0 0 R/W 7 6 5 4 3 2 1 0 0 0 0 0 Bit Reset R/W DMA7_NXT_TC[7-0] 0 0 0 0 R/W 0 0 0 0 Register Description This register provides bits 15-0 of the next transfer count for Channel 7 in buffer chaining mode. Bit Definitions Bit 15-0 Name DMA7_NXT_ TC[15-0] Function DMA Channel 7 Next Transfer Count Low This bit field provides bits 15-0 of the next transfer count to be used by Channel 7 in the buffer chaining mode. Programming Notes The value of this register is ignored if buffer chaining mode is not enabled for this channel in the GPDMABCCTL register (see page 11-21). In PCI bus 2.2-compliant designs, software must limit the length of GP bus DMA demand- or block-mode transfers. Very large transfers could cause the PCI Host Bridge target controller to violate the 10-s memory write maximum completion time limit set in the PCI Local Bus Specification, Revision 2.2. 11-40 ElanTMSC520 Microcontroller Register Set Manual GP DMA Controller Registers GP-DMA Channel 7 Next Transfer Count High (GPDMANXTTCH7) Memory-Mapped MMCR Offset DBEh 7 Bit Reset R/W 6 5 4 3 2 1 0 DMA7_NXT_TC[23-16] 0 0 0 0 R/W 0 0 0 0 Register Description This register provides bits 23-16 of the next transfer count for Channel 7 in buffer chaining mode. Bit Definitions Bit 7-0 Name DMA7_NXT_ TC[23-16] Function DMA Channel 7 Next Transfer Count High This bit field provides bits 23-16 of the next transfer count to be used by Channel 7 in the buffer chaining mode. Programming Notes The value of this register is ignored if buffer chaining mode is not enabled for this channel in the GPDMABCCTL register (see page 11-21). In PCI bus 2.2-compliant designs, software must limit the length of GP bus DMA demand- or block-mode transfers. Very large transfers could cause the PCI Host Bridge target controller to violate the 10-s memory write maximum completion time limit set in the PCI Local Bus Specification, Revision 2.2. ElanTMSC520 Microcontroller Register Set Manual 11-41 GP DMA Controller Registers Slave DMA Channel 0 Memory Address (GPDMA0MAR) Direct-Mapped I/O Address 0000h 7 Bit Reset R/W 6 5 4 3 2 1 0 DMA0MAR[15-0] x x x x R/W! x x x x Register Description This register contains bits 15-0 of the memory address for Channel 0 during DMA operation. Bit Definitions Bit 7-0 Name DMA0MAR [15-0] Function Lower 16 Bits of DMA Channel 0 Memory Address This 8-bit field is used in two successive I/O accesses to read or write the channel's memory address bits 15-0. Bits 7-0 of the channel's memory address can be read from or written to this bit field immediately after a write to the SLDMACBP register (see page 11-57). Bits 15-8 of the channel's memory address can be read from or written to this bit field immediately after memory address bits 7-0 are read from or written to this bit field. Programming Notes To ensure that the lower byte of this register (GPDMA0MAR) is always accessed first, software should precede any access to this register with a write to the SLDMACBP register (see page 11-57) to clear the slave DMA byte pointer. The value in this register (GPDMA0MAR) is used with the values in the GPDMA0PG register (see page 11-69) and the GPDMAEXTPG0 register (see page 11-10) to generate DMA address bits 27-0. 11-42 ElanTMSC520 Microcontroller Register Set Manual GP DMA Controller Registers Slave DMA Channel 0 Transfer Count (GPDMA0TC) Direct-Mapped I/O Address 0001h 7 Bit Reset R/W 6 5 4 3 2 1 0 DMA0TC[15-0] x x x x R/W! x x x x Register Description This register contains bits 15-0 of the transfer count for Channel 0 during DMA operation. Bit Definitions Bit 7-0 Name DMA0TC [15-0] Function DMA Channel 0 Transfer Count (16-Bit Register) This 8-bit field is used in two successive I/O accesses to read or write the channel's transfer count bits 15-0. Bits 7-0 of the channel's transfer count can be read from or written to this bit field immediately after a write to the SLDMACBP register (see page 11-57). Bits 15-8 of the channel's transfer count can be read from or written to this bit field immediately after transfer count bits 7-0 are read from or written to this bit field. The actual number of transfers is one more than the programmed transfer count value. Programming Notes To ensure that the lower byte of this register (GPDMA0TC) is always accessed first, software should precede any access to this register with a write to the SLDMACBP register (see page 11-57) to clear the slave DMA byte pointer. In PCI bus 2.2-compliant designs, software must limit the length of GP bus DMA demand- or block-mode transfers. Very large transfers could cause the PCI Host Bridge target controller to violate the 10-s memory write maximum completion time limit set in the PCI Local Bus Specification, Revision 2.2. ElanTMSC520 Microcontroller Register Set Manual 11-43 GP DMA Controller Registers Slave DMA Channel 1 Memory Address (GPDMA1MAR) Direct-Mapped I/O Address 0002h 7 Bit Reset R/W 6 5 4 3 2 1 0 DMA1MAR[15-0] x x x x R/W! x x x x Register Description This register contains bits 15-0 of the memory address for Channel 1 during DMA operation. Bit Definitions Bit 7-0 Name DMA1MAR [15-0] Function Lower 16 Bits of DMA Channel 1 Memory Address This 8-bit field is used in two successive I/O accesses to read or write the channel's memory address bits 15-0. Bits 7-0 of the channel's memory address can be read from or written to this bit field immediately after a write to the SLDMACBP register (see page 11-57). Bits 15-8 of the channel's memory address can be read from or written to this bit field immediately after memory address bits 7-0 are read from or written to this bit field. Programming Notes To ensure that the lower byte of this register (GPDMA1MAR) is always accessed first, software should precede any access to this register with a write to the SLDMACBP register (see page 11-57) to clear the slave DMA byte pointer. The value in this register (GPDMA1MAR) is used with the values in the GPDMA1PG register (see page 11-65) and the GPDMAEXTPG1 register (see page 11-11) to generate DMA address bits 27-0. 11-44 ElanTMSC520 Microcontroller Register Set Manual GP DMA Controller Registers Slave DMA Channel 1 Transfer Count (GPDMA1TC) Direct-Mapped I/O Address 0003h 7 Bit Reset R/W 6 5 4 3 2 1 0 DMA1TC[15-0] x x x x R/W! x x x x Register Description This register contains bits 15-0 of the transfer count for Channel 1 during DMA operation. Bit Definitions Bit 7-0 Name DMA1TC [15-0] Function DMA Channel 1 Transfer Count (16-Bit Register) This 8-bit field is used in two successive I/O accesses to read or write the channel's transfer count bits 15-0. Bits 7-0 of the channel's transfer count can be read from or written to this bit field immediately after a write to the SLDMACBP register (see page 11-57). Bits 15-8 of the channel's transfer count can be read from or written to this bit field immediately after transfer count bits 7-0 are read from or written to this bit field. The actual number of transfers is one more than the programmed transfer count value. Programming Notes To ensure that the lower byte of this register (GPDMA1TC) is always accessed first, software should precede any access to this register with a write to the SLDMACBP register (see page 11-57) to clear the slave DMA byte pointer. In PCI bus 2.2-compliant designs, software must limit the length of GP bus DMA demand- or block-mode transfers. Very large transfers could cause the PCI Host Bridge target controller to violate the 10-s memory write maximum completion time limit set in the PCI Local Bus Specification, Revision 2.2. ElanTMSC520 Microcontroller Register Set Manual 11-45 GP DMA Controller Registers Slave DMA Channel 2 Memory Address (GPDMA2MAR) Direct-Mapped I/O Address 0004h 7 Bit Reset R/W 6 5 4 3 2 1 0 DMA2MAR[15-0] x x x x R/W! x x x x Register Description This register contains bits 15-0 of the memory address for Channel 2 during DMA operation. Bit Definitions Bit 7-0 Name DMA2MAR [15-0] Function Lower 16 Bits of DMA Channel 2 Memory Address This 8-bit field is used in two successive I/O accesses to read or write the channel's memory address bits 15-0. Bits 7-0 of the channel's memory address can be read from or written to this bit field immediately after a write to the SLDMACBP register (see page 11-57). Bits 15-8 of the channel's memory address can be read from or written to this bit field immediately after memory address bits 7-0 are read from or written to this bit field. Programming Notes To ensure that the lower byte of this register (GPDMA2MAR) is always accessed first, software should precede any access to this register with a write to the SLDMACBP register (see page 11-57) to clear the slave DMA byte pointer. The value in this register (GPDMA2MAR) is used with the values in the GPDMA2PG register (see page 11-63) and the GPDMAEXTPG2 register (see page 11-12) to generate DMA address bits 27-0. 11-46 ElanTMSC520 Microcontroller Register Set Manual GP DMA Controller Registers Slave DMA Channel 2 Transfer Count (GPDMA2TC) Direct-Mapped I/O Address 0005h 7 Bit Reset R/W 6 5 4 3 2 1 0 DMA2TC[15-0] x x x x R/W! x x x x Register Description This register contains bits 15-0 of the transfer count for Channel 2 during DMA operation. Bit Definitions Bit 7-0 Name DMA2TC [15-0] Function DMA Channel 2 Transfer Count (16-Bit Register) This 8-bit field is used in two successive I/O accesses to read or write the channel's transfer count bits 15-0. Bits 7-0 of the channel's transfer count can be read from or written to this bit field immediately after a write to the SLDMACBP register (see page 11-57). Bits 15-8 of the channel's transfer count can be read from or written to this bit field immediately after transfer count bits 7-0 are read from or written to this bit field. The actual number of transfers is one more than the programmed transfer count value. Programming Notes To ensure that the lower byte of this register (GPDMA2TC) is always accessed first, software should precede any access to this register with a write to the SLDMACBP register (see page 11-57) to clear the slave DMA byte pointer. In PCI bus 2.2-compliant designs, software must limit the length of GP bus DMA demand- or block-mode transfers. Very large transfers could cause the PCI Host Bridge target controller to violate the 10-s memory write maximum completion time limit set in the PCI Local Bus Specification, Revision 2.2. ElanTMSC520 Microcontroller Register Set Manual 11-47 GP DMA Controller Registers Slave DMA Channel 3 Memory Address (GPDMA3MAR) Direct-Mapped I/O Address 0006h 7 Bit Reset R/W 6 5 4 3 2 1 0 DMA3MAR[15-0] x x x x R/W! x x x x Register Description This register contains bits 15-0 of the memory address for Channel 3 during DMA operation. Bit Definitions Bit 7-0 Name DMA3MAR [15-0] Function Lower 16 Bits of DMA Channel 3 Memory Address This 8-bit field is used in two successive I/O accesses to read or write the channel's memory address bits 15-0. Bits 7-0 of the channel's memory address can be read from or written to this bit field immediately after a write to the SLDMACBP register (see page 11-57). Bits 15-8 of the channel's memory address can be read from or written to this bit field immediately after memory address bits 7-0 are read from or written to this bit field. Programming Notes To ensure that the lower byte of this register (GPDMA3MAR) is always accessed first, software should precede any access to this register with a write to the SLDMACBP register (see page 11-57) to clear the slave DMA byte pointer. The value in this register (GPDMA3MAR) is used with the values in the GPDMA3PG register (see page 11-64) and the GPDMAEXTPG3 register (see page 11-13) to generate DMA address bits 27-0. In enhanced mode, this channel can be programmed for 16-bit DMA transfers (see the descriptions for GPDMACTL register bits CH3_ALT_SIZE and ENH_MODE_ENB, on page 11-4). For 16-bit transfers, this register (GPDMA3MAR) holds address bits 16-1 and address bit 0 is always 0 (i.e., the 16-bit transfers are word-aligned). Because of this, software must load this register with the desired memory address divided by 2 for 16-bit transfers. 11-48 ElanTMSC520 Microcontroller Register Set Manual GP DMA Controller Registers Slave DMA Channel 3 Transfer Count (GPDMA3TC) Direct-Mapped I/O Address 0007h 7 Bit Reset R/W 6 5 4 3 2 1 0 DMA3TC[15-0] x x x x R/W! x x x x Register Description This register contains bits 15-0 of the transfer count for Channel 3 during DMA operation. Bit Definitions Bit 7-0 Name DMA3TC [15-0] Function DMA Channel 3 Transfer Count (16-Bit Register) This 8-bit field is used in two successive I/O accesses to read or write the channel's transfer count bits 15-0. Bits 7-0 of the channel's transfer count can be read from or written to this bit field immediately after a write to the SLDMACBP register (see page 11-57). Bits 15-8 of the channel's transfer count can be read from or written to this bit field immediately after transfer count bits 7-0 are read from or written to this bit field. The actual number of transfers is one more than the programmed transfer count value. Programming Notes To ensure that the lower byte of this register (GPDMA3TC) is always accessed first, software should precede any access to this register with a write to the SLDMACBP register (see page 11-57) to clear the slave DMA byte pointer. The value in this register (GPDMA3TC) can be used with the value in the GPDMAEXTTC3 register (see page 11-17) to allow counts of up to 16 M (16,777,216) transfers. In PCI bus 2.2-compliant designs, software must limit the length of GP bus DMA demand- or block-mode transfers. Very large transfers could cause the PCI Host Bridge target controller to violate the 10-s memory write maximum completion time limit set in the PCI Local Bus Specification, Revision 2.2. ElanTMSC520 Microcontroller Register Set Manual 11-49 GP DMA Controller Registers Slave DMA Channel 0-3 Status (SLDMASTA) Direct-Mapped I/O Address 0008h 7 Bit Reset R/W 6 DMAR2 ? R 5 DMAR1 ? R 4 DMAR0 ? R 3 TC3 0 R! 2 TC2 0 R! 1 TC1 0 R! 0 TC0 0 R! DMAR3 ? R Register Description This register indicates the request status and terminal count status for Channels 0-3. Bit Definitions Bit 7 Name DMAR3 Function Channel 3 DMA Request 0 = Channel 3 DMA request not pending 1 = Channel 3 DMA request pending Channel 2 DMA Request 0 = Channel 2 DMA request not pending 1 = Channel 2 DMA request pending Channel 1 DMA Request 0 = Channel 1 DMA request not pending 1 = Channel 1 DMA request pending Channel 0 DMA Request 0 = Channel 0 DMA request not pending 1 = Channel 0 DMA request pending Channel 3 Terminal Count 0 = Channel 3 terminal count not detected 1 = Channel 3 terminal count detected Channel 2 Terminal Count 0 = Channel 2 terminal count not detected 1 = Channel 2 terminal count detected Channel 1 Terminal Count 0 = Channel 1 terminal count not detected 1 = Channel 1 terminal count detected Channel 0 Terminal Count 0 = Channel 0 terminal count not detected 1 = Channel 0 terminal count detected 6 DMAR2 5 DMAR1 4 DMAR0 3 TC3 2 TC2 1 TC1 0 TC0 Programming Notes Bits 3-0 of this register are reset when read. Any read from this register (SLDMASTA) clears bits 3-0. 11-50 ElanTMSC520 Microcontroller Register Set Manual GP DMA Controller Registers Slave DMA Channel 0-3 Control (SLDMACTL) Direct-Mapped I/O Address 0008h 7 Bit Reset R/W 6 DRQSEN 0 W 5 WRTSEL 0 W 4 PRITYPE 0 W 3 COMPTIM 0 W 2 DMA_DIS 0 W 1 Reserved 0 RSV 0 DAKSEN 0 W 0 Register Description This register provides the control function for Channels 0-3. Bit Definitions Bit 7 Name DAKSEN Function Internal dackx Sense In a discrete DMA controller, this bit controls the polarity of all dackx outputs from the slave DMA controller: 0 = Asserted Low 1 = Asserted High System logic external to the DMA controller expects the DMA controller to drive active Low dackx outputs. This bit must be written to 0 for proper system operation. 6 DRQSEN Internal drqx Sense In a discrete DMA controller, this bit controls the polarity of all drqx inputs to the slave DMA controller: 0 = Asserted High 1 = Asserted Low System logic external to the DMA controller expects the DMA controller to respond to active High drqx inputs. This bit must be written to 0 for proper system operation. 5 WRTSEL Write Selection Control 0 = Late write selection. 1 = Extended (early) write selection. Write command signals (GPIOWR and GPMEMWR) are asserted one clock early. Enabling this feature results in timing changes on the GP bus that can violate the ISA specification. This bit has no effect when the COMPTIM bit is 1. 4 PRITYPE Priority Type 0 = Fixed priority 1 = Rotating priority Compressed Timing 0 = Normal timing. 1 = Compressed timing. Read command signals (GPIORD and GPMEMRD) have a one clock pulse width. Enabling this feature results in timing changes on the GP bus that can violate the ISA specification. 3 COMPTIM 2 DMA_DIS Disable DMA Controller 0 = DMA requests are enabled. 1 = DMA requests are ignored but DMA registers are available to the CPU. The DMA controller should be disabled prior to programming it in order to prevent unintended transfers from occurring during the DMA controller programming operation. Care should also be taken to ensure that the DMA controller is idle before disabling it. If the DMA controller is performing a transfer when software disables it, abnormal system operation can occur. ElanTMSC520 Microcontroller Register Set Manual 11-51 GP DMA Controller Registers Bit 1-0 Name Reserved Function Reserved This bit field should be written to 0 for normal system operation. Programming Notes If DMA Channel 0, 1, 2, or 3 is used by an internal UART, the DAKSEN, DRQSEN, WRTSEL, and COMPTIM bit fields must be 0 (the default). 11-52 ElanTMSC520 Microcontroller Register Set Manual GP DMA Controller Registers Slave Software DRQ(n) Request (SLDMASWREQ) Direct-Mapped I/O Address 0009h 7 Bit Reset R/W 6 5 Reserved 4 3 2 REQDMA 1 0 REQSEL[1-0] x W x 0 0 0 RSV 0 0 x W Register Description This register is used to initiate a software DMA request for one of Channels 0-3. Bit Definitions Bit 7-3 2 Name Reserved REQDMA Function Reserved This bit field should be written to 0 for normal system operation. Software DMA Request 0 = Clear the request bit for the channel selected by the REQSEL bit field. 1 = Set the request bit for the channel selected by the REQSEL bit field. The request bit is cleared internally after the corresponding channel has reached the end of its transfer count. 1-0 REQSEL[1-0] DMA Channel Select This bit field selects the DMA channel that is to latch the REQDMA bit internally to assert or deassert a DMA request via software: 00 = Select Channel 0 for internal DMA request per the REQDMA bit. 01 = Select Channel 1 for internal DMA request per the REQDMA bit. 10 = Select Channel 2 for internal DMA request per the REQDMA bit. 11 = Select Channel 3 for internal DMA request per the REQDMA bit. Programming Notes ElanTMSC520 Microcontroller Register Set Manual 11-53 GP DMA Controller Registers Slave DMA Channel 0-3 Mask (SLDMAMSK) Direct-Mapped I/O Address 000Ah 7 Bit Reset R/W 6 5 Reserved 4 3 2 CHMASK 1 0 MSKSEL[1-0] x W x 0 0 0 RSV 0 0 x W Register Description This register provides a mask or unmask capability for the DMA request signal to each of Channels 0-3. Bit Definitions Bit 7-3 2 Name Reserved CHMASK Function Reserved This bit field should be written to 0 for normal system operation. DMA Channel Mask 0 = Clear the mask bit for the channel selected by the MSKSEL bit field. 1 = Set the mask bit for the channel selected by the MSKSEL bit field. If the AINIT bit is 0 in the SLDMAMODE register (see page 11-55), the mask bit is set internally when the corresponding channel reaches the end of its transfer count. If the AINIT bit is 1, the mask bit remains clear when the transfer ends. 1-0 MSKSEL[1-0] DMA Channel Mask Select This bit field selects the DMA channel that is to latch the CHMASK bit internally to mask or unmask the DMA request signal into the specified DMA channel: 00 = Mask or unmask DMA Channel 0 per the CHMASK bit. 01 = Mask or unmask DMA Channel 1 per the CHMASK bit. 10 = Mask or unmask DMA Channel 2 per the CHMASK bit. 11 = Mask or unmask DMA Channel 3 per the CHMASK bit. Programming Notes The same DMA channel masks can be controlled via DMA registers SLDMAMSK, SLDMAMSKRST (see page 11-60), and SLDMAGENMSK (see page 11-61). Before masking an active DMA channel, software must ensure that the DMA request is deasserted. Masking an active channel while it is being granted might cause the system to hang. 11-54 ElanTMSC520 Microcontroller Register Set Manual GP DMA Controller Registers Slave DMA Channel 0-3 Mode (SLDMAMODE) Direct-Mapped I/O Address 000Bh 7 Bit Reset R/W 6 5 ADDDEC x W 4 AINIT x W 3 2 1 0 TRNMOD[1-0] x W x OPSEL[1-0] x W x MODSEL[1-0] x W x Register Description This register indicates the transfer mode for Channels 0-3. Bit Definitions Bit 7-6 Name TRNMOD[1-0] Function Transfer Mode This bit field selects the transfer mode for the channel selected by the MODSEL bit field. 00 = Demand transfer mode 01 = Single transfer mode 10 = Block transfer mode 11 = Cascade mode. (Only Channel 4 should be programmed for cascade mode. All other channels should be programmed for one of the other modes). 5 ADDDEC Address Decrement This bit field selects increment or decrement counting for the channel selected by the MODSEL bit field. 0 = Increment the DMA memory address after each transfer. 1 = Decrement the DMA memory address after each transfer. Automatic Initialization Control This bit field enables automatic initialization for the channel selected by the MODSEL bit field. 0 = Automatic initialization is disabled. 1 = Automatic initialization is enabled. Automatic initialization causes the channel's base address and transfer count registers to be restored to the values they contained prior to the DMA transfer when the transfer count ends. The channel is then ready to perform another DMA transfer without processor intervention as soon as the next DMA request is detected. Automatic initialization must be disabled when buffer chaining mode is used; otherwise unexpected results may occur. 4 AINIT 3-2 OPSEL[1-0] Operation Select This bit field selects the DMA operation for the channel selected by the MODSEL bit field. 00 = Verify mode. The DMA controller acts normally except that no I/O or memory commands are generated, and no data is transferred. 01 = Write transfer. Data is transferred from a DMA-capable I/O or memory-mapped device into system memory. 10 = Read transfer. Data is transferred from system memory to a DMA-capable I/O or memory-mapped device. 11 = Reserved. ElanTMSC520 Microcontroller Register Set Manual 11-55 GP DMA Controller Registers Bit 1-0 Name MODSEL[1-0] Function DMA Channel Select This bit field selects the channel that is to internally latch the other bits written to this register: 00 = Select Channel 0 01 = Select Channel 1 10 = Select Channel 2 11 = Select Channel 3 Programming Notes 11-56 ElanTMSC520 Microcontroller Register Set Manual GP DMA Controller Registers Slave DMA Clear Byte Pointer (SLDMACBP) Direct-Mapped I/O Address 000Ch 7 Bit Reset R/W x 6 5 4 3 2 1 0 SLAVE_CBP[7-0] x x x W! x x x x Register Description This register channel provides a mechanism to adjust the byte pointer to the low byte of the memory address and transfer count registers for Channels 0-3. Bit Definitions Bit 7-0 Name SLAVE_CBP [7-0] Function Slave DMA Clear Byte Pointer The DMA controller's 16-bit memory address and terminal count registers are accessed by writing or reading consecutive 8-bit values to the same direct-mapped I/O address. A single byte pointer is used across the slave DMA controller to determine which byte is accessed if any of these 16-bit registers is read or written. Any access to one of these registers toggles the byte pointer between the low and high bytes. A write of any data to this bit field (SLAVE_CBP) clears the byte pointer so that the next memory address or transfer count register access is to the low byte. Programming Notes ElanTMSC520 Microcontroller Register Set Manual 11-57 GP DMA Controller Registers Slave DMA Controller Reset (SLDMARST) Direct-Mapped I/O Address 000Dh 7 Bit Reset R/W 6 5 4 3 2 1 0 SLAVE_RST[7-0] 0 0 0 0 W! 0 0 0 0 Register Description This register provides a reset mechanism for Channels 0-3. Bit Definitions Bit 7-0 Name SLAVE_RST [7-0] Function Slave DMA Controller Reset A write of any data to this address resets the DMA controller to the same state as a system reset. Programming Notes 11-58 ElanTMSC520 Microcontroller Register Set Manual GP DMA Controller Registers Slave DMA Controller Temporary (SLDMATMP) Direct-Mapped I/O Address 000Dh 7 Bit Reset R/W 6 5 4 3 2 1 0 SLAVE_TMP[7-0] 0 0 0 0 R 0 0 0 0 Register Description This register has no real use in the ELANSC520 microcontroller. It is included for compatibility only. Bit Definitions Bit 7-0 Name SLAVE_TMP [7-0] Function Slave DMA Controller Temporary Register In a discrete DMA controller, this bit field is used as a temporary storage buffer when doing memory-to-memory DMA. Memory-to-memory DMA transfers are not supported in the ELANSC520 microcontroller, so this register is included for compatibility reasons only. Programming Notes ElanTMSC520 Microcontroller Register Set Manual 11-59 GP DMA Controller Registers Slave DMA Mask Reset (SLDMAMSKRST) Direct-Mapped I/O Address 000Eh 7 Bit Reset R/W 6 5 4 3 2 1 0 SLAVE_MSK_RST[7-0] x x x x W! x x x x Register Description This register provides a mechanism to reset the SLDMAGENMSK register (see page 11-61). Bit Definitions Bit 7-0 Name SLAVE_MSK_ RST[7-0] Function Slave DMA Reset Mask Writing any data to this I/O address resets the SLDMAGENMSK register (see page 11-61), thereby activating the four slave DMA channels. Programming Notes The same DMA channel masks can be controlled via DMA registers SLDMAMSK (see page 11-54), SLDMAMSKRST, and SLDMAGENMSK (see page 11-61). Before masking an active DMA channel, software must ensure that the DMA request is deasserted. Masking an active channel while it is being granted might cause the system to hang. 11-60 ElanTMSC520 Microcontroller Register Set Manual GP DMA Controller Registers Slave DMA General Mask (SLDMAGENMSK) Direct-Mapped I/O Address 000Fh 7 Bit Reset R/W 6 Reserved 5 4 3 CH3_DIS 2 CH2_DIS 1 W 1 CH1_DIS 1 W 0 CH0_DIS 1 W 0 0 RSV 0 0 1 W Register Description This register provides a mechanism to mask or unmask the DMA request signal to each of Channels 0-3. Bit Definitions Bit 7-4 3 Name Reserved CH3_DIS Function Reserved This bit field should be written to 0 for normal system operation. DMA Channel 3 Mask 0 = Enable DMA Channel 3 for servicing DMA requests. 1 = Disable DMA Channel 3 from servicing DMA requests. DMA Channel 2 Mask 0 = Enable DMA Channel 2 for servicing DMA requests. 1 = Disable DMA Channel 2 from servicing DMA requests. DMA Channel 1 Mask 0 = Enable DMA Channel 1 for servicing DMA requests. 1 = Disable DMA Channel 1 from servicing DMA requests. DMA Channel 0 Mask 0 = Enable DMA Channel 0 for servicing DMA requests. 1 = Disable DMA Channel 0 from servicing DMA requests. 2 CH2_DIS 1 CH1_DIS 0 CH0_DIS Programming Notes The same DMA channel masks can be controlled via DMA registers SLDMAMSK (see page 11-54), SLDMAMSKRST (see page 11-60), and SLDMAGENMSK. Before masking an active DMA channel, software must ensure that the DMA request is deasserted. Masking an active channel while it is being granted might cause the system to hang. ElanTMSC520 Microcontroller Register Set Manual 11-61 GP DMA Controller Registers General 0 (GPDMAGR0) Direct-Mapped I/O Address 0080h 7 Bit Reset R/W 6 5 4 3 2 1 0 PORT80[7-0] 0 0 0 0 0 0 0 0 R/W Register Description This is a general-purpose register. Bit Definitions Bit 7-0 Name PORT80[7-0] Function General-Purpose R/W Register Writes to this bit field are stored internally and propagated to the GP bus. Reads from this bit field return the internal register value, but are not propagated to the GP bus. Programming Notes In a discrete DMA controller, this register would be the DMA Channel 4 Page register, but in PC/AT-compatible systems DMA Channel 4 is used for the cascade function, so this register is not used by the DMA subsystem. In a PC/AT-compatible system, this I/O address (Port 0080h) is typically used to send BIOS Power-on Self Test (POST) codes to the ISA bus where special hardware can be used to decode the address and display the POST codes. In the ELANSC520 microcontroller, writes to this register are propagated to the GP bus to allow PC/ATcompatible operation. Reads from this register return the internally-stored value only. 11-62 ElanTMSC520 Microcontroller Register Set Manual GP DMA Controller Registers Slave DMA Channel 2 Page (GPDMA2PG) Direct-Mapped I/O Address 0081h 7 Bit Reset R/W 6 5 4 3 2 1 0 DMA2MAR[23-16] 0 0 0 0 0 0 0 0 R/W Register Description This register provides bits 23-16 of the memory address for Channel 2. Bit Definitions Bit 7-0 Name DMA2MAR [23-16] Function DMA Channel 2 Memory Address Bits [23-16] This bit field is used with the values in the GPDMA2MAR register (see page 11-46) and the GPDMAEXTPG2 register (see page 11-12) to generate DMA address bits 27-0. Programming Notes ElanTMSC520 Microcontroller Register Set Manual 11-63 GP DMA Controller Registers Slave DMA Channel 3 Page (GPDMA3PG) Direct-Mapped I/O Address 0082h 7 Bit Reset R/W 6 5 4 3 2 1 0 DMA3MAR[23-16] 0 0 0 0 0 0 0 0 R/W! Register Description This register provides bits 23-16 of the memory address for Channel 3. Bit Definitions Bit 7-0 Name DMA3MAR [23-16] Function DMA Channel 3 Memory Address Bits [23-16] For 8-bit transfers, the value in this bit field is used with the values in the GPDMA3MAR register (see page 11-48) and the GPDMAEXTPG3 register (see page 11-13) to generate DMA address bits 27-0. For 16-bit transfers (enhanced mode only), bits 7-1 of this bit field hold address bits 23-17, and address bit 16 is located in the GPDMA3MAR register (see page 11-48). Bit 0 of this bit field is not used in 16-bit DMA operation. The bit 0 value read back is always the last value written, but the bit is not applied to the system address unless 8-bit operation is selected. Programming Notes In enhanced mode, this channel can be programmed for 16-bit DMA transfers (see the descriptions for GPDMACTL register bits CH3_ALT_SIZE and ENH_MODE_ENB, on page 11-4). In the enhanced mode, this register is updated during DMA cycles if the DMA addresses cross the 64-Kbyte boundary for 8-bit transfers, or cross the 128-Kbyte boundary for 16-bit transfers. 11-64 ElanTMSC520 Microcontroller Register Set Manual GP DMA Controller Registers Slave DMA Channel 1 Page (GPDMA1PG) Direct-Mapped I/O Address 0083h 7 Bit Reset R/W 6 5 4 3 2 1 0 DMA1MAR[23-16] 0 0 0 0 0 0 0 0 R/W Register Description This register provides bits 23-16 of the memory address for Channel 1. Bit Definitions Bit 7-0 Name DMA1MAR [23-16] Function DMA Channel 1 Memory Address Bits [23-16] This bit field is used with the values in the GPDMA1MAR register (see page 11-44) and the GPDMAEXTPG1 register (see page 11-11) to generate DMA address bits 27-0. Programming Notes ElanTMSC520 Microcontroller Register Set Manual 11-65 GP DMA Controller Registers General 1 (GPDMAGR1) Direct-Mapped I/O Address 0084h 7 Bit Reset R/W 6 5 4 3 2 1 0 PORT84[7-0] 0 0 0 0 0 0 0 0 R/W Register Description This is a general-purpose register. Bit Definitions Bit 7-0 Name PORT84[7-0] Function General-Purpose R/W Register Writes to this bit field are stored internally and propagated to the GP bus. Reads from this bit field return the internal register value, but are not propagated to the GP bus. Programming Notes 11-66 ElanTMSC520 Microcontroller Register Set Manual GP DMA Controller Registers General 2 (GPDMAGR2) Direct-Mapped I/O Address 0085h 7 Bit Reset R/W 6 5 4 3 2 1 0 PORT85[7-0] 0 0 0 0 0 0 0 0 R/W Register Description This is a general-purpose register. Bit Definitions Bit 7-0 Name PORT85[7-0] Function General-Purpose R/W Register Writes to this bit field are stored internally and propagated to the GP bus. Reads from this bit field return the internal register value, but are not propagated to the GP bus. Programming Notes ElanTMSC520 Microcontroller Register Set Manual 11-67 GP DMA Controller Registers General 3 (GPDMAGR3) Direct-Mapped I/O Address 0086h 7 Bit Reset R/W 6 5 4 3 2 1 0 PORT86[7-0] 0 0 0 0 0 0 0 0 R/W Register Description This is a general-purpose register. Bit Definitions Bit 7-0 Name PORT86[7-0] Function General-Purpose R/W Register Writes to this bit field are stored internally and propagated to the GP bus. Reads from this bit field return the internal register value, but are not propagated to the GP bus. Programming Notes 11-68 ElanTMSC520 Microcontroller Register Set Manual GP DMA Controller Registers Slave DMA Channel 0 Page (GPDMA0PG) Direct-Mapped I/O Address 0087h 7 Bit Reset R/W 6 5 4 3 2 1 0 DMA0MAR[23-16] 0 0 0 0 0 0 0 0 R/W Register Description This register provides bits 23-16 of the memory address for Channel 0. Bit Definitions Bit 7-0 Name DMA0MAR [23-16] Function DMA Channel 0 Memory Address Bits [23-16] This bit field is used with the values in the GPDMA0MAR register (see page 11-42) and the GPDMAEXTPG0 register (see page 11-10) to generate DMA address bits 27-0. Programming Notes ElanTMSC520 Microcontroller Register Set Manual 11-69 GP DMA Controller Registers General 4 (GPDMAGR4) Direct-Mapped I/O Address 0088h 7 Bit Reset R/W 6 5 4 3 2 1 0 PORT88[7-0] 0 0 0 0 0 0 0 0 R/W Register Description This is a general-purpose register. Bit Definitions Bit 7-0 Name PORT88[7-0] Function General-Purpose R/W Register Writes to this bit field are stored internally and propagated to the GP bus. Reads from this bit field return the internal register value, but are not propagated to the GP bus. Programming Notes 11-70 ElanTMSC520 Microcontroller Register Set Manual GP DMA Controller Registers Master DMA Channel 6 Page (GPDMA6PG) Direct-Mapped I/O Address 0089h 7 Bit Reset R/W 6 5 4 3 2 1 0 DMA6MAR[23-16] 0 0 0 0 R/W! 0 0 0 0 Register Description This register provides bits 23-16 of the memory address for Channel 6. Bit Definitions Bit 7-1 Name DMA6MAR [23-16] Function DMA Channel 6 Memory Address Bits [23-16] For 8-bit transfers (enhanced mode only), the value in this bit field is used with the values in the GPDMA6MAR register (see page 11-82) and the GPDMAEXTPG6 register (see page 11-15) to generate DMA address bits 27-0. For 16-bit transfers, bits 7-1 of this bit field hold address bits 23-17, and address bit 16 is located in the GPDMA6MAR register (see page 11-82). Bit 0 of this bit field is not used in 16-bit DMA operation. The bit 0 value read back is always the last value written, but the bit is not applied to the system address unless 8-bit operation is selected. Programming Notes In enhanced mode, this channel can be programmed for 8-bit DMA transfers (see the descriptions for GPDMACTL register bits CH6_ALT_SIZE and ENH_MODE_ENB, on page 11-4). In enhanced mode, this register is updated during DMA cycles if the DMA addresses cross the 64-Kbyte boundary for 8-bit transfers, or cross the 128-Kbyte boundary for 16-bit transfers. ElanTMSC520 Microcontroller Register Set Manual 11-71 GP DMA Controller Registers Master DMA Channel 7 Page (GPDMA7PG) Direct-Mapped I/O Address 008Ah 7 Bit Reset R/W 6 5 4 3 2 1 0 DMA7MAR[23-16] 0 0 0 0 R/W! 0 0 0 0 Register Description This register provides bits 23-16 of the memory address for Channel 7. Bit Definitions Bit 7-1 Name DMA7MAR [23-16] Function DMA Channel 7 Memory Address Bits [23-17] For 8-bit transfers (enhanced mode only), the value in this bit field is used with the values in the GPDMA7MAR register (see page 11-84) and the GPDMAEXTPG7 register (see page 11-16) to generate DMA address bits 27-0. For 16-bit transfers, bits 7-1 of this bit field hold address bits 23-17, and address bit 16 is located in the GPDMA7MAR register (see page 11-84). Bit 0 of this bit field is not used in 16-bit DMA operation. The bit 0 value read back is always the last value written, but the bit is not applied to the system address unless 8-bit operation is selected. Programming Notes In enhanced mode, this channel can be programmed for 8-bit DMA transfers (see the descriptions for GPDMACTL register bits CH7_ALT_SIZE and ENH_MODE_ENB, on page 11-4). In enhanced mode, this register is updated during DMA cycles if the DMA addresses cross the 64-Kbyte boundary for 8-bit transfers, or cross the 128-Kbyte boundary for 16-bit transfers. 11-72 ElanTMSC520 Microcontroller Register Set Manual GP DMA Controller Registers Master DMA Channel 5 Page (GPDMA5PG) Direct-Mapped I/O Address 008Bh 7 Bit Reset R/W 6 5 4 3 2 1 0 DMA5MAR[23-16] 0 0 0 0 R/W! 0 0 0 0 Register Description This register provides bits 23-16 of the memory address for Channel 5. Bit Definitions Bit 7-1 Name DMA5MAR [23-16] Function DMA Channel 5 Memory Address Bits [23-16] For 8-bit transfers (enhanced mode only), the value in this bit field is used with the values in the GPDMA5MAR register (see page 11-80) and the GPDMAEXTPG5 register (see page 11-14) to generate DMA address bits 27-0. For 16-bit transfers, bits 7-1 of this bit field hold address bits 23-17, and address bit 16 is located in the GPDMA5MAR register (see page 11-80). Bit 0 of this bit field is not used in 16-bit DMA operation. The bit 0 value read back is always the last value written, but the bit is not applied to the system address unless 8-bit operation is selected. Programming Notes In enhanced mode, this channel can be programmed for 8-bit DMA transfers (see the descriptions for GPDMACTL register bits CH5_ALT_SIZE and ENH_MODE_ENB, on page 11-4). In enhanced mode, this register is updated during DMA cycles if the DMA addresses cross the 64-Kbyte boundary for 8-bit transfers, or cross the 128-Kbyte boundary for 16-bit transfers. ElanTMSC520 Microcontroller Register Set Manual 11-73 GP DMA Controller Registers General 5 (GPDMAGR5) Direct-Mapped I/O Address 008Ch 7 Bit Reset R/W 6 5 4 3 2 1 0 PORT8C[7-0] 0 0 0 0 0 0 0 0 R/W Register Description This is a general-purpose register. Bit Definitions Bit 7-0 Name PORT8C[7-0] Function General-Purpose R/W Register Writes to this bit field are stored internally and propagated to the GP bus. Reads from this bit field return the internal register value, but are not propagated to the GP bus. Programming Notes 11-74 ElanTMSC520 Microcontroller Register Set Manual GP DMA Controller Registers General 6 (GPDMAGR6) Direct-Mapped I/O Address 008Dh 7 Bit Reset R/W 6 5 4 3 2 1 0 PORT8D[7-0] 0 0 0 0 0 0 0 0 R/W Register Description This is a general-purpose register. Bit Definitions Bit 7-0 Name PORT8D[7-0] Function General-Purpose R/W Register Writes to this bit field are stored internally and propagated to the GP bus. Reads from this bit field return the internal register value, but are not propagated to the GP bus. Programming Notes ElanTMSC520 Microcontroller Register Set Manual 11-75 GP DMA Controller Registers General 7 (GPDMAGR7) Direct-Mapped I/O Address 008Eh 7 Bit Reset R/W 6 5 4 3 2 1 0 PORT8E[7-0] 0 0 0 0 0 0 0 0 R/W Register Description This is a general-purpose register. Bit Definitions Bit 7-0 Name PORT8E[7-0] Function General-Purpose R/W Register Writes to this bit field are stored internally and propagated to the GP bus. Reads from this bit field return the internal register value, but are not propagated to the GP bus. Programming Notes 11-76 ElanTMSC520 Microcontroller Register Set Manual GP DMA Controller Registers General 8 (GPDMAGR8) Direct-Mapped I/O Address 008Fh 7 Bit Reset R/W 6 5 4 3 2 1 0 PORT8F[7-0] 0 0 0 0 0 0 0 0 R/W Register Description This is a general-purpose register. Bit Definitions Bit 7-0 Name PORT8F[7-0] Function General-Purpose R/W Register Writes to this bit field are stored internally. Reads from this bit field return the internal register value. Programming Notes This general register is slightly different from the other direct-mapped general registers. No GP bus cycles are generated on writes to this I/O address (Port 008Fh). ElanTMSC520 Microcontroller Register Set Manual 11-77 GP DMA Controller Registers Master DMA Channel 4 Memory Address (GPDMA4MAR) Direct-Mapped I/O Address 00C0h 7 Bit Reset R/W 6 5 4 3 2 1 0 DMA4MAR[16-1] x x x x R/W! x x x x Register Description Because Channel 4 is used to cascade the slave DMA controller to the master DMA controller, this register has no real use. Bit Definitions Bit 7-0 Name DMA4MAR [16-1] Function DMA Channel 4 Memory Address In a discrete DMA controller, this bit field holds the lower 16 bits of memory address for DMA Channel 4. Because the drq and dack internal signals for this DMA channel are used to cascade to the slave DMA controller in a PC/AT-compatible system, DMA Channel 4 is not used directly for DMA transfers. So this register has no real function; it is documented only for completeness. For the same reason, there is no corresponding page register for DMA Channel 4. Programming Notes 11-78 ElanTMSC520 Microcontroller Register Set Manual GP DMA Controller Registers Master DMA Channel 4 Transfer Count (GPDMA4TC) Direct-Mapped I/O Address 00C2h 7 Bit Reset R/W 6 5 4 3 2 1 0 DMA4TC[15-0] x x x x R/W! x x x x Register Description Because Channel 4 is used to cascade the slave DMA controller to the master DMA controller, this register has no real use. Bit Definitions Bit 7-0 Name DMA4TC [15-0] Function DMA Channel 4 Transfer Count In a discrete DMA controller, this bit field holds the 16-bit transfer count for DMA Channel 4. Because the drq and dack internal signals for this DMA channel are used to cascade to the slave DMA controller in a PC/AT-compatible system, DMA Channel 4 is not used directly for DMA transfers. So this register has no real function; it is documented only for completeness. Programming Notes ElanTMSC520 Microcontroller Register Set Manual 11-79 GP DMA Controller Registers Master DMA Channel 5 Memory Address (GPDMA5MAR) Direct-Mapped I/O Address 00C4h 7 Bit Reset R/W 6 5 4 3 2 1 0 DMA5MAR[16-1] x x x x R/W! x x x x Register Description This register contains bits 16-1 of the memory address for Channel 5 during DMA operation. Bit Definitions Bit 7-0 Name DMA5MAR [16-1] Function Lower 16 Bits of DMA Channel 5 Memory Address This 8-bit field is used in two successive I/O accesses to read or write the channel's memory address bits 16-1 for 16-bit DMA transfers. Bits 8-1 of the channel's memory address can be read from or written to this bit field immediately after a write to the MSTDMACBP register (see page 11-93). Bits 16-9 of the channel's memory address can be read from or written to this bit field immediately after memory address bits 8-1 are read from or written to this bit field. Programming Notes To ensure that the lower byte of this register (GPDMA5MAR) is always accessed first, software should precede any access to this register with a write to the MSTDMACBP register (see page 11-93) to clear the master DMA byte pointer. The value in this register (GPDMA5MAR) is used with the values in the GPDMA5PG register (see page 11-73) and the GPDMAEXTPG5 register (see page 11-14) to generate DMA address bits 27-0. By default, this channel is set up for PC/AT compatibility (16-bit DMA transfers on the master DMA controller). For 16-bit transfers, this register (GPDMA5MAR) holds address bits 16-1 and address bit 0 is always 0 (i.e., the 16-bit transfers are word-aligned). Because of this, software must load this register with the desired memory address divided by 2 for 16-bit transfers. In enhanced mode, this channel can be programmed for 8-bit DMA transfers (see the descriptions for GPDMACTL register bits CH5_ALT_SIZE and ENH_MODE_ENB, on page 11-4). For 8-bit transfers, this register (GPDMA5MAR) holds address bits 15-0, and address bit 16 is controlled via the GPDMA5PG register (see page 11-73). 11-80 ElanTMSC520 Microcontroller Register Set Manual GP DMA Controller Registers Master DMA Channel 5 Transfer Count (GPDMA5TC) Direct-Mapped I/O Address 00C6h 7 Bit Reset R/W 6 5 4 3 2 1 0 DMA5TC[15-0] x x x x R/W! x x x x Register Description This register contains bits 15-0 of the transfer count for Channel 5 during DMA operation. Bit Definitions Bit 7-0 Name DMA5TC [15-0] Function DMA Channel 5 Transfer Count (16-Bit Register) This 8-bit field is used in two successive I/O accesses to read or write the channel's transfer count bits 15-0. Bits 7-0 of the channel's transfer count can be read from or written to this bit field immediately after a write to the MSTDMACBP register (see page 11-93). Bits 15-8 of the channel's transfer count can be read from or written to this bit field immediately after transfer count bits 7-0 are read from or written to this bit field. The actual number of transfers is one more than the programmed transfer count value. Programming Notes To ensure that the lower byte of this register (GPDMA5TC) is always accessed first, software should precede any access to this register with a write to the MSTDMACBP register (see page 11-93) to clear the master DMA byte pointer. By default, this channel is set up for PC/AT compatibility (16-bit DMA transfers on the master DMA controller). For 16-bit transfers, each transfer is two bytes, so a transfer count of FFFFh results in a transfer of 128 Kbytes. The value in this register (GPDMA5TC) can be used with the value in the GPDMAEXTTC5 register (see page 11-18) to allow counts of up to 16 M (16,777,216) transfers. In PCI bus 2.2-compliant designs, software must limit the length of GP bus DMA demand- or block-mode transfers. Very large transfers could cause the PCI Host Bridge target controller to violate the 10-s memory write maximum completion time limit set in the PCI Local Bus Specification, Revision 2.2. ElanTMSC520 Microcontroller Register Set Manual 11-81 GP DMA Controller Registers Master DMA Channel 6 Memory Address (GPDMA6MAR) Direct-Mapped I/O Address 00C8h 7 Bit Reset R/W 6 5 4 3 2 1 0 DMA6MAR[16-1] x x x x R/W! x x x x Register Description This register contains bits 16-1 of the memory address for Channel 6 during DMA operation. Bit Definitions Bit 7-0 Name DMA6MAR [16-1] Function Lower 16 Bits of DMA Channel 6 Memory Address This 8-bit field is used in two successive I/O accesses to read or write the channel's memory address bits 16-1 for 16-bit DMA transfers. Bits 8-1 of the channel's memory address can be read from or written to this bit field immediately after a write to the MSTDMACBP register (see page 11-93). Bits 16-9 of the channel's memory address can be read from or written to this bit field immediately after memory address bits 8-1 are read from or written to this bit field. Programming Notes To ensure that the lower byte of this register (GPDMA6MAR) is always accessed first, software should precede any access to this register with a write to the MSTDMACBP register (see page 11-93) to clear the master DMA byte pointer. The value in this register (GPDMA6MAR) is used with the values in the GPDMA6PG register (see page 11-71) and the GPDMAEXTPG6 register (see page 11-15) to generate DMA address bits 27-0. By default, this channel is set up for PC/AT compatibility (16-bit DMA transfers on the master DMA controller). For 16-bit transfers, this register (GPDMA6MAR) holds address bits 16-1 and address bit 0 is always 0 (i.e., the 16-bit transfers are word-aligned). Because of this, software must load this register with the desired memory address divided by 2 for 16-bit transfers. In enhanced mode, this channel can be programmed for 8-bit DMA transfers (see the descriptions for GPDMACTL register bits CH6_ALT_SIZE and ENH_MODE_ENB, on page 11-4). For 8-bit transfers, this register (GPDMA6MAR) holds address bits 15-0, and address bit 16 is controlled via the GPDMA6PG register (see page 11-71). 11-82 ElanTMSC520 Microcontroller Register Set Manual GP DMA Controller Registers Master DMA Channel 6 Transfer Count (GPDMA6TC) Direct-Mapped I/O Address 00CAh 7 Bit Reset R/W 6 5 4 3 2 1 0 DMA6TC[15-0] x x x x R/W! x x x x Register Description This register contains bits 15-0 of the transfer count for Channel 6 during DMA operation. Bit Definitions Bit 7-0 Name DMA6TC [15-0] Function DMA Channel 6 Transfer Count (16-Bit Register) This 8-bit field is used in two successive I/O accesses to read or write the channel's transfer count bits 15-0. Bits 7-0 of the channel's transfer count can be read from or written to this bit field immediately after a write to the MSTDMACBP register (see page 11-93). Bits 15-8 of the channel's transfer count can be read from or written to this bit field immediately after transfer count bits 7-0 are read from or written to this bit field. The actual number of transfers is one more than the programmed transfer count value. Programming Notes To ensure that the lower byte of this register (GPDMA6TC) is always accessed first, software should precede any access to this register with a write to the MSTDMACBP register (see page 11-93) to clear the master DMA byte pointer. By default, this channel is set up for PC/AT compatibility (16-bit DMA transfers on the master DMA controller). For 16-bit transfers, each transfer is two bytes, so a transfer count of FFFFh results in a transfer of 128 Kbytes. The value in this register (GPDMA6TC) can be used with the value in the GPDMAEXTTC6 register (see page 11-19) to allow counts of up to 16 M (16,777,216) transfers. In PCI bus 2.2-compliant designs, software must limit the length of GP bus DMA demand- or block-mode transfers. Very large transfers could cause the PCI Host Bridge target controller to violate the 10-s memory write maximum completion time limit set in the PCI Local Bus Specification, Revision 2.2. ElanTMSC520 Microcontroller Register Set Manual 11-83 GP DMA Controller Registers Master DMA Channel 7 Memory Address (GPDMA7MAR) Direct-Mapped I/O Address 00CCh 7 Bit Reset R/W 6 5 4 3 2 1 0 DMA7MAR[16-1] x x x x R/W! x x x x Register Description This register contains bits 16-1 of the memory address for Channel 7 during DMA operation. Bit Definitions Bit 7-0 Name DMA7MAR [16-1] Function Lower 16 Bits of DMA Channel 7 Memory Address This 8-bit field is used in two successive I/O accesses to read or write the channel's memory address bits 16-1 for 16-bit DMA transfers. Bits 8-1 of the channel's memory address can be read from or written to this bit field immediately after a write to the MSTDMACBP register (see page 11-93). Bits 16-9 of the channel's memory address can be read from or written to this bit field immediately after memory address bits 8-1 are read from or written to this bit field. Programming Notes To ensure that the lower byte of this register (GPDMA7MAR) is always accessed first, software should precede any access to this register with a write to the MSTDMACBP register (see page 11-93) to clear the master DMA byte pointer. The value in this register (GPDMA7MAR) is used with the values in the GPDMA7PG register (see page 11-72) and the GPDMAEXTPG7 register (see page 11-16) to generate DMA address bits 27-0. By default, this channel is set up for PC/AT compatibility (16-bit DMA transfers on the master DMA controller). For 16-bit transfers, this register (GPDMA7MAR) holds address bits 16-1 and address bit 0 is always 0 (i.e., the 16-bit transfers are word-aligned). Because of this, software must load this register with the desired memory address divided by 2 for 16-bit transfers. In enhanced mode, this channel can be programmed for 8-bit DMA transfers (see the descriptions for GPDMACTL register bits CH7_ALT_SIZE and ENH_MODE_ENB, on page 11-4). For 8-bit transfers, this register (GPDMA7MAR) holds address bits 15-0, and address bit 16 is controlled via the GPDMA7PG register (see page 11-72). 11-84 ElanTMSC520 Microcontroller Register Set Manual GP DMA Controller Registers Master DMA Channel 7 Transfer Count (GPDMA7TC) Direct-Mapped I/O Address 00CEh 7 Bit Reset R/W 6 5 4 3 2 1 0 DMA7TC[15-0] x x x x R/W! x x x x Register Description This register contains bits 15-0 of the transfer count for Channel 7 during DMA operation. Bit Definitions Bit 7-0 Name DMA7TC [15-0] Function DMA Channel 7 Transfer Count (16-Bit Register) This 8-bit field is used in two successive I/O accesses to read or write the channel's transfer count bits 15-0. Bits 7-0 of the channel's transfer count can be read from or written to this bit field immediately after a write to the MSTDMACBP register (see page 11-93). Bits 15-8 of the channel's transfer count can be read from or written to this bit field immediately after transfer count bits 7-0 are read from or written to this bit field. The actual number of transfers is one more than the programmed transfer count value. Programming Notes To ensure that the lower byte of this register (GPDMA7TC) is always accessed first, software should precede any access to this register with a write to the MSTDMACBP register (see page 11-93) to clear the master DMA byte pointer. By default, this channel is set up for PC/AT compatibility (16-bit DMA transfers on the master DMA controller). For 16-bit transfers, each transfer is two bytes, so a transfer count of FFFFh results in a transfer of 128 Kbytes. The value in this register (GPDMA7TC) can be used with the value in the GPDMAEXTTC7 register (see page 11-20) to allow counts of up to 16 M (16,777,216) transfers. In PCI bus 2.2-compliant designs, software must limit the length of GP bus DMA demand- or block-mode transfers. Very large transfers could cause the PCI Host Bridge target controller to violate the 10-s memory write maximum completion time limit set in the PCI Local Bus Specification, Revision 2.2. ElanTMSC520 Microcontroller Register Set Manual 11-85 GP DMA Controller Registers Master DMA Channel 4-7 Status (MSTDMASTA) Direct-Mapped I/O Address 00D0h 7 Bit Reset R/W 6 DMAR6 ? R 5 DMAR5 ? R 4 DMAR4 ? R 3 TC7 0 R! 2 TC6 0 R! 1 TC5 0 R! 0 TC4 0 R! DMAR7 ? R Register Description This register indicates the request status and terminal count status for Channels 4-7. Bit Definitions Bit 7 Name DMAR7 Function Channel 7 DMA Request 0 = Channel 7 DMA request not pending 1 = Channel 7 DMA request pending Channel 6 DMA Request 0 = Channel 6 DMA request not pending 1 = Channel 6 DMA request pending Channel 5 DMA Request 0 = Channel 5 DMA request not pending 1 = Channel 5 DMA request pending Channel 4 DMA Request 0 = Channel 4 DMA request not pending 1 = Channel 4 DMA request pending Channel 7 Terminal Count 0 = Channel 7 terminal count not detected 1 = Channel 7 terminal count detected Channel 6 Terminal Count 0 = Channel 6 terminal count not detected 1 = Channel 6 terminal count detected Channel 5 Terminal Count 0 = Channel 5 terminal count not detected 1 = Channel 5 terminal count detected Channel 4 Terminal Count 0 = Channel 4 terminal count not detected 1 = Channel 4 terminal count detected 6 DMAR6 5 DMAR5 4 DMAR4 3 TC7 2 TC6 1 TC5 0 TC4 Programming Notes Bits 3-0 of this register are reset when read. Any read from this register (MSTDMASTA) clears bits 3-0. 11-86 ElanTMSC520 Microcontroller Register Set Manual GP DMA Controller Registers Master DMA Channel 4-7 Control (MSTDMACTL) Direct-Mapped I/O Address 00D0h 7 Bit Reset R/W 6 DRQSEN 0 W 5 WRTSEL 0 W 4 PRITYPE 0 W 3 COMPTIM 0 W 2 DMA_DIS 0 W 1 Reserved 0 RSV 0 DAKSEN 0 W 0 Register Description This register provides the control function for Channels 4-7. Bit Definitions Bit 7 Name DAKSEN Function Internal dackx Sense In a discrete DMA controller, this bit controls the polarity of all dackx outputs from the slave DMA controller: 0 = Asserted Low 1 = Asserted High System logic external to the DMA controller expects the DMA controller to drive active Low dackx outputs. This bit must be written to `0b' for proper system operation. 6 DRQSEN Internal drqx Sense In a discrete DMA controller, this bit controls the polarity of all drqx inputs to the slave DMA controller: 0 = Asserted High 1 = Asserted Low System logic external to the DMA controller expects the DMA controller to respond to active High drqx inputs. This bit must be written to `0b' for proper system operation. 5 WRTSEL Write Selection Control 0 = Late write selection 1 = Extended (early) write selection. Write command signals (GPIOWR and GPMEMWR) are asserted one clock early. Enabling this feature results in timing changes on the GP bus that can violate the ISA specification. This bit has no effect when the COMPTIM bit is 1. 4 PRITYPE Priority Type 0 = Fixed priority 1 = Rotating priority Compressed Timing 0 = Normal timing. 1 = Compressed timing. Read command signals (GPIORD and GPMEMRD) have a one clock pulse width. Enabling this feature results in timing changes on the GP bus that can violate the ISA specification. 3 COMPTIM 2 DMA_DIS Disable DMA Controller 0 = DMA requests are enabled. 1 = DMA requests are ignored but DMA registers are available to the CPU. The DMA controller should be disabled prior to programming it in order to prevent unintended transfers from occurring during the DMA controller programming operation. Care should also be taken to ensure that the DMA controller is idle before disabling it. If the DMA controller is performing a transfer when software disables it, abnormal system operation can occur. ElanTMSC520 Microcontroller Register Set Manual 11-87 GP DMA Controller Registers Bit 1-0 Name Reserved Function Reserved This bit field should be written to 0 for normal system operation. Programming Notes 11-88 ElanTMSC520 Microcontroller Register Set Manual GP DMA Controller Registers Master Software DRQ(n) Request (MSTDMASWREQ) Direct-Mapped I/O Address 00D2h 7 Bit Reset R/W 6 5 Reserved 4 3 2 REQDMA 1 0 REQSEL[1-0] x W x 0 0 0 RSV 0 0 x W Register Description This register is used to initiate a software DMA request for one of Channels 4-7. Bit Definitions Bit 7-3 2 Name Reserved REQDMA Function Reserved This bit field should be written to 0 for normal system operation. Software DMA Request 0 = Clear the request bit for the channel selected by the REQSEL bit field. 1 = Set the request bit for the channel selected by the REQSEL bit field. The request bit is cleared internally after the corresponding channel has reached the end of its transfer count. 1-0 REQSEL[1-0] DMA Channel Select This bit field selects DMA channel that is to latch the REQDMA bit internally to assert or deassert a DMA request via software: 00 = Select Channel 4 for internal DMA request per the REQDMA bit. 01 = Select Channel 5 for internal DMA request per the REQDMA bit. 10 = Select Channel 6 for internal DMA request per the REQDMA bit. 11 = Select Channel 7 for internal DMA request per the REQDMA bit. Programming Notes ElanTMSC520 Microcontroller Register Set Manual 11-89 GP DMA Controller Registers Master DMA Channel 4-7 Mask (MSTDMAMSK) Direct-Mapped I/O Address 00D4h 7 Bit Reset R/W 6 5 Reserved 4 3 2 CHMASK 1 0 MSKSEL[1-0] x W x 0 0 0 RSV 0 0 x W Register Description This register provides a mask or unmask capability for the DMA request signal to each of Channels 4-7. Bit Definitions Bit 7-3 2 Name Reserved CHMASK Function Reserved This bit field should be written to 0 for normal system operation. DMA Channel Mask 0 = Clear the mask bit for the channel selected by the MSKSEL bit field. 1 = Set the mask bit for the channel selected by the MSKSEL bit field. If the AINIT bit is 0 in the MSTDMAMODE register (see page 11-91), the mask bit is set internally when the corresponding channel reaches the end of its transfer count. If the AINIT bit is 1, the mask bit remains clear when the transfer ends. 1-0 MSKSEL[1-0] DMA Channel Mask Select This bit field selects the DMA channel that is to latch the CHMASK bit internally to mask or unmask the DMA request signal into the specified DMA channel: 00 = Mask or unmask DMA Channel 4 per the CHMASK bit. 01 = Mask or unmask DMA Channel 5 per the CHMASK bit. 10 = Mask or unmask DMA Channel 6 per the CHMASK bit. 11 = Mask or unmask DMA Channel 7 per the CHMASK bit. Programming Notes The same DMA channel masks can be controlled via DMA registers MSTDMAMSK, MSTDMAMSKRST (see page 11-96), and MSTDMAGENMSK (see page 11-97). Before masking an active DMA channel, software must ensure that the DMA request is deasserted. Masking an active channel while it is being granted might cause the system to hang. 11-90 ElanTMSC520 Microcontroller Register Set Manual GP DMA Controller Registers Master DMA Channel 4-7 Mode (MSTDMAMODE) Direct-Mapped I/O Address 00D6h 7 Bit Reset R/W 6 5 ADDDEC x W 4 AINIT x W 3 2 1 0 TRNMOD[1-0] x W x OPSEL[1-0] x W x MODSEL[1-0] x W x Register Description This register indicates the transfer mode for Channels 4-7. Bit Definitions Bit 7-6 Name TRNMOD[1-0] Function Transfer Mode This bit field selects the transfer mode for the channel selected by the MODSEL bit field. 00 = Demand transfer mode 01 = Single transfer mode 10 = Block transfer mode 11 = Cascade mode. (Only Channel 4 should be programmed for cascade mode. All other channels should be programmed for one of the other modes). 5 ADDDEC Address Decrement This bit field selects increment or decrement counting for the channel selected by the MODSEL bit field. 0 = Increment the DMA memory address after each transfer. 1 = Decrement the DMA memory address after each transfer. Automatic Initialization Control This bit field enables automatic initialization for the channel selected by the MODSEL bit field. 0 = Automatic initialization is disabled. 1 = Automatic initialization is enabled. Automatic initialization causes the channel's base address and transfer count registers to be restored to the values they contained prior to the DMA transfer when the transfer count ends. The channel is then ready to perform another DMA transfer without processor intervention as soon as the next DMA request is detected. Automatic initialization must be disabled when buffer chaining mode is used; otherwise unexpected results may occur. 4 AINIT 3-2 OPSEL[1-0] Operation Select This bit field selects the DMA operation for the channel selected by the MODSEL bit field. 00 = Verify mode. The DMA controller acts normally except that no I/O or memory commands are generated, and no data is transferred. 01 = Write transfer. Data is transferred from a DMA-capable I/O or memory-mapped device into system memory. 10 = Read transfer. Data is transferred from system memory to a DMA-capable I/O or memory-mapped device. 11 = Reserved. ElanTMSC520 Microcontroller Register Set Manual 11-91 GP DMA Controller Registers Bit 1-0 Name MODSEL[1-0] Function DMA Channel Select This bit field selects the channel that is to internally latch the other bits written to this register: 00 = Select Channel 4 01 = Select Channel 5 10 = Select Channel 6 11 = Select Channel 7 Programming Notes 11-92 ElanTMSC520 Microcontroller Register Set Manual GP DMA Controller Registers Master DMA Clear Byte Pointer (MSTDMACBP) Direct-Mapped I/O Address 00D8h 7 Bit Reset R/W x 6 5 4 3 2 1 0 MASTR_CBP[7-0] x x x W! x x x x Register Description This register channel provides a mechanism to adjust the byte pointer to the low byte of the memory address and transfer count registers for Channels 4-7. Bit Definitions Bit 7-0 Name MASTR_CBP [7-0] Function Master DMA Clear Byte Pointer The DMA controller's 16-bit memory address and terminal count registers are accessed by writing or reading consecutive 8-bit values to the same direct-mapped I/O address. A single byte pointer is used across the master DMA controller to determine which byte is accessed if any of these 16-bit registers is read or written. Any access to one of these registers toggles the byte pointer between the low and high bytes. A write of any data to this bit field (MASTR_CBP) clears the byte pointer so that the next memory address or transfer count register access is to the low byte. Programming Notes ElanTMSC520 Microcontroller Register Set Manual 11-93 GP DMA Controller Registers Master DMA Controller Reset (MSTDMARST) Direct-Mapped I/O Address 00DAh 7 Bit Reset R/W 6 5 4 3 2 1 0 MASTR_RST[7-0] 0 0 0 0 W! 0 0 0 0 Register Description This register provides a reset mechanism for Channels 4-7. Bit Definitions Bit 7-0 Name MASTR_RST [7-0] Function Master DMA Controller Reset A write of any data to this address resets the DMA controller to the same state as a system reset. Programming Notes 11-94 ElanTMSC520 Microcontroller Register Set Manual GP DMA Controller Registers Master DMA Controller Temporary (MSTDMATMP) Direct-Mapped I/O Address 00DAh 7 Bit Reset R/W 6 5 4 3 2 1 0 MASTR_TMP[7-0] 0 0 0 0 R 0 0 0 0 Register Description This register has no real use in the ELANSC520 microcontroller. It is included for compatibility only. Bit Definitions Bit 7-0 Name MASTR_TMP [7-0] Function Master DMA Controller Temporary Register In a discrete DMA controller, this bit field is used as a temporary storage buffer when doing memory-to-memory DMA. Memory-to-memory DMA transfers are not supported in the ELANSC520 microcontroller, so this register is included for compatibility reasons only. Programming Notes ElanTMSC520 Microcontroller Register Set Manual 11-95 GP DMA Controller Registers Master DMA Mask Reset (MSTDMAMSKRST) Direct-Mapped I/O Address 00DCh 7 Bit Reset R/W 6 5 4 3 2 1 0 MASTR_MSK_RST[7-0] x x x x W! x x x x Register Description This register provides a mechanism to reset the MSTDMAGENMSK register (see page 11-97). Bit Definitions Bit 7-0 Name MASTR_MSK_ RST[7-0] Function Master DMA Reset Mask Writing any data to this I/O address resets the MSTDMAGENMSK register (see page 11-97), thereby activating the four slave DMA channels. Programming Notes The same DMA channel masks can be controlled via DMA registers MSTDMAMSK (see page 11-90), MSTDMAMSKRST, and MSTDMAGENMSK (see page 11-97). Before masking an active DMA channel, software must ensure that the DMA request is deasserted. Masking an active channel while it is being granted might cause the system to hang. 11-96 ElanTMSC520 Microcontroller Register Set Manual GP DMA Controller Registers Master DMA General Mask (MSTDMAGENMSK) Direct-Mapped I/O Address 00DEh 7 Bit Reset R/W 6 Reserved 5 4 3 CH7_DIS 2 CH6_DIS 1 W 1 CH5_DIS 1 W 0 CH4_DIS 1 W 0 0 RSV 0 0 1 W Register Description This register provides a mechanism to mask or unmask the DMA request signal to each of Channels 4-7. Bit Definitions Bit 7-4 3 Name Reserved CH7_DIS Function Reserved This bit field should be written to 0 for normal system operation. DMA Channel 7 Mask 0 = Enable DMA Channel 7 for servicing DMA requests. 1 = Disable DMA Channel 7 from servicing DMA requests. DMA Channel 6 Mask 0 = Enable DMA Channel 6 for servicing DMA requests. 1 = Disable DMA Channel 6 from servicing DMA requests. DMA Channel 5 Mask 0 = Enable DMA Channel 5 for servicing DMA requests. 1 = Disable DMA Channel 5 from servicing DMA requests. DMA Channel 4 Mask 0 = Enable DMA Channel 4 for servicing DMA requests. 1 = Disable DMA Channel 4 from servicing DMA requests. 2 CH6_DIS 1 CH5_DIS 0 CH4_DIS Programming Notes The same DMA channel masks can be controlled via DMA registers MSTDMAMSK (see page 11-90), MSTDMAMSKRST (see page 11-96), and MSTDMAGENMSK. Before masking an active DMA channel, software must ensure that the DMA request is deasserted. Masking an active channel while it is being granted might cause the system to hang. ElanTMSC520 Microcontroller Register Set Manual 11-97 GP DMA Controller Registers 11-98 ElanTMSC520 Microcontroller Register Set Manual CHAPTER 12 12.1 PROGRAMMABLE INTERRUPT CONTROLLER REGISTERS OVERVIEW This chapter describes the programmable interrupt controller (PIC) registers of the ELANSC520 microcontroller. The ELANSC520 microcontroller's programmable interrupt controller (PIC) consists of three industry-standard controllers, integrated with a highly programmable interrupt router. The PIC register set includes two groups of registers: s 39 memory-mapped configuration region (MMCR) registers are used to configure and control PIC functions specific to the ELANSC520 microcontroller. s 28 direct-mapped I/O registers are used for industry-standard PIC configuration, control, and status functions. See the ElanTMSC520 Microcontroller User's Manual, order #22004, for details about the interrupt controller. Table 12-1 and Table 12-2 on page 12-2 list each type of PIC register in offset order, with the corresponding description's page number. 12.2 Table 12-1 REGISTERS Programmable Interrupt Controller MMCR Registers Register Name Interrupt Control Master PIC Interrupt Mode Slave 1 PIC Interrupt Mode Slave 2 PIC Interrupt Mode Software Interrupt 16-1 Control Software Interrupt 22-17/NMI Control Interrupt Pin Polarity PCI Host Bridge Interrupt Mapping ECC Interrupt Mapping GP Timer 0 Interrupt Mapping GP Timer 1 Interrupt Mapping GP Timer 2 Interrupt Mapping PIT 0 Interrupt Mapping PIT 1 Interrupt Mapping PIT 2 Interrupt Mapping UART 1 Interrupt Mapping UART 2 Interrupt Mapping PCI Interrupt A Mapping Mnemonic PICICR MPICMODE SL1PICMODE SL2PICMODE SWINT16_1 SWINT22_17 INTPINPOL PCIHOSTMAP ECCMAP GPTMR0MAP GPTMR1MAP GPTMR2MAP PIT0MAP PIT1MAP PIT2MAP UART1MAP UART2MAP PCIINTAMAP MMCR Offset Page Number D00h D02h D03h D04h D08h D0Ah D10h D14h D18h D1Ah D1Bh D1Ch D20h D21h D22h D28h D29h D30h page 12-4 page 12-6 page 12-8 page 12-9 page 12-10 page 12-13 page 12-15 page 12-17 page 12-19 page 12-21 page 12-21 page 12-21 page 12-21 page 12-21 page 12-21 page 12-21 page 12-21 page 12-21 ElanTMSC520 Microcontroller Register Set Manual 12-1 Programmable Interrupt Controller Registers Table 12-1 Programmable Interrupt Controller MMCR Registers (Continued) Register Name PCI Interrupt B Mapping PCI Interrupt C Mapping PCI Interrupt D Mapping DMA Buffer Chaining Interrupt Mapping SSI Interrupt Mapping Watchdog Timer Interrupt Mapping RTC Interrupt Mapping Write-Protect Violation Interrupt Mapping Floating Point Error Interrupt Mapping GPIRQ0 Interrupt Mapping GPIRQ1 Interrupt Mapping GPIRQ2 Interrupt Mapping GPIRQ3 Interrupt Mapping GPIRQ4 Interrupt Mapping GPIRQ5 Interrupt Mapping GPIRQ6 Interrupt Mapping GPIRQ7 Interrupt Mapping GPIRQ8 Interrupt Mapping GPIRQ9 Interrupt Mapping GPIRQ10 Interrupt Mapping Table 12-2 Mnemonic PCIINTBMAP PCIINTCMAP PCIINTDMAP DMABCINTMAP SSIMAP WDTMAP RTCMAP WPVMAP FERRMAP GP0IMAP GP1IMAP GP2IMAP GP3IMAP GP4IMAP GP5IMAP GP6IMAP GP7IMAP GP8IMAP GP9IMAP GP10IMAP MMCR Offset Page Number D31h D32h D33h D40h D41h D42h D43h D44h D45h D46h D50h D51h D52h D53h D54h D55h D56h D57h D58h D59h D5Ah page 12-21 page 12-21 page 12-21 page 12-21 page 12-21 page 12-21 page 12-21 page 12-21 page 12-21 page 12-21 page 12-21 page 12-21 page 12-21 page 12-21 page 12-21 page 12-21 page 12-21 page 12-21 page 12-21 page 12-21 page 12-21 AMDebugTM Technology RX/TX Interrupt Mapping ICEMAP Programmable Interrupt Controller Direct-Mapped Registers Register Name Master PIC Interrupt Request Master PIC In-Service Master PIC Initialization Control Word 1 Master PIC Operation Control Word 2 Master PIC Operation Control Word 3 Master PIC Initialization Control Word 2 Master PIC Initialization Control Word 3 Master PIC Initialization Control Word 4 Master PIC Interrupt Mask Slave 2 PIC Interrupt Request Slave 2 PIC In-Service Slave 2 PIC Initialization Control Word 1 Slave 2 PIC Operation Control Word 2 Slave 2 PIC Operation Control Word 3 Slave 2 PIC Initialization Control Word 2 Slave 2 PIC Initialization Control Word 3 Slave 2 PIC Initialization Control Word 4 Mnemonic MPICIR MPICISR MPICICW1 MPICOCW2 MPICOCW3 MPICICW2 MPICICW3 MPICICW4 MPICINTMSK S2PICIR S2PICISR S2PICICW1 S2PICOCW2 S2PICOCW3 S2PICICW2 S2PICICW3 S2PICICW4 I/O Address Page Number 0020h 0020h 0020h 0020h 0020h 0021h 0021h 0021h 0021h 0024h 0024h 0024h 0024h 0024h 0025h 0025h 0025h page 12-24 page 12-25 page 12-26 page 12-28 page 12-30 page 12-32 page 12-33 page 12-35 page 12-36 page 12-37 page 12-38 page 12-39 page 12-41 page 12-43 page 12-45 page 12-46 page 12-47 12-2 ElanTMSC520 Microcontroller Register Set Manual Programmable Interrupt Controller Registers Table 12-2 Programmable Interrupt Controller Direct-Mapped Registers (Continued) Register Name Slave 2 PIC Interrupt Mask Slave 1 PIC Interrupt Request Slave 1 PIC In-Service Slave 1 PIC Initialization Control Word 1 Slave 1 PIC Operation Control Word 2 Slave 1 PIC Operation Control Word 3 Slave 1 PIC Initialization Control Word 2 Slave 1 PIC Initialization Control Word 3 Slave 1 PIC Initialization Control Word 4 Slave 1 PIC Interrupt Mask FPU Error Interrupt Clear Mnemonic S2PICINTMSK S1PICIR S1PICISR S1PICICW1 S1PICOCW2 S1PICOCW3 S1PICICW2 S1PICICW3 S1PICICW4 S1PICINTMSK FPUERRCLR I/O Address Page Number 0025h 00A0h 00A0h 00A0h 00A0h 00A0h 00A1h 00A1h 00A1h 00A1h 00F0h page 12-48 page 12-49 page 12-50 page 12-51 page 12-53 page 12-55 page 12-57 page 12-58 page 12-59 page 12-60 page 12-61 ElanTMSC520 Microcontroller Register Set Manual 12-3 Programmable Interrupt Controller Registers Interrupt Control (PICICR) Memory-Mapped MMCR Offset D00h 7 Bit Reset R/W 6 NMI_ENB 0 R/W 5 4 Reserved 3 2 S2_GINT_ MODE 1 S1_GINT_ MODE 1 R/W 0 M_GINT_ MODE 1 R/W NMI_DONE 0 R/W! 0 0 RSV 0 1 R/W Register Description This register controls the global interrupt mode for the Master, Slave 1 and Slave 2 programmable interrupt controllers, slave controller bypass, and the global nonmaskable interrupt (NMI) mask bit. Bit Definitions Bit 7 Name NMI_DONE Function NMI Routine Done 0 = After this bit is set, it is cleared automatically by interrupt controller logic. 1 = Software sets this bit to indicate that the NMI routine is completed. Subsequent NMI events are blocked by the interrupt controller until the NMI_DONE bit is set by software, but if an NMI source is active at the time when the handler for another NMI sets this bit, then the interrupt controller generates an NMI for the second source shortly after returning from the first handler. 6 NMI_ENB Master NMI Enable This bit is a read/write version of the NMI enable bit that typically resides at direct-mapped Port 0070h, bit 7, on a PC/AT-compatible system. It has been moved here to facilitate internal design integration with the ELANSC520 microcontroller. 0 = NMI is gated off from reaching the CPU core. 1 = NMI propagates to the CPU core. If any NMI interrupt sources are active when this bit is set, an NMI is generated immediately. The NMI_ENB bit is cleared by a CPU soft reset event. This allows software to initialize the stack pointer before setting the NMI_ENB bit again after a soft reset. See Table 3-3 on page 3-6 for a summary of ELANSC520 microcontroller reset sources. 5-3 2 Reserved S2_GINT_ MODE Reserved This bit field should be written to 0 for normal system operation. Slave 2 PIC Global Interrupt Mode Enable This bit provides a global or individual channel interrupt mode for the Slave 2 PIC. 0 = Slave 2 PIC global interrupt mode disabled. 1 = Slave 2 PIC global interrupt mode enabled. If the S2_GINT_MODE bit is set, bit LTIM of the S2PICICW1 register (see page 12-39) determines the interrupt mode for the Slave 2 PIC channels. If the S2_GINT_MODE bit and the LTIM bit are set, all the Slave 2 PIC interrupt channels recognize level-sensitive interrupt requests. If the S2_GINT_MODE bit is set and the LTIM bit is cleared, all the Slave 2 PIC interrupt channels recognize edge-sensitive interrupt requests. If the S2_GINT_MODE bit is cleared, the Slave 2 LTIM bit has no meaning, and the Slave 2 PIC channels can be programmed individually via the SL2PICMODE register (see page 12-9) to select either edge- or level-sensitive interrupt recognition. 12-4 ElanTMSC520 Microcontroller Register Set Manual Programmable Interrupt Controller Registers Bit 1 Name S1_GINT_ MODE Function Slave 1 PIC Global Interrupt Mode Enable This bit provides a global or individual channel interrupt mode for the Slave 1 PIC. 0 = Slave 1 PIC global interrupt mode disabled. 1 = Slave 1 PIC global interrupt mode enabled. If the S1_GINT_MODE bit is set, bit LTIM of the S1PICICW1 register (see page 12-51) determines the interrupt mode for the Slave 1 PIC channels. If the S1_GINT_MODE bit and the LTIM bit are set, all the Slave 1 PIC interrupt channels recognize level-sensitive interrupt requests. If the S1_GINT_MODE bit is set and the LTIM bit is cleared, all the Slave 1 PIC interrupt channels recognize edge-sensitive interrupt requests. If the S1_GINT_MODE bit is cleared, the Slave 1 LTIM bit has no meaning, and the Slave 1 PIC channels can be programmed individually via the SL1PICMODE register (see page 12-8) to select either edge- or level-sensitive interrupt recognition. 0 M_GINT_ MODE Master PIC Global Interrupt Mode Enable This bit provides a global or individual channel interrupt mode for the Master PIC. 0 = Master PIC global interrupt mode disabled. 1 = Master PIC global interrupt mode enabled. If the M_GINT_MODE bit is set, bit LTIM of the MPICICW1 register (see page 12-26) determines the interrupt mode for the Master PIC channels. If the M_GINT_MODE bit and the LTIM bit are set, all the Master PIC interrupt channels recognize level-sensitive interrupt requests. If the M_GINT_MODE bit is set and the LTIM bit is cleared, all the Master PIC interrupt channels recognize edge-sensitive interrupt requests. If the M_GINT_MODE bit is cleared, the Master LTIM bit has no meaning, and the Master PIC channels can be programmed individually via the MPICMODE register (see page 12-6) to select either edge- or level-sensitive interrupt recognition. Programming Notes For PC/AT compatibility, bits M_GINT_MODE and S1_GINT_MODE in this register (PICICR) should be set, and bit S2 should be set and bit S5 cleared in the MPICICW3 register (see page 12-34). In this configuration, the Slave 2 controller is bypassed and any interrupt sources mapped to the Slave 2 controller have no effect; also, interrupt sources can be mapped directly to Master PIC interrupt channel 5 by mapping them to priority P13. ElanTMSC520 Microcontroller Register Set Manual 12-5 Programmable Interrupt Controller Registers Master PIC Interrupt Mode (MPICMODE) Memory-Mapped MMCR Offset D02h 7 Bit Reset R/W 6 CH6_INT_ MODE 0 R/W 5 CH5_INT_ MODE 0 R/W 4 CH4_INT_ MODE 0 R/W 3 CH3_INT_ MODE 0 R/W 2 CH2_INT_ MODE 0 R/W 1 CH1_INT_ MODE 0 R/W 0 CH0_INT_ MODE 0 R/W CH7_INT_ MODE 0 R/W Register Description This register controls the individual Master PIC channel interrupt mode. Bit Definitions Bit 7 Name CH7_INT_ MODE Function Master PIC Channel 7 Interrupt Mode 0 = Edge-sensitive interrupt request detection 1 = Level-sensitive interrupt request detection Master PIC Channel 6 Interrupt Mode 0 = Edge-sensitive interrupt request detection 1 = Level-sensitive interrupt request detection Master PIC Channel 5 Interrupt Mode 0 = Edge-sensitive interrupt request detection 1 = Level-sensitive interrupt request detection If the SNGL bit in the MPICICW1 register is set (see page 12-26), and the M_GINT_MODE bit of the PICICR register is cleared (see page 12-5), setting the CH5_INT_MODE bit causes interrupts to be recognized as level-sensitive on channel 5. Clearing the CH5_INT_MODE bit under the same condition causes channel 5 interrupts to be recognized as edge-sensitive. However, if both the SNGL bit and the M_GINT_MODE bit are cleared, the CH5_INT_MODE bit value has no meaning because the channel is used for cascading with the Slave 2 controller. 6 CH6_INT_ MODE 5 CH5_INT_ MODE 4 CH4_INT_ MODE Master PIC Channel 4 Interrupt Mode 0 = Edge-sensitive interrupt request detection 1 = Level-sensitive interrupt request detection Master PIC Channel 3 Interrupt Mode 0 = Edge-sensitive interrupt request detection 1 = Level-sensitive interrupt request detection Master PIC Channel 2 Interrupt Mode 0 = Edge-sensitive interrupt request detection 1 = Level-sensitive interrupt request detection If the SNGL bit in the MPICICW1 register is set (see page 12-26), and the M_GINT_MODE bit of the PICICR register is cleared (see page 12-5), setting the CH2_INT_MODE bit causes interrupts to be recognized as level-sensitive on channel 2. Clearing the CH2_INT_MODE bit under the same condition causes channel 2 interrupts to be recognized as edge-sensitive. However, if both the SNGL bit and the M_GINT_MODE bit are cleared, the CH2_INT_MODE bit value has no meaning because the channel is used for cascading with the Slave 1 controller. 3 CH3_INT_ MODE 2 CH2_INT_ MODE 1 CH1_INT_ MODE Master PIC Channel 1 Interrupt Mode 0 = Edge-sensitive interrupt request detection 1 = Level-sensitive interrupt request detection 12-6 ElanTMSC520 Microcontroller Register Set Manual Programmable Interrupt Controller Registers Bit 0 Name CH0_INT_ MODE Function Master PIC Channel 0 Interrupt Mode 0 = Edge-sensitive interrupt request detection 1 = Level-sensitive interrupt request detection Programming Notes There is a global overriding bit, M_GINT_MODE in the PICICR register (see page 12-5). When set, the M_GINT_MODE bit causes this register (MPICMODE) to have no effect on the interrupt mode programmed for each channel. If the M_GINT_MODE bit is set, the overriding global interrupt mode for the Master PIC channels is determined by the LTIM bit in the MPICICW1 register (see page 12-26). If the M_GINT_MODE bit is cleared, the LTIM bit has no meaning, and the MPICMODE register bits take effect for determining each Master PIC channel's interrupt mode. ElanTMSC520 Microcontroller Register Set Manual 12-7 Programmable Interrupt Controller Registers Slave 1 PIC Interrupt Mode (SL1PICMODE) Memory-Mapped MMCR Offset D03h 7 Bit Reset R/W 6 CH6_INT_ MODE 0 R/W 5 CH5_INT_ MODE 0 R/W 4 CH4_INT_ MODE 0 R/W 3 CH3_INT_ MODE 0 R/W 2 CH2_INT_ MODE 0 R/W 1 CH1_INT_ MODE 0 R/W 0 CH0_INT_ MODE 0 R/W CH7_INT_ MODE 0 R/W Register Description This register controls the individual Slave 1 PIC channel interrupt mode. Bit Definitions Bit 7 Name CH7_INT_ MODE Function Slave 1 PIC Channel 7 Interrupt Mode 0 = Edge-sensitive interrupt request detection 1 = Level-sensitive interrupt request detection Slave 1 PIC Channel 6 Interrupt Mode 0 = Edge-sensitive interrupt request detection 1 = Level-sensitive interrupt request detection Slave 1 PIC Channel 5 Interrupt Mode 0 = Edge-sensitive interrupt request detection 1 = Level-sensitive interrupt request detection Slave 1 PIC Channel 4 Interrupt Mode 0 = Edge-sensitive interrupt request detection 1 = Level-sensitive interrupt request detection Slave 1 PIC Channel 3 Interrupt Mode 0 = Edge-sensitive interrupt request detection 1 = Level-sensitive interrupt request detection Slave 1 PIC Channel 2 Interrupt Mode 0 = Edge-sensitive interrupt request detection 1 = Level-sensitive interrupt request detection Slave 1 PIC Channel 1 Interrupt Mode 0 = Edge-sensitive interrupt request detection 1 = Level-sensitive interrupt request detection Slave 1 PIC Channel 0 Interrupt Mode 0 = Edge-sensitive interrupt request detection 1 = Level-sensitive interrupt request detection 6 CH6_INT_ MODE 5 CH5_INT_ MODE 4 CH4_INT_ MODE 3 CH3_INT_ MODE 2 CH2_INT_ MODE 1 CH1_INT_ MODE 0 CH0_INT_ MODE Programming Notes There is a global overriding bit, S1_GINT_MODE in the PICICR register (see page 12-5). When set, the S1_GINT_MODE bit causes this register (SL1PICMODE) to have no effect on the interrupt mode programmed for each channel. If the S1_GINT_MODE bit is set, the overriding global interrupt mode for the Slave 1 PIC channels is determined by the LTIM bit in the S1PICICW1 register (see page 12-51). If the S1_GINT_MODE bit is cleared, the LTIM bit has no meaning, and the SL1PICMODE register bits take effect for determining each Slave 1 PIC channel's interrupt mode. 12-8 ElanTMSC520 Microcontroller Register Set Manual Programmable Interrupt Controller Registers Slave 2 PIC Interrupt Mode (SL2PICMODE) Memory-Mapped MMCR Offset D04h 7 Bit Reset R/W 6 CH6_INT_ MODE 0 R/W 5 CH5_INT_ MODE 0 R/W 4 CH4_INT_ MODE 0 R/W 3 CH3_INT_ MODE 0 R/W 2 CH2_INT_ MODE 0 R/W 1 CH1_INT_ MODE 0 R/W 0 CH0_INT_ MODE 0 R/W CH7_INT_ MODE 0 R/W Register Description This register controls the individual Slave 2 PIC channel interrupt mode. Bit Definitions Bit 7 Name CH7_INT_ MODE Function Slave 2 PIC Channel 7 Interrupt Mode 0 = Edge-sensitive interrupt request detection 1 = Level-sensitive interrupt request detection Slave 2 PIC Channel 6 Interrupt Mode 0 = Edge-sensitive interrupt request detection 1 = Level-sensitive interrupt request detection Slave 2 PIC Channel 5 Interrupt Mode 0 = Edge-sensitive interrupt request detection 1 = Level-sensitive interrupt request detection Slave 2 PIC Channel 4 Interrupt Mode 0 = Edge-sensitive interrupt request detection 1 = Level-sensitive interrupt request detection Slave 2 PIC Channel 3 Interrupt Mode 0 = Edge-sensitive interrupt request detection 1 = Level-sensitive interrupt request detection Slave 2 PIC Channel 2 Interrupt Mode 0 = Edge-sensitive interrupt request detection 1 = Level-sensitive interrupt request detection Slave 2 PIC Channel 1 Interrupt Mode 0 = Edge-sensitive interrupt request detection 1 = Level-sensitive interrupt request detection Slave 2 PIC Channel 0 Interrupt Mode 0 = Edge-sensitive interrupt request detection 1 = Level-sensitive interrupt request detection 6 CH6_INT_ MODE 5 CH5_INT_ MODE 4 CH4_INT_ MODE 3 CH3_INT_ MODE 2 CH2_INT_ MODE 1 CH1_INT_ MODE 0 CH0_INT_ MODE Programming Notes There is a global overriding bit, S2_GINT_MODE in the PICICR register (see page 12-5). When set, the S2_GINT_MODE bit causes this register (SL2PICMODE) to have no effect on the interrupt mode programmed for each channel. If the S2_GINT_MODE bit is set, the overriding global interrupt mode for the Slave 2 PIC channels is determined by the LTIM bit in the S2PICICW1 register (see page 12-51). If the S2_GINT_MODE bit is cleared, the LTIM bit has no meaning, and the SL2PICMODE register bits take effect for determining each Slave 2 PIC channel's interrupt mode. ElanTMSC520 Microcontroller Register Set Manual 12-9 Programmable Interrupt Controller Registers Software Interrupt 16-1 Control (SWINT16_1) Memory-Mapped MMCR Offset D08h 15 Bit Reset R/W 14 SW_P15_ TRIG 0 R/W 6 SW_P7_ TRIG 0 R/W 13 SW_P14_ TRIG 0 R/W 5 SW_P6_ TRIG 0 R/W 12 SW_P13_ TRIG 0 R/W 4 SW_P5_ TRIG 0 R/W 11 SW_P12_ TRIG 0 R/W 3 SW_P4_ TRIG 0 R/W 10 SW_P11_ TRIG 0 R/W 2 SW_P3_ TRIG 0 R/W 9 SW_P10_ TRIG 0 R/W 1 SW_P2_ TRIG 0 R/W 8 SW_P9_ TRIG 0 R/W 0 SW_P1_ TRIG 0 R/W SW_P16_ TRIG 0 R/W 7 Bit Reset R/W SW_P8_ TRIG 0 R/W Register Description This register allows software to generate interrupt priority levels P1-P16 to the CPU. Bit Definitions Bit 15 Name SW_P16_TRIG Function Directly Trigger Priority Level P16 Setting this bit directly asserts a maskable interrupt of priority level P16. Clearing this bit removes this direct interrupt assertion. 0 = Do not assert the interrupt. 1 = Assert the interrupt. Directly Trigger Priority Level P15 Setting this bit directly asserts a maskable interrupt of priority level P15. Clearing this bit removes this direct interrupt assertion. 0 = Do not assert the interrupt. 1 = Assert the interrupt. Directly Trigger Priority Level P14 Setting this bit directly asserts a maskable interrupt of priority level P14. Clearing this bit removes this direct interrupt assertion. 0 = Do not assert the interrupt. 1 = Assert the interrupt. Directly Trigger Priority Level P13 Setting this bit directly asserts a maskable interrupt of priority level P13. Clearing this bit removes this direct interrupt assertion. 0 = Do not assert the interrupt. 1 = Assert the interrupt. Directly Trigger Priority Level P12 Setting this bit directly asserts a maskable interrupt of priority level P12. Clearing this bit removes this direct interrupt assertion. 0 = Do not assert the interrupt. 1 = Assert the interrupt. 14 SW_P15_TRIG 13 SW_P14_TRIG 12 SW_P13_TRIG 11 SW_P12_TRIG 12-10 ElanTMSC520 Microcontroller Register Set Manual Programmable Interrupt Controller Registers Bit 10 Name SW_P11_TRIG Function Directly Trigger Priority Level P11 Setting this bit directly asserts a maskable interrupt of priority level P11. Clearing this bit removes this direct interrupt assertion. 0 = Do not assert the interrupt. 1 = Assert the interrupt. 9 SW_P10_TRIG Directly Trigger Priority Level P10 Setting this bit directly asserts a maskable interrupt of priority level P10. Clearing this bit removes this direct interrupt assertion. 0 = Do not assert the interrupt. 1 = Assert the interrupt. 8 SW_P9_TRIG Directly Trigger Priority Level P9 Setting this bit directly asserts a maskable interrupt of priority level P9. Clearing this bit removes this direct interrupt assertion. 0 = Do not assert the interrupt. 1 = Assert the interrupt. 7 SW_P8_TRIG Directly Trigger Priority Level P8 Setting this bit directly asserts a maskable interrupt of priority level P8. Clearing this bit removes this direct interrupt assertion. 0 = Do not assert the interrupt. 1 = Assert the interrupt. 6 SW_P7_TRIG Directly Trigger Priority Level P7 Setting this bit directly asserts a maskable interrupt of priority level P7. Clearing this bit removes this direct interrupt assertion. 0 = Do not assert the interrupt. 1 = Assert the interrupt. 5 SW_P6_TRIG Directly Trigger Priority Level P6 Setting this bit directly asserts a maskable interrupt of priority level P6. Clearing this bit removes this direct interrupt assertion. 0 = Do not assert the interrupt. 1 = Assert the interrupt. 4 SW_P5_TRIG Directly Trigger Priority Level P5 Setting this bit directly asserts a maskable interrupt of priority level P5. Clearing this bit removes this direct interrupt assertion. 0 = Do not assert the interrupt. 1 = Assert the interrupt. 3 SW_P4_TRIG Directly Trigger Priority Level P4 Setting this bit directly asserts a maskable interrupt of priority level P4. Clearing this bit removes this direct interrupt assertion. 0 = Do not assert the interrupt. 1 = Assert the interrupt. 2 SW_P3_TRIG Directly Trigger Priority Level P3 Setting this bit directly asserts a maskable interrupt of priority level P3. Clearing this bit removes this direct interrupt assertion. 0 = Do not assert the interrupt. 1 = Assert the interrupt. 1 SW_P2_TRIG Directly Trigger Priority Level P2 Setting this bit directly asserts a maskable interrupt of priority level P2. Clearing this bit removes this direct interrupt assertion. 0 = Do not assert the interrupt. 1 = Assert the interrupt. ElanTMSC520 Microcontroller Register Set Manual 12-11 Programmable Interrupt Controller Registers Bit 0 Name SW_P1_TRIG Function Directly Trigger Priority Level P1 Setting this bit directly asserts a maskable interrupt of priority level P1. Clearing this bit removes this direct interrupt assertion. This is the highest interrupt priority level. 0 = Do not assert the interrupt. 1 = Assert the interrupt. Programming Notes This register (SWINT16-1) and register SWINT22-17 provide access to all 22 maskable interrupt priority levels. Priority level P1 is the highest priority, and priority level P22 is the lowest. Setting an interrupt trigger bit causes an interrupt to be asserted on the corresponding PIC's interrupt channel for as long as the bit is set. To use these bits effectively, the interrupt service routines should clear the interrupt trigger bit early in the routine. Note that for the internal PC/AT-compatible peripherals, and for many PCI peripherals, existing drivers in off-theshelf operating systems are not aware of these interrupt trigger bits. For peripherals with these kinds of interrupt service routines, care must be taken not to set the interrupt trigger bits. If this occurs, the interrupt gets stuck in the asserted state and the system loops in the interrupt service routine because the routine does not clear the trigger bit. 12-12 ElanTMSC520 Microcontroller Register Set Manual Programmable Interrupt Controller Registers Software Interrupt 22-17/NMI Control (SWINT22_17) Memory-Mapped MMCR Offset D0Ah 7 Bit Reset R/W 6 NMI_TRIG 0 R/W 5 SW_P22_ TRIG 0 R/W 4 SW_P21_ TRIG 0 R/W 3 SW_P20_ TRIG 0 R/W 2 SW_P19_T RIG 0 R/W 1 SW_P18_ TRIG 0 R/W 0 SW_P17_ TRIG 0 R/W Reserved 0 RSV Register Description This register allows software to generate interrupt priority levels P17-P22 or the nonmaskable interrupt (NMI) to the CPU. Bit Definitions Bit 7 6 Name Reserved NMI_TRIG Function Reserved This bit field should be written to 0 for normal system operation. Software NMI Source Setting this bit directly asserts an NMI to the CPU. This bit should be cleared by software prior to setting the NMI_DONE bit of the PICICR register (see page 12-4). 0 = NMI not directly asserted (other sources can still assert an NMI). 1 = Directly assert the NMI to the CPU. Directly Trigger Priority Level P22 Setting this bit directly asserts a maskable interrupt of priority level P22. Clearing this bit removes this direct interrupt assertion. This is the lowest interrupt priority level. 0 = Do not assert the interrupt. 1 = Assert the interrupt. Directly Trigger Priority Level P21 Setting this bit directly asserts a maskable interrupt of priority level P21. Clearing this bit removes this direct interrupt assertion. 0 = Do not assert the interrupt. 1 = Assert the interrupt. Directly Trigger Priority Level P20 Setting this bit directly asserts a maskable interrupt of priority level P20. Clearing this bit removes this direct interrupt assertion. 0 = Do not assert the interrupt. 1 = Assert the interrupt. Directly Trigger Priority Level P19 Setting this bit directly asserts a maskable interrupt of priority level P19. Clearing this bit removes this direct interrupt assertion. 0 = Do not assert the interrupt. 1 = Assert the interrupt. Directly Trigger Priority Level P18 Setting this bit directly asserts a maskable interrupt of priority level P18. Clearing this bit removes this direct interrupt assertion. 0 = Do not assert the interrupt. 1 = Assert the interrupt. 5 SW_P22_TRIG 4 SW_P21_TRIG 3 SW_P20_TRIG 2 SW_P19_TRIG 1 SW_P18_TRIG ElanTMSC520 Microcontroller Register Set Manual 12-13 Programmable Interrupt Controller Registers Bit 0 Name SW_P17_TRIG Function Directly Trigger Priority Level P17 Setting this bit directly asserts a maskable interrupt of priority level P17. Clearing this bit removes this direct interrupt assertion. 0 = Do not assert the interrupt. 1 = Assert the interrupt. Programming Notes This register (SWINT22-17) and register SWINT16-1 provide access to all 22 maskable interrupt priority levels. Priority level P1 is the highest priority, and priority level P22 is the lowest. Setting an interrupt trigger bit causes an interrupt to be asserted on the corresponding PIC's interrupt channel for as long as the bit is set. To use these bits effectively, the interrupt service routines should clear the interrupt trigger bit early in the routine. Note that for the internal PC/AT-compatible peripherals, and for many PCI peripherals, existing drivers in off-theshelf operating systems are not aware of these interrupt trigger bits. For peripherals with these kinds of interrupt service routines, care must be taken not to set the interrupt trigger bits. If this occurs, the interrupt gets stuck in the asserted state and the system loops in the interrupt service routine because the routine does not clear the trigger bit. 12-14 ElanTMSC520 Microcontroller Register Set Manual Programmable Interrupt Controller Registers Interrupt Pin Polarity (INTPINPOL) Memory-Mapped MMCR Offset D10h 15 Bit Reset R/W 14 INTC_POL 0 R/W 6 GPINT6_ POL 0 R/W 13 INTB_POL 0 R/W 5 GPINT5_ POL 0 R/W 12 INTA_POL 0 R/W 4 GPINT4_ POL 0 R/W 11 Reserved 0 RSV 3 GPINT3_ POL 0 R/W 10 GPINT10 _POL 0 R/W 2 GPINT2_ POL 0 R/W 9 GPINT9_ POL 0 R/W 1 GPINT1_ POL 0 R/W 8 GPINT8_ POL 0 R/W 0 GPINT0_ POL 0 R/W INTD_POL 0 R/W 7 Bit Reset R/W GPINT7_ POL 0 R/W Register Description This register determines the polarity to be used for each external interrupt source. Bit Definitions Bit 15 Name INTD_POL Function PCI Interrupt Request INTD Polarity 0 = High-to-Low transition or Low-level-sensitive interrupt 1 = Low-to-High transition or High-level-sensitive interrupt PCI Interrupt Request INTC Polarity 0 = High-to-Low transition or Low-level-sensitive interrupt 1 = Low-to-High transition or High-level-sensitive interrupt PCI Interrupt Request INTB Polarity 0 = High-to-Low transition or Low-level-sensitive interrupt 1 = Low-to-High transition or High-level-sensitive interrupt PCI Interrupt Request INTA Polarity 0 = High-to-Low transition or Low-level-sensitive interrupt 1 = Low-to-High transition or High-level-sensitive interrupt Reserved This bit field should be written to 0 for normal system operation. General-Purpose Interrupt Request GPIRQ10 Polarity 0 = Low-to-High transition or High-level-sensitive interrupt 1 = High-to-Low transition or Low-level-sensitive interrupt General-Purpose Interrupt Request GPIRQ9 Polarity 0 = Low-to-High transition or High-level-sensitive interrupt 1 = High-to-Low transition or Low-level-sensitive interrupt General-Purpose Interrupt Request GPIRQ8 Polarity 0 = Low-to-High transition or High-level-sensitive interrupt 1 = High-to-Low transition or Low-level-sensitive interrupt General-Purpose Interrupt Request GPIRQ7 Polarity 0 = Low-to-High transition or High-level-sensitive interrupt 1 = High-to-Low transition or Low-level-sensitive interrupt 14 INTC_POL 13 INTB_POL 12 INTA_POL 11 10 Reserved GPINT10_POL 9 GPINT9_POL 8 GPINT8_POL 7 GPINT7_POL ElanTMSC520 Microcontroller Register Set Manual 12-15 Programmable Interrupt Controller Registers Bit 6 Name GPINT6_POL Function General-Purpose Interrupt Request GPIRQ6 Polarity 0 = Low-to-High transition or High-level-sensitive interrupt 1 = High-to-Low transition or Low-level-sensitive interrupt 5 GPINT5_POL General-Purpose Interrupt Request GPIRQ5 Polarity 0 = Low-to-High transition or High-level-sensitive interrupt 1 = High-to-Low transition or Low-level-sensitive interrupt 4 GPINT4_POL General-Purpose Interrupt Request GPIRQ4 Polarity 0 = Low-to-High transition or High-level-sensitive interrupt 1 = High-to-Low transition or Low-level-sensitive interrupt 3 GPINT3_POL General-Purpose Interrupt Request GPIRQ3 Polarity 0 = Low-to-High transition or High-level-sensitive interrupt 1 = High-to-Low transition or Low-level-sensitive interrupt 2 GPINT2_POL General-Purpose Interrupt Request GPIRQ2 Polarity 0 = Low-to-High transition or High-level-sensitive interrupt 1 = High-to-Low transition or Low-level-sensitive interrupt 1 GPINT1_POL General-Purpose Interrupt Request GPIRQ1 Polarity 0 = Low-to-High transition or High-level-sensitive interrupt 1 = High-to-Low transition or Low-level-sensitive interrupt 0 GPINT0_POL General-Purpose Interrupt Request GPIRQ0 Polarity 0 = Low-to-High transition or High-level-sensitive interrupt 1 = High-to-Low transition or Low-level-sensitive interrupt Programming Notes This register should be programmed only when the corresponding interrupt channel mask bits are enabled. At system reset, the INTx_POL bits (bits 15-12 of this register, INTPINPOL) are cleared to enable the active Low PCI interrupt to be used as a default so that no inversion is necessary for the PCI interrupt to be recognized correctly. If the INTx pins are to be configured for use as general-purpose interrupt sources (as opposed to PCI interrupt sources), then the correct polarity can be programmed as necessary using this register. 12-16 ElanTMSC520 Microcontroller Register Set Manual Programmable Interrupt Controller Registers PCI Host Bridge Interrupt Mapping (PCIHOSTMAP) Memory-Mapped MMCR Offset D14h 15 Bit Reset R/W 14 13 12 Reserved 11 10 9 8 PCI_NMI_ ENB 0 0 0 0 RSV 0 0 0 0 R/W 7 Bit Reset R/W 6 Reserved 5 4 3 2 PCI_IRQ_MAP[4-0] 1 0 0 0 RSV 0 0 0 0 R/W 0 0 Register Description This register maps the internally-generated PCI host bridge interrupt to any of the desired interrupt channels or as an NMI. It also enables the PCI Host Bridge NMI request as an NMI source. Bit Definitions Bit 15-9 8 Name Reserved PCI_NMI_ENB Function Reserved This bit field should be written to 0 for normal system operation. PCI Host Bridge NMI Enable This bit enables the PCI Host Bridge NMI request as an NMI source. 0 = PCI Host Bridge NMI request disabled as an NMI source 1 = PCI Host Bridge NMI request enabled as an NMI source This bit (PCI_NMI_ENB) has no effect on the PCI bus Host Bridge interrupt request, which can configured to generate an NMI by setting the PCI_IRQ_MAP bit field to 11111b. 7-5 Reserved Reserved This bit field should be written to 0 for normal system operation. ElanTMSC520 Microcontroller Register Set Manual 12-17 Programmable Interrupt Controller Registers Bit 4-0 Name PCI_IRQ_MAP [4-0] Function PCI Host Bridge Interrupt Mapping The value in this 5-bit field maps the internally-generated PCI Host Bridge interrupt to one of the following interrupt priority channels on the microcontroller or as an NMI. 00000 = Disables the internally-generated PCI interrupt from reaching the PIC 00001 = Priority P1 (Master PIC IR0) (Highest priority) 00010 = Priority P2 (Master PIC IR1) 00011 = Priority P3 (Slave 1 PIC IR0/Master PIC IR2) 00100 = Priority P4 (Slave 1 PIC IR1) 00101 = Priority P5 (Slave 1 PIC IR2) 00110 = Priority P6 (Slave 1 PIC IR3) 00111 = Priority P7 (Slave 1 PIC IR4) 01000 = Priority P8 (Slave 1 PIC IR5) 01001 = Priority P9 (Slave 1 PIC IR6) 01010 = Priority P10 (Slave 1 PIC IR7) 01011 = Priority P11 (Master PIC IR3) 01100 = Priority P12 (Master PIC IR4) 01101 = Priority P13 (Slave 2 PIC IR0/Master PIC IR5) 01110 = Priority P14 (Slave 2 PIC IR1) 01111 = Priority P15 (Slave 2 PIC IR2) 10000 = Priority P16 (Slave 2 PIC IR3) 10001 = Priority P17 (Slave 2 PIC IR4) 10010 = Priority P18 (Slave 2 PIC IR5) 10011 = Priority P19 (Slave 2 PIC IR6) 10100 = Priority P20 (Slave 2 PIC IR7) 10101 = Priority P21 (Master PIC IR6) 10110 = Priority P22 (Master PIC IR7) (Lowest priority) 10111-11110 = Disables the internally-generated PCI interrupt from reaching the PIC 11111 = NMI source For example, if PCI_IRQ_MAP = 01101b, the PCI interrupt request is mapped to interrupt priority P13 in the microcontroller. If PCI_IRQ_MAP = 00000b or any binary value from 10111-11110b, the PCI interrupt request is disabled from reaching the microcontroller's PIC. If this field is set to 11111b, then the PCI interrupt is routed and enabled as an NMI source. If bit S2 in the MPICICW3 register is cleared (see page 12-34), the Slave 1 PIC is bypassed, so programming the PCI_IRQ_MAP bit field to a value in the range 00100-01010b does not pass the interrupt request to the CPU. However, if this bit field is programmed to 00011b with the S2 bit cleared, the PCI interrupt request is routed to the Master PIC IR2 input. If bit S5 in the MPICICW3 register is cleared (see page 12-33), the Slave 2 PIC is bypassed, so programming the PCI_IRQ_MAP bit field to a value in the range 01110-10100b does not pass the interrupt request to the CPU. However, if this field is programmed to 01101b with the S5 bit cleared, the PCI interrupt request is routed to Master PIC IR5 input. Programming Notes This register should be programmed only when the corresponding interrupt channel mask bits are set in the PIC. For NMIs, this register should be programmed only when bit NMI_ENB is cleared in the PICICR register (see page 12-4). NMI_ENB can be set immediately after programming this register (PCIHOSTMAP) to allow NMIs to be passed to the CPU. Programming more than one interrupt source to an interrupt channel results in interrupt sharing on that channel. Programming more than one interrupt source as an NMI source results in NMI sharing on the CPU's NMI input. All interrupt and NMI sources can be found in the following register descriptions: s s s s s Software Interrupt 16-1 Control, page 12-10 Software Interrupt 22-17/NMI Control, page 12-13 PCI Host Bridge Interrupt Mapping, page 12-17 ECC Interrupt Mapping, page 12-19 Other interrupt mapping registers (30), page 12-21 ElanTMSC520 Microcontroller Register Set Manual 12-18 Programmable Interrupt Controller Registers ECC Interrupt Mapping (ECCMAP) Memory-Mapped MMCR Offset D18h 15 Bit Reset R/W 14 13 12 Reserved 11 10 9 8 ECC_NMI_ ENB 0 0 0 0 RSV 0 0 0 0 R/W 7 Bit Reset R/W 6 Reserved 5 4 3 2 ECC_IRQ_MAP[4-0] 1 0 0 0 RSV 0 0 0 0 R/W 0 0 Register Description This register maps the internally-generated ECC single-bit interrupt to any of the desired interrupt channels. It also enables the ECC multi-bit error as an NMI source. Bit Definitions Bit 15-9 8 Name Reserved ECC_NMI_ ENB Function Reserved This bit field should be written to 0 for normal system operation. ECC NMI Enable This bit enables the ECC multiple-bit error as an NMI source. 0 = ECC multiple-bit error disabled as an NMI source. 1 = ECC multiple-bit error enabled as an NMI source. Reserved This bit field should be written to 0 for normal system operation. 7-5 Reserved ElanTMSC520 Microcontroller Register Set Manual 12-19 Programmable Interrupt Controller Registers Bit 4-0 Name ECC_IRQ_MAP [4-0] Function SDRAM ECC Interrupt Mapping The value in this 5-bit field maps the internally-generated SDRAM ECC single-bit interrupt to one of the following interrupt priority channels on the microcontroller. 00000 = Disables the internally-generated ECC interrupt from reaching the PIC 00001 = Priority P1 (Master PIC IR0) (Highest priority) 00010 = Priority P2 (Master PIC IR1) 00011 = Priority P3 (Slave 1 PIC IR0/Master PIC IR2) 00100 = Priority P4 (Slave 1 PIC IR1) 00101 = Priority P5 (Slave 1 PIC IR2) 00110 = Priority P6 (Slave 1 PIC IR3) 00111 = Priority P7 (Slave 1 PIC IR4) 01000 = Priority P8 (Slave 1 PIC IR5) 01001 = Priority P9 (Slave 1 PIC IR6) 01010 = Priority P10 (Slave 1 PIC IR7) 01011 = Priority P11 (Master PIC IR3) 01100 = Priority P12 (Master PIC IR4) 01101 = Priority P13 (Slave 2 PIC IR0/Master PIC IR5) 01110 = Priority P14 (Slave 2 PIC IR1) 01111 = Priority P15 (Slave 2 PIC IR2) 10000 = Priority P16 (Slave 2 PIC IR3) 10001 = Priority P17 (Slave 2 PIC IR4) 10010 = Priority P18 (Slave 2 PIC IR5) 10011 = Priority P19 (Slave 2 PIC IR6) 10100 = Priority P20 (Slave 2 PIC IR7) 10101 = Priority P21 (Master PIC IR6) 10110 = Priority P22 (Master PIC IR7) (Lowest priority) 10111-11111 = Disables the internally-generated ECC interrupt from reaching the PIC For example, if ECC_IRQ_MAP = 01101b, the ECC interrupt request is mapped to interrupt priority P13 in the microcontroller. If ECC_IRQ_MAP = 00000b or any binary value from 10111-11111b, the ECC interrupt request is disabled from reaching the microcontroller's PIC. The single-bit ECC interrupt request cannot be routed as a source for generating an NMI. If bit S2 in the MPICICW3 register is cleared (see page 12-34), the Slave 1 PIC is bypassed, so programming the ECC_IRQ_MAP bit field to a value in the range 00100-01010b does not pass the interrupt request to the CPU. However, if this bit field is programmed to 00011b with the S2 bit cleared, the ECC interrupt request is routed to the Master PIC IR2 input. If bit S5 in the MPICICW3 register is cleared (see page 12-33), the Slave 2 PIC is bypassed, so programming the ECC_IRQ_MAP bit field to a value in the range 01110-10100b does not pass the interrupt request to the CPU. However, if this field is programmed to 01101b with the S5 bit cleared, the ECC interrupt request is routed to Master PIC IR5 input. Programming Notes This register should be programmed only when the corresponding interrupt channel mask bits are set in the PIC. For NMIs, this register should be programmed only when bit NMI_ENB is cleared in the PICICR register (see page 12-4). NMI_ENB can be set immediately after programming this register (ECCMAP) to allow NMIs to be passed to the CPU. Programming more than one interrupt source to an interrupt channel results in interrupt sharing on that channel. Programming more than one interrupt source as an NMI source results in NMI sharing on the CPU's NMI input. All interrupt and NMI sources can be found in the following register descriptions: s s s s s Software Interrupt 16-1 Control, page 12-10 Software Interrupt 22-17/NMI Control, page 12-13 PCI Host Bridge Interrupt Mapping, page 12-17 ECC Interrupt Mapping, page 12-19 Other interrupt mapping registers (30), page 12-21 12-20 ElanTMSC520 Microcontroller Register Set Manual Programmable Interrupt Controller Registers Memory-Mapped GP Timer 0 Interrupt Mapping (GPTMR0MAP) GP Timer 1 Interrupt Mapping (GPTMR1MAP) GP Timer 2 Interrupt Mapping (GPTMR2MAP) PIT 0 Interrupt Mapping (PIT0MAP) PIT 1 Interrupt Mapping (PIT1MAP) PIT 2 Interrupt Mapping (PIT2MAP) UART 1 Interrupt Mapping (UART1MAP) UART 2 Interrupt Mapping (UART2MAP) PCI Interrupt A Mapping (PCIINTAMAP) PCI Interrupt B Mapping (PCIINTBMAP) PCI Interrupt C Mapping (PCIINTCMAP) PCI Interrupt D Mapping (PCIINTDMAP) SSI Interrupt Mapping (SSIMAP) Watchdog Timer Interrupt Mapping (WDTMAP) RTC Interrupt Mapping (RTCMAP) Write-Protect Violation Interrupt Mapping (WPVMAP) AMDebugTM Technology RX/TX Interrupt Mapping (ICEMAP) Floating Point Error Interrupt Mapping (FERRMAP) GPIRQ0 Interrupt Mapping (GP0IMAP) GPIRQ1 Interrupt Mapping (GP1IMAP) GPIRQ2 Interrupt Mapping (GP2IMAP) GPIRQ3 Interrupt Mapping (GP3IMAP) GPIRQ4 Interrupt Mapping (GP4IMAP) GPIRQ5 Interrupt Mapping (GP5IMAP) GPIRQ6 Interrupt Mapping (GP6IMAP) GPIRQ7 Interrupt Mapping (GP7IMAP) GPIRQ8 Interrupt Mapping (GP8IMAP) GPIRQ9 Interrupt Mapping (GP9IMAP) GPIRQ10 Interrupt Mapping (GP10IMAP) MMCR Offset D1Ah MMCR Offset D1Bh MMCR Offset D1Ch MMCR Offset D20h MMCR Offset D21h MMCR Offset D22h MMCR Offset D28h MMCR Offset D29h MMCR Offset D30h MMCR Offset D31h MMCR Offset D32h MMCR Offset D33h MMCR Offset D41h MMCR Offset D42h MMCR Offset D43h MMCR Offset D44h MMCR Offset D45h MMCR Offset D46h MMCR Offset D50h MMCR Offset D51h MMCR Offset D52h MMCR Offset D53h MMCR Offset D54h MMCR Offset D55h MMCR Offset D56h MMCR Offset D57h MMCR Offset D58h MMCR Offset D59h MMCR Offset D5Ah DMA Buffer Chaining Interrupt Mapping (DMABCINTMAP) MMCR Offset D40h 7 Bit Reset R/W 6 Reserved 5 4 3 2 INT_MAP[4-0] 1 0 0 0 RSV 0 0 0 0 R/W 0 0 ElanTMSC520 Microcontroller Register Set Manual 12-21 Programmable Interrupt Controller Registers Register Description These registers map each of the interrupt sources (except for ECC and PCI Host Bridge interrupts, see page 12-19 and page 12-17, respectively) to their desired interrupt channel or NMI. Bit Definitions Bit 7-5 4-0 Name Reserved INT_MAP[4-0] Function Reserved This bit field should be written to 0 for normal system operation. Interrupt Mapping The value in this 5-bit field maps the interrupt source for the register to one of the following interrupt priority channels on the microcontroller or as an NMI. 00000 = Disables the interrupt source as an input 00001 = Priority P1 (Master PIC IR0) (Highest priority) 00010 = Priority P2 (Master PIC IR1) 00011 = Priority P3 (Slave 1 PIC IR0/Master PIC IR2) 00100 = Priority P4 (Slave 1 PIC IR1) 00101 = Priority P5 (Slave 1 PIC IR2) 00110 = Priority P6 (Slave 1 PIC IR3) 00111 = Priority P7 (Slave 1 PIC IR4) 01000 = Priority P8 (Slave 1 PIC IR5) 01001 = Priority P9 (Slave 1 PIC IR6) 01010 = Priority P10 (Slave 1 PIC IR7) 01011 = Priority P11 (Master PIC IR3) 01100 = Priority P12 (Master PIC IR4) 01101 = Priority P13 (Slave 2 PIC IR0/Master PIC IR5) 01110 = Priority P14 (Slave 2 PIC IR1) 01111 = Priority P15 (Slave 2 PIC IR2) 10000 = Priority P16 (Slave 2 PIC IR3) 10001 = Priority P17 (Slave 2 PIC IR4) 10010 = Priority P18 (Slave 2 PIC IR5) 10011 = Priority P19 (Slave 2 PIC IR6) 10100 = Priority P20 (Slave 2 PIC IR7) 10101 = Priority P21 (Master PIC IR6) 10110 = Priority P22 (Master PIC IR7) (Lowest priority) 10111 - 11110 = Disables the interrupt source as an input 11111 = NMI source For example, if INT_MAP = 01101b, the interrupt request is mapped to interrupt priority P13 in the microcontroller. If INT_MAP = 00000b or any binary value from 10111-11110b, the interrupt request is disabled from reaching the microcontroller's PIC. If this field is set to 11111b, then the interrupt is routed to generate an NMI. If bit S2 in the MPICICW3 register is cleared (see page 12-34), the Slave 1 PIC is bypassed, so programming the INT_MAP bit field to a value in the range 00100-01010b does not pass the interrupt request to the CPU. However, if this bit field is programmed to 00011b with the S2 bit cleared, the interrupt request is routed to the Master PIC IR2 input. If bit S5 in the MPICICW3 register is cleared (see page 12-33), the Slave 2 PIC is bypassed, so programming the INT_MAP bit field to a value in the range 01110-10100b does not pass the interrupt request to the CPU. However, if this field is programmed to 01101b with the S5 bit cleared, the interrupt request is routed to Master PIC IR5 input. Programming Notes This register should be programmed only when the corresponding interrupt channel mask bits are set in the PIC. For NMIs, this register should be programmed only when bit NMI_ENB is cleared in the PICICR register (see page 12-4). NMI_ENB can be set immediately after programming this mapping register to allow NMIs to be passed to the CPU. 12-22 ElanTMSC520 Microcontroller Register Set Manual Programmable Interrupt Controller Registers Programming more than one interrupt source to an interrupt channel results in interrupt sharing on that channel. Programming more than one interrupt source as an NMI source results in NMI sharing on the CPU's NMI input. All interrupt and NMI sources can be found in the following register descriptions: s s s s s Software Interrupt 16-1 Control, page 12-10 Software Interrupt 22-17/NMI Control, page 12-13 PCI Host Bridge Interrupt Mapping, page 12-17 ECC Interrupt Mapping, page 12-19 Other interrupt mapping registers (30), page 12-21 ElanTMSC520 Microcontroller Register Set Manual 12-23 Programmable Interrupt Controller Registers Master PIC Interrupt Request (MPICIR) Direct-Mapped I/O Address 0020h 7 Bit Reset R/W 6 IR6 x R 5 IR5 x R 4 IR4 x R 3 IR3 x R 2 IR2 x R 1 IR1 x R 0 IR0 x R IR7 x R Register Description This register provides a real-time status of the interrupt request inputs to the Master PIC. This register latches all incoming interrupt requests and provides individual status of the requests to be acknowledged. Bit Definitions Bit 7 Name IR7 Function Interrupt Request 7 0 = The IR7 input to the Master PIC is not asserted. 1 = The IR7 input is asserted. Interrupt Request 6 0 = The IR6 input to the Master PIC is not asserted. 1 = The IR6 input is asserted. Interrupt Request 5 0 = The IR5 input to the Master PIC is not asserted. 1 = The IR5 input is asserted. Interrupt Request 4 0 = The IR4 input to the Master PIC is not asserted. 1 = The IR4 input is asserted. Interrupt Request 3 0 = The IR3 input to the Master PIC is not asserted. 1 = The IR3 input is asserted. Interrupt Request 2 0 = The IR2 input to the Master PIC is not asserted. 1 = The IR2 input is asserted. Interrupt Request 1 0 = The IR1 input to the Master PIC is not asserted. 1 = The IR1 input is asserted. Interrupt Request 0 0 = The IR0 input to the Master PIC is not asserted. 1 = The IR0 input is asserted. 6 IR6 5 IR5 4 IR4 3 IR3 2 IR2 1 IR1 0 IR0 Programming Notes This register (MPICIR) is accessed by first writing a value of 0Ah to Port 0020h followed by a read-back from Port 0020h. Because the Slave 1 PIC cascades into Channel 2 of the Master PIC, the IR2 bit is a real-time status indication that one of the Slave 1 interrupt request inputs is asserted. Because the Slave 2 PIC cascades into Channel 5 of the Master PIC, the IR5 bit is a real-time status indication that one of the Slave 2 interrupt request inputs is asserted. 12-24 ElanTMSC520 Microcontroller Register Set Manual Programmable Interrupt Controller Registers Master PIC In-Service (MPICISR) Direct-Mapped I/O Address 0020h 7 Bit Reset R/W 6 IS6 x R 5 IS5 x R 4 IS4 x R 3 IS3 x R 2 IS2 x R 1 IS1 x R 0 IS0 x R IS7 x R Register Description This register indicates the Master interrupt priority levels that are being serviced. Bit Definitions Bit 7 Name IS7 Function Interrupt Request 7 In-Service 0 = Interrupt request 7 is not being serviced. 1 = Interrupt request 7 is being serviced. Interrupt Request 6 In-Service 0 = Interrupt request 6 is not being serviced. 1 = Interrupt request 6 is being serviced. Interrupt Request 5 In-Service 0 = Interrupt request 5 is not being serviced. 1 = Interrupt request 5 is being serviced. Interrupt Request 4 In-Service 0 = Interrupt request 4 is not being serviced. 1 = Interrupt request 4 is being serviced. Interrupt Request 3 In-Service 0 = Interrupt request 3 is not being serviced. 1 = Interrupt request 3 is being serviced. Interrupt Request 2 In-Service 0 = Interrupt request 2 is not being serviced. 1 = Interrupt request 2 is being serviced. Interrupt Request 1 In-Service 0 = Interrupt request 1 is not being serviced. 1 = Interrupt request 1 is being serviced. Interrupt Request 0 In-Service 0 = Interrupt request 0 is not being serviced. 1 = Interrupt request 0 is being serviced. 6 IS6 5 IS5 4 IS4 3 IS3 2 IS2 1 IS1 0 IS0 Programming Notes This register (MPICISR) is accessed by first writing a value of 0Bh to Port 0020h followed by a read-back from Port 0020h. Because the Slave 1 PIC cascades into Channel 2 of the Master PIC, the IS2 bit is asserted if any of the Slave 1 interrupt request levels is asserted. Because the Slave 2 PIC cascades into Channel 5 of the Master PIC, the IS5 bit is asserted if any of the Slave 2 interrupt request levels is asserted. ElanTMSC520 Microcontroller Register Set Manual 12-25 Programmable Interrupt Controller Registers Master PIC Initialization Control Word 1 (MPICICW1) Direct-Mapped I/O Address 0020h 7 Bit Reset R/W 6 Reserved 5 4 SLCT_ ICW1 3 LTIM x W 2 ADI 1 W 1 SNGL x W 0 IC4 x W x x RSV! x x W Register Description This register is the first initialization register of the Master controller. Bit Definitions Bit 7-5 Name Reserved Function Reserved This bit field should be written to 0 for normal system operation. This I/O address changes functions when read. See the programming notes for this register (MPICICW1) on page 12-27. Select ICW1 Software must set this bit to 1 when writing this address (Port 0020h) to access this register (MPICICW1). 0 = The write does not access this register (MPICICW1). Instead, either the MPICOCW2 register (see page 12-28) or the MPICOCW3 register (see page 12-30) is written, depending on the state of bit 3. 1 = The write accesses this register (MPICICW1). Subsequent writes to Port 0021h access additional initialization control words. See the programming notes for this register (MPICICW1) on page 12-27. 4 SLCT_ICW1 3 LTIM Level-Triggered Interrupt Mode This bit is the global interrupt mode selection for the Master PIC. 0 = Edge-sensitive interrupt request detection 1 = Level-sensitive interrupt request detection If the M_GINT_MODE bit in the PICICR register is set (see page 12-5), the LTIM bit determines the interrupt mode for the Master PIC channels. If the M_GINT_MODE bit is cleared, the Master LTIM bit has no meaning, and the Master PIC channel modes can be programmed individually via the MPICMODE register (see page 12-6). 2 ADI Address Interval 0 = Interrupt vectors are separated by eight locations (not valid in the ELANSC520 microcontroller). 1 = Interrupt vectors are separated by four locations. In the ELANSC520 microcontroller design, this PC/AT-compatible bit (ADI) is internally fixed to 1. 1 SNGL Single PIC 0 = Cascade mode; MPICICW3 is expected. 1 = Single PIC in the system; MPICICW3 is not expected. Setting this bit logically removes the Slave 1 and Slave 2 controllers from the Master PIC. This routes the interrupt requests that were hooked to IR0 of the Slave 1 and Slave 2 controllers directly to interrupt requests IR2 and IR5 of the Master PIC, respectively. If this bit is set, then the internal register pointer skips MPICICW3 and points to MPICICW4 if MPICICW4 was selected to be programmed via the IC4 bit. See the programming notes for this register (MPICICW1) on page 12-27. 12-26 ElanTMSC520 Microcontroller Register Set Manual Programmable Interrupt Controller Registers Bit 0 Name IC4 Function Initialization Control Word 4 Software uses this bit to indicate whether it intends to explicitly program the MPICICW4 register (see page 12-35) after writing to the MPICICW3 register (see page 12-33). See the programming notes on this page for details. 0 = The MPICICW4 register is initialized internally when this register (MPICICW1) is written. The PIC does not expect software to write to the MPICICW4 register after writing to the MPICICW3 register. 1 = The MPICICW4 register is not initialized by the write to this register (MPICICW1). Software is expected to initialize the MPICICW4 register. Programming Notes The PIC's initialization control word (MPICICWx) registers 1-4 must be programmed in sequence. Writing to Port 0020h with bit 4 = 1 causes the MPICICW1 register to be written and also resets the PIC's internal state machine and the internal MPICICWx register pointer. Then MPICICWx registers 2-4 can be programmed by sequential writes to Port 0021h. Each time Port 0021h is written to (following the write to MPICICW1), the internal register pointer points to the next MPICICWx register. MPICICW1 and MPICICW2 must always be programmed. The MPICICW3 register is skipped if the SNGL bit in MPICICW1 is 1. The MPICICW4 register is skipped if the IC4 bit in MPICICW1 is 0. I/O Port 0020h provides access to different Master PIC registers based on the data that is written. Table 12-3 provides a summary of bit patterns to write for access to each register. Table 12-3 Master PIC I/O Port 0020h Access Summary Bits 7 x 0 0 0 0 6 x x 0 0 0 5 x x 0 0 0 4 0 0 0 0 1 3 0 1 1 1 x 2 x x 0 0 x 1 x 0 1 1 x 0 x x 0 1 x Port 0020h Register Written MPICOCW2 (page 12-28) MPICOCW3 (page 12-30) MPICOCW3 MPICOCW3 MPICICW1 (page 12-26) Next Port 0020h Read Returns -- -- MPICIR (page 12-24) MPICISR (page 12-25) -- ElanTMSC520 Microcontroller Register Set Manual 12-27 Programmable Interrupt Controller Registers Master PIC Operation Control Word 2 (MPICOCW2) Direct-Mapped I/O Address 0020h 7 Bit Reset R/W 6 R_SL_EOI[2-0] 5 4 SLCT_ ICW1 3 IS_OCW3 x W 2 1 LS[2-0] 0 x x W x x W x x W x Register Description This register provides control for various interrupt priority and end-of-interrupt (EOI) modes. It also controls write access for this register (MPICOCW2) and for the MPICOCW3 and MPICICW1 registers (see page 12-30 and page 12-26). Bit Definitions Bit 7-5 Name R_SL_EOI[2-0] Function Interrupt Request EOI and Priority Rotation Controls 000 = Rotate in auto EOI mode (clear) 001 = Nonspecific EOI 010 = No operation 011 = Specific EOI 100 = Rotate in auto EOI mode (set) 101 = Rotate on nonspecific EOI command 110 = Set priority command 111 = Rotate on specific EOI command 4 SLCT_ICW1 Select ICW1 Software must clear this bit to 0 when writing this address (Port 0020h) to access either this register (MPICOCW2) or the MPICOCW3 register. 0 = The write accesses either this register (MPICOCW2) or the MPICOCW3 register (see page 12-30), depending on the state of bit 3. 1 = The write accesses the MPICICW1 register (see page 12-26). Access is OCW3 Software must clear this bit (IS_OCW3) and clear SLCT_ICW1 when writing this address (Port 0020h) to access this register (MPICOCW2). 0 = The write accesses this register (MPICOCW2) if the SLCT_ICW1 bit is cleared. 1 = The write accesses the MPICOCW3 register (see page 12-30) if the SLCT_ICW1 bit is cleared. 3 IS_OCW3 2-0 LS[2-0] Specific EOI Level Select Interrupt level that is acted upon when the SL bit = 1 (see bits 7-5 of this register): 000 = IR0 001 = IR1 010 = IR2 011 = IR3 100 = IR4 101 = IR5 110 = IR6 111 = IR7 12-28 ElanTMSC520 Microcontroller Register Set Manual Programmable Interrupt Controller Registers Programming Notes I/O Port 0020h provides access to different Master PIC registers based on the data that is written. Table 12-4 provides a summary of bit patterns to write for access to each register. Table 12-4 Master PIC I/O Port 0020h Access Summary (Same as Table 12-3) Bits 7 x 0 0 0 0 6 x x 0 0 0 5 x x 0 0 0 4 0 0 0 0 1 3 0 1 1 1 x 2 x x 0 0 x 1 x 0 1 1 x 0 x x 0 1 x Port 0020h Register Written MPICOCW2 (page 12-28) MPICOCW3 (page 12-30) MPICOCW3 MPICOCW3 MPICICW1 (page 12-26) Next Port 0020h Read Returns -- -- MPICIR (page 12-24) MPICISR (page 12-25) -- ElanTMSC520 Microcontroller Register Set Manual 12-29 Programmable Interrupt Controller Registers Master PIC Operation Control Word 3 (MPICOCW3) Direct-Mapped I/O Address 0020h 7 Bit Reset R/W 6 5 4 SLCT_ ICW1 x W 3 IS_OCW3 x W 2 P x W 1 0 Reserved x RSV! ESMM_SMM[1-0] 1 W x RR_RIS[1-0] x W x Register Description This register controls the PIC's mask and poll modes. It also controls read access for the MPICIR and MPICISR registers (see page 12-24 and page 12-25), and write access for this register (MPICOCW3) and for the MPICOCW2 and MPICICW1 registers (see page 12-28 and page 12-26). Bit Definitions Bit 7 Name Reserved Function Reserved This bit field should be written to 0 for normal system operation. This I/O address changes functions when read. See the programming notes for this register (MPICOCW3) on page 12-31. Special Mask Mode 00 = No operation 01 = No operation 10 = Reset special mask 11 =Set special mask 6-5 ESMM_SMM [1-0] 4 SLCT_ICW1 Initialization Control Word 1 Select Software must clear this bit to 0 when writing this address (Port 0020h) to access either this register (MPICOCW3) or the MPICOCW2 register. 0 = The write accesses either this register (MPICOCW3) or the MPICOCW2 register (see page 12-28), depending on the state of bit 3. 1 = The write accesses the MPICICW1 register (see page 12-26). Access is OCW3 Software must set this bit (IS_OCW3) and clear SLCT_ICW1 when writing this address (Port 0020h) to access this register (MPICOCW3). 0 = The write accesses the MPICOCW2 register (see page 12-28) if the SLCT_ICW1 bit is cleared. 1 = The write accesses this register (MPICOCW3) if the SLCT_ICW1 bit is cleared. PIC Poll Command A system designer can choose to use the PIC in a non-interrupting mode. In this case, the interrupt controller can be polled for the status of pending interrupts. To support this PC/ATincompatible mode of operation, the PIC supports a special poll command that is invoked by setting this bit. 0 = Not poll command 1 = Poll command Status Register Select 00 = No change from last state 01 = No change from last state 10 = Next Port 0020h read returns the MPICIR register's contents (see page 12-24). 11 = Next Port 0020h read returns the MPICISR register's contents (see page 12-25). 3 IS_OCW3 2 P 1-0 RR_RIS[1-0] 12-30 ElanTMSC520 Microcontroller Register Set Manual Programmable Interrupt Controller Registers Programming Notes I/O Port 0020h provides access to different Master PIC registers based on the data that is written. Table 12-5 provides a summary of bit patterns to write for access to each register. Table 12-5 Master PIC I/O Port 0020h Access Summary (Same as Table 12-3) Bits 7 x 0 0 0 0 6 x x 0 0 0 5 x x 0 0 0 4 0 0 0 0 1 3 0 1 1 1 x 2 x x 0 0 x 1 x 0 1 1 x 0 x x 0 1 x Port 0020h Register Written MPICOCW2 (page 12-28) MPICOCW3 (page 12-30) MPICOCW3 MPICOCW3 MPICICW1 (page 12-26) Next Port 0020h Read Returns -- -- MPICIR (page 12-24) MPICISR (page 12-25) -- ElanTMSC520 Microcontroller Register Set Manual 12-31 Programmable Interrupt Controller Registers Master PIC Initialization Control Word 2 (MPICICW2) Direct-Mapped I/O Address 0021h 7 Bit Reset R/W 6 5 T7-T3 4 3 2 1 A10-A8 0 x x x W x x x x W x Register Description This register is the second initialization register of the Master controller. Bit Definitions Bit 7-3 Name T7-T3 Function Bits 7-3 of Base Interrupt Vector Number for this PIC The PIC concatenates the T7-T3 bit field value to the 3-bit PIC interrupt request level (in the bit 2-0 position) to form the interrupt vector. For example, in a PC/AT-compatible system, bits T7-T3 for the Master PIC are programmed to 00001b so the Master PIC IR0 channel generates an interrupt 08h vector (PC/AT IRQ0); and bits T7-T3 for the Slave 1 PIC are programmed to 01110b so the Slave 1 PIC IR0 channel generates an interrupt 70h (PC/AT IRQ8). A10-A8 of Interrupt Vector This bit field should be written to 0 for normal operation. (It is always = 0 in a PC/AT-compatible system.) 2-0 A10-A8 Programming Notes The PIC's initialization control word (MPICICWx) registers 1-4 must be programmed in sequence. Writing to Port 0020h with bit 4 = 1 causes the MPICICW1 register to be written and also resets the PIC's internal state machine and the internal MPICICWx register pointer. Then MPICICWx registers 2-4 can be programmed by sequential writes to Port 0021h. Each time Port 0021h is written to (following the write to MPICICW1), the internal register pointer points to the next MPICICWx register. MPICICW1 and MPICICW2 must always be programmed. The MPICICW3 register is skipped if the SNGL bit in MPICICW1 is 1. The MPICICW4 register is skipped if the IC4 bit in MPICICW1 is 0. 12-32 ElanTMSC520 Microcontroller Register Set Manual Programmable Interrupt Controller Registers Master PIC Initialization Control Word 3 (MPICICW3) Direct-Mapped I/O Address 0021h 7 Bit Reset R/W 6 S6 0 W 5 S5 x W 4 S4 0 W 3 S3 0 W 2 S2 x W 1 S1 0 W 0 S0 0 W S7 0 W Register Description This register is the 3rd initialization register of the Master controller. Bit Definitions Bit 7 Name S7 Function Channel 7 Slave Cascade Select 0 = I/O device attached to IR7 input 1 = IR7 input used for slave cascading (not valid in the ELANSC520 microcontroller) In the ELANSC520 microcontroller, this bit is internally fixed to 0. 6 S6 Channel 6 Slave Cascade Select 0 = I/O device attached to IR6 input 1 = IR6 input used for slave cascading (not valid in the ELANSC520 microcontroller) In the ELANSC520 microcontroller, this bit is internally fixed to 0. 5 S5 Channel 5 Slave Cascade Select 0 = I/O device attached to IR5 input 1 = IR5 input used for slave cascading This bit allows the Slave 2 controller to be logically cascaded or removed from the Master PIC. Since the output of the Slave 2 controller is hard-wired to interrupt channel 5 of the Master PIC, this bit can be used to make the Slave 2 controller transparent to the user. If this bit is set, Slave 2 controller is cascaded to the Master PIC. If this bit is cleared, Slave 2 is logically removed from the cascade chain. The interrupt request that is hooked to IR0 of the Slave 2 controller is now routed directly to interrupt channel 5 of the Master PIC, bypassing the Slave 2 controller. This is useful where fewer than eight interrupts are needed in a system. In this case, a single EOI would need to be generated instead of two. 4 S4 Channel 4 Slave Cascade Select 0 = I/O device attached to IR4 input 1 = IR4 input used for slave cascading (not valid in the ELANSC520 microcontroller) In the ELANSC520 microcontroller, this bit is internally fixed to 0. ElanTMSC520 Microcontroller Register Set Manual 12-33 Programmable Interrupt Controller Registers Bit 3 Name S3 Function Channel 3 Slave Cascade Select 0 = I/O device attached to IR3 input 1 = IR3 input used for slave cascading (not valid in the ELANSC520 microcontroller) In the ELANSC520 microcontroller, this bit is internally fixed to 0. 2 S2 Channel 2 Slave Cascade Select 0 = I/O device attached to IR2 input 1 = IR2 input used for slave cascading This bit allows the Slave 1 controller to be logically cascaded or removed from the Master PIC. Since the output of the Slave 1 controller is hard-wired to interrupt channel 2 of the Master PIC, this bit can be used to make the Slave 1 controller transparent to the user. If this bit is set, Slave 1 controller is cascaded to the Master PIC. If this bit is cleared, Slave 1 is logically removed from the cascade chain. The interrupt request that is hooked to IR0 of the Slave 1 controller is now routed directly to interrupt channel 2 of the Master PIC, bypassing the Slave 1 controller. This is useful where fewer than eight interrupts are needed in a system. In this case, a single EOI would need to be generated instead of two. 1 S1 Channel 1 Slave Cascade Select 0 = I/O device attached to IR1 input 1 = IR1 input used for slave cascading (not valid in the ELANSC520 microcontroller) In the ELANSC520 microcontroller, this bit is internally fixed to 0. 0 S0 Channel 0 Slave Cascade Select 0 = I/O device attached to IR0 input 1 = IR0 input used for slave cascading (not valid in the ELANSC520 microcontroller) In the ELANSC520 microcontroller, this bit is internally fixed to 0. Programming Notes If bits S5 and S2 of this register (MPICICW3) are cleared, both the slave controllers are logically removed from the cascade chain to the Master controller and only eight interrupt request priority levels are available to the user. The PIC's initialization control word (MPICICWx) registers 1-4 must be programmed in sequence. Writing to Port 0020h with bit 4 = 1 causes the MPICICW1 register to be written and also resets the PIC's internal state machine and the internal MPICICWx register pointer. Then MPICICWx registers 2-4 can be programmed by sequential writes to Port 0021h. Each time Port 0021h is written to (following the write to MPICICW1), the internal register pointer points to the next MPICICWx register. MPICICW1 and MPICICW2 must always be programmed. The MPICICW3 register is skipped if the SNGL bit in MPICICW1 is 1. The MPICICW4 register is skipped if the IC4 bit in MPICICW1 is 0. 12-34 ElanTMSC520 Microcontroller Register Set Manual Programmable Interrupt Controller Registers Master PIC Initialization Control Word 4 (MPICICW4) Direct-Mapped I/O Address 0021h 7 Bit Reset R/W 6 Reserved 5 4 SFNM 3 2 1 AEOI x W 0 PM 1 W BUF_M/S[1-0] 0 W 0 x x RSV! x x W Register Description This register is the fourth initialization register of the Master controller. Bit Definitions Bit 7-5 4 Name Reserved SFNM Function Reserved This bit field should be written to 0 for normal system operation. This bit field is write-only. Special Fully Nested Mode Enable 0 = Normal nested mode 1 = Special fully nested mode Buffered Mode and Master/Slave Select 00 = Non-buffered mode 01 = Non-buffered mode 10 = Buffered mode/slave 11 = Buffered mode/Master In the ELANSC520 microcontroller design, these bits are internally fixed to 00b. 3-2 BUF_M/S[1-0] 1 AEOI Automatic EOI Mode 0 = Normal EOI: the interrupt handler must send an End of Interrupt command to the PIC(s). 1 = Auto EOI: the EOI is automatically performed after the second interrupt acknowledge signal from the CPU. 0 PM Microprocessor Mode 0 = 8080/8085 mode 1 = 8086 mode In the ELANSC520 microcontroller design, this PC/AT-compatible bit is internally fixed to 1. Programming Notes Initialization of this register is optional unless the IC4 bit is set in the MPICICW1 register (see page 12-27). If the IC4 bit is cleared, the ELANSC520 microcontroller uses 01h for the value of this register (MPICICW4). The PIC's initialization control word (MPICICWx) registers 1-4 must be programmed in sequence. Writing to Port 0020h with bit 4 = 1 causes the MPICICW1 register to be written and also resets the PIC's internal state machine and the internal MPICICWx register pointer. Then MPICICWx registers 2-4 can be programmed by sequential writes to Port 0021h. Each time Port 0021h is written to (following the write to MPICICW1), the internal register pointer points to the next MPICICWx register. MPICICW1 and MPICICW2 must always be programmed. The MPICICW3 register is skipped if the SNGL bit in MPICICW1 is 1. The MPICICW4 register is skipped if the IC4 bit in MPICICW1 is 0. Note that AEOI mode is not supported by the Slave 1 PIC or Slave 2 PIC. ElanTMSC520 Microcontroller Register Set Manual 12-35 Programmable Interrupt Controller Registers Master PIC Interrupt Mask (MPICINTMSK) Direct-Mapped I/O Address 0021h 7 Bit Reset R/W 6 IM6 x R/W 5 IM5 x R/W 4 IM4 x R/W 3 IM3 x R/W 2 IM2 x R/W 1 IM1 x R/W 0 IM0 x R/W IM7 x R/W Register Description This register provides masking of individual interrupt requests for the Master controller. This register is also known as Operation Control Word 1 in other PC/AT-compatible designs. Bit Definitions Bit 7 Name IM7 Function IR7 Mask 0 = Unmask IR7 1 = Mask IR7 IR6 Mask 0 = Unmask IR6 1 = Mask IR6 IR5 Mask 0 = Unmask IR5 1 = Mask IR5 If the S5 bit in the MPICICW3 register is set (see page 12-33), setting the IM5 bit inhibits interrupt requests assigned to Slave 2 controller inputs from reaching the CPU. Clearing this bit allows interrupts from Slave 2 controller to be propagated to the CPU. IR4 Mask 0 = Unmask IR4 1 = Mask IR4 IR3 Mask 0 = Unmask IR3 1 = Mask IR3 IR2 Mask 0 = Unmask IR2 1 = Mask IR2 If the S2 bit in the MPICICW3 register is set (see page 12-34), setting the IM2 bit inhibits interrupt requests assigned to Slave 1 controller inputs from reaching the CPU. Clearing this bit allows interrupts from Slave 1 controller to be propagated to the CPU. IR1 Mask 0 = Unmask IR1 1 = Mask IR1 IR0 Mask 0 = Unmask IR0 1 = Mask IR0 6 IM6 5 IM5 4 IM4 3 IM3 2 IM2 1 IM1 0 IM0 Programming Notes This register (MPICINTMSK) cannot be accessed during a Master PIC initialization control sequence, which is initiated by setting the SLCT_ICW1 bit in the MPICICW1 register (see page 12-26). When the MPICICWx register initialization sequence is not in effect, any read or write of Port 0021h accesses the MPICINTMSK register. 12-36 ElanTMSC520 Microcontroller Register Set Manual Programmable Interrupt Controller Registers Slave 2 PIC Interrupt Request (S2PICIR) Direct-Mapped I/O Address 0024h 7 Bit Reset R/W 6 IR6 x R 5 IR5 x R 4 IR4 x R 3 IR3 x R 2 IR2 x R 1 IR1 x R 0 IR0 x R IR7 x R Register Description This register provides a real-time status of the interrupt request inputs to the Slave 2 PIC. This register latches all incoming interrupt requests and provides individual status of the requests to be acknowledged. Bit Definitions Bit 7 Name IR7 Function Interrupt Request 7 0 = The IR7 input to the Slave 2 PIC is not asserted. 1 = The IR7 input is asserted. Interrupt Request 6 0 = The IR6 input to the Slave 2 PIC is not asserted. 1 = The IR6 input is asserted. Interrupt Request 5 0 = The IR5 input to the Slave 2 PIC is not asserted. 1 = The IR5 input is asserted. Interrupt Request 4 0 = The IR4 input to the Slave 2 PIC is not asserted. 1 = The IR4 input is asserted. Interrupt Request 3 0 = The IR3 input to the Slave 2 PIC is not asserted. 1 = The IR3 input is asserted. Interrupt Request 2 0 = The IR2 input to the Slave 2 PIC is not asserted. 1 = The IR2 input is asserted. Interrupt Request 1 0 = The IR1 input to the Slave 2 PIC is not asserted. 1 = The IR1 input is asserted. Interrupt Request 0 0 = The IR0 input to the Slave 2 PIC is not asserted. 1 = The IR0 input is asserted. 6 IR6 5 IR5 4 IR4 3 IR3 2 IR2 1 IR1 0 IR0 Programming Notes This register (S2PICIR) is accessed by first writing a value of 0Ah to Port 0024h followed by a read-back from Port 0024h. If the S5 bit in the MPICICW3 register is cleared (see page 12-33), then the Slave 2 controller is bypassed and any interrupt requests latched in this register (S2PICIR) are not propagated to the CPU. ElanTMSC520 Microcontroller Register Set Manual 12-37 Programmable Interrupt Controller Registers Slave 2 PIC In-Service (S2PICISR) Direct-Mapped I/O Address 0024h 7 Bit Reset R/W 6 IS6 x R 5 IS5 x R 4 IS4 x R 3 IS3 x R 2 IS2 x R 1 IS1 x R 0 IS0 x R IS7 x R Register Description This register indicates the Slave 2 interrupt priority levels that are being serviced. Bit Definitions Bit 7 Name IS7 Function Interrupt Request 7 In-Service 0 = Interrupt request 7 is not being serviced. 1 = Interrupt request 7 is being serviced. Interrupt Request 6 In-Service 0 = Interrupt request 6 is not being serviced. 1 = Interrupt request 6 is being serviced. Interrupt Request 5 In-Service 0 = Interrupt request 5 is not being serviced. 1 = Interrupt request 5 is being serviced. Interrupt Request 4 In-Service 0 = Interrupt request 4 is not being serviced. 1 = Interrupt request 4 is being serviced. Interrupt Request 3 In-Service 0 = Interrupt request 3 is not being serviced. 1 = Interrupt request 3 is being serviced. Interrupt Request 2 In-Service 0 = Interrupt request 2 is not being serviced. 1 = Interrupt request 2 is being serviced. Interrupt Request 1 In-Service 0 = Interrupt request 1 is not being serviced. 1 = Interrupt request 1 is being serviced. Interrupt Request 0 In-Service 0 = Interrupt request 0 is not being serviced. 1 = Interrupt request 0 is being serviced. 6 IS6 5 IS5 4 IS4 3 IS3 2 IS2 1 IS1 0 IS0 Programming Notes This register (S2PICISR) is accessed by first writing a value of 0Bh to Port 0024h followed by a read-back from Port 0024h. If the S5 bit in the MPICICW3 register is cleared (see page 12-33), then the Slave 2 controller is bypassed and interrupt requests latched are not serviced. 12-38 ElanTMSC520 Microcontroller Register Set Manual Programmable Interrupt Controller Registers Slave 2 PIC Initialization Control Word 1 (S2PICICW1) Direct-Mapped I/O Address 0024h 7 Bit Reset R/W 6 Reserved 5 4 SLCT_ ICW1 3 LTIM x W 2 ADI 1 W 1 SNGL 0 W 0 IC4 x W x x RSV! x x W Register Description This register is the first initialization register of the Slave 2 controller. Bit Definitions Bit 7-5 Name Reserved Function Reserved This bit field should be written to 0 for normal system operation. This I/O address changes functions when read. See the programming notes for this register (S2PICICW1) on page 12-40. Initialization Control Word 1 Select Software must set this bit to 1 when writing this address (Port 0024h) to access this register (S2PICICW1). 0 = The write does not access this register (S2PICICW1). Instead, either the S2PICOCW2 register (see page 12-41) or the S2PICOCW3 register (see page 12-43) is written, depending on the state of bit 3. 1 = The write accesses this register (S2PICICW1). Subsequent writes to Port 0025h access additional initialization control words. See the programming notes for this register (S2PICICW1) on page 12-40. 4 SLCT_ICW1 3 LTIM Level-Triggered Interrupt Mode This bit is the global interrupt mode selection for the Slave 2 PIC. 0 = Edge-sensitive interrupt request detection 1 = Level-sensitive interrupt request detection If the S2_GINT_MODE bit in the PICICR register is set (see page 12-4), the LTIM bit determines the interrupt mode for the Slave 2 PIC channels. If the S2_GINT_MODE bit is cleared, the Slave 2 LTIM bit has no meaning, and the Slave 2 PIC channel modes can be programmed individually via the SL2PICMODE register (see page 12-9). 2 ADI Address Interval 0 = Interrupt vectors are separated by eight locations. 1 = Interrupt vectors are separated by four locations. In the ELANSC520 microcontroller design, this bit is internally fixed to 1. ElanTMSC520 Microcontroller Register Set Manual 12-39 Programmable Interrupt Controller Registers Bit 1 Name SNGL Function Single PIC 0 = Cascade mode; S2PICICW3 is expected. 1 = Single PIC in the system; S2PICICW3 is not expected (not valid in the ELANSC520 microcontroller). In the ELANSC520 microcontroller design, this bit is internally fixed to 0. Because this bit is internally fixed to 0, software must always write the S2PICICW3 register after writing S1PICICW2. See the programming notes on this page for details. 0 IC4 Initialization Control Word 4 Software uses this bit to indicate whether it intends to explicitly program the S2PICICW4 register (see page 12-47) after writing to the S2PICICW3 register (see page 12-46). See the programming notes on this page for details. 0 = The S2PICICW4 register is initialized internally when this register (S2PICICW1) is written. The PIC does not expect software to write to the S2PICICW4 register. 1 = The S2PICICW4 register is not initialized by the write to this register (S2PICICW1). Software is expected to initialize the S2PICICW4 register after writing to the S2PICICW3 register. Programming Notes The PIC's initialization control word (S2PICICWx) registers 1-4 must be programmed in sequence. Writing to Port 0024h with bit 4 = 1 causes the S2PICICW1 register to be written and also resets the PIC's internal state machine and the internal S2PICICWx register pointer. Then, S2PICICWx registers 2-4 can be programmed by sequential writes to Port 0025h. Each time Port 0025h is written to (following the write to S2PICICW1), the internal register pointer points to the next S2PICICWx register. S2PICICW1 and S2PICICW2 must always be programmed. Also, the S2PICICW3 register must always be programmed in this design because the SNGL bit in S2PICICW1 is internally fixed to 0. The S2PICICW4 register is skipped if the IC4 bit in S2PICICW1 is 0. If the S5 bit in the MPICICW3 register is cleared (see page 12-33), then the Slave 2 controller is bypassed and programming this register does not affect other registers. I/O Port 0024h provides access to different Slave 2 PIC registers based on the data that is written. Table 12-6 provides a summary of bit patterns to write for access to each register. Table 12-6 Slave 2 PIC I/O Port 0024h Access Summary Bits 7 x 0 0 0 0 6 x x 0 0 0 5 x x 0 0 0 4 0 0 0 0 1 3 0 1 1 1 x 2 x x 0 0 x 1 x 0 1 1 x 0 x x 0 1 x Port 0024h Register Written S2PICOCW2 (page 12-41) S2PICOCW3 (page 12-43) S2PICOCW3 S2PICOCW3 S2PICICW1 (page 12-39) Next Port 0024h Read Returns -- -- S2PICIR (page 12-37) S2PICISR (page 12-38) -- 12-40 ElanTMSC520 Microcontroller Register Set Manual Programmable Interrupt Controller Registers Slave 2 PIC Operation Control Word 2 (S2PICOCW2) Direct-Mapped I/O Address 0024h 7 Bit Reset R/W 6 R_SL_EOI[2-0] 5 4 SLCT_ ICW1 3 IS_OCW3 x W 2 1 LS[2-0] 0 x x W x x W x x W x Register Description This register provides control for various interrupt priority and end-of-interrupt (EOI) modes. It also controls write access for this register (S2PICOCW2) and for the S2PICOCW3 and S2PICICW1 registers (see page 12-43 and page 12-39). Bit Definitions Bit 7-5 Name R_SL_EOI[2-0] Function Interrupt Request EOI and Priority Rotation Controls 000 = Rotate in auto EOI mode (clear) 001 = Nonspecific EOI 010 = No operation 011 = Specific EOI 100 = Rotate in auto EOI mode (set) 101 = Rotate on nonspecific EOI command 110 = Set priority command 111 = Rotate on specific EOI command 4 SLCT_ICW1 Initialization Control Word 1 Select Software must clear this bit to 0 when writing this address (Port 0024h) to access either this register (S2PICOCW2) or the S2PICOCW3 register. 0 = The write accesses either this register (S2PICOCW2) or the S2PICOCW3 register (see page 12-43), depending on the state of bit 3. 1 = The write accesses the S2PICICW1 register (see page 12-39). Access is OCW3 Software must clear this bit (IS_OCW3) and clear SLCT_ICW1 when writing this address (Port 0024h) to access this register (S2PICOCW2). 0 = The write accesses this register (S2PICOCW2) if the SLCT_ICW1 bit is cleared. 1 = The write accesses the S2PICOCW3 register (see page 12-43) if the SLCT_ICW1 bit is cleared. 3 IS_OCW3 2-0 LS[2-0] Specific EOI Level Select Interrupt level that is acted upon when the SL bit = 1 (see bits 7-5 of this register): 000 = IR0 001 = IR1 010 = IR2 011 = IR3 100 = IR4 101 = IR5 110 = IR6 111 = IR7 ElanTMSC520 Microcontroller Register Set Manual 12-41 Programmable Interrupt Controller Registers Programming Notes If the S5 bit in the MPICICW3 register is cleared (see page 12-33), then the Slave 2 controller is bypassed and programming this register does not affect other registers. I/O Port 0024h provides access to different Slave 2 PIC registers based on the data that is written. Table 12-7 provides a summary of bit patterns to write for access to each register. Table 12-7 Slave 2 PIC I/O Port 0024h Access Summary (Same as Table 12-6) Bits 7 x 0 0 0 0 6 x x 0 0 0 5 x x 0 0 0 4 0 0 0 0 1 3 0 1 1 1 x 2 x x 0 0 x 1 x 0 1 1 x 0 x x 0 1 x Port 0024h Register Written S2PICOCW2 (page 12-41) S2PICOCW3 (page 12-43) S2PICOCW3 S2PICOCW3 S2PICICW1 (page 12-39) Next Port 0024h Read Returns -- -- S2PICIR (page 12-37) S2PICISR (page 12-38) -- 12-42 ElanTMSC520 Microcontroller Register Set Manual Programmable Interrupt Controller Registers Slave 2 PIC Operation Control Word 3 (S2PICOCW3) Direct-Mapped I/O Address 0024h 7 Bit Reset R/W 6 5 4 SLCT_ ICW1 x W 3 IS_OCW3 x W 2 P x W 1 0 Reserved x RSV! ESMM_SMM[1-0] 1 W x RR_RIS[1-0] x W x Register Description This register controls the PIC's mask and poll modes. It also controls read access for the S2PICIR and S2PICISR registers (see page 12-37 and page 12-38), and write access for this register (S2PICOCW3) and for the S2PICOCW2 and S2PICICW1 registers (see page 12-41 and page 12-39). Bit Definitions Bit 7 Name Reserved Function Reserved This bit field should be written to 0 for normal system operation. This I/O address changes functions when read. See the programming notes for this register (S2PICOCW3) on page 12-44. Special Mask Mode 00 = No operation 01 = No operation 10 = Reset special mask 11 =Set special mask 6-5 ESMM_SMM [1-0] 4 SLCT_ICW1 Initialization Control Word 1 Select Software must clear this bit to 0 when writing this address (Port 0024h) to access either this register (S2PICOCW3) or the S2PICOCW2 register. 0 = The write accesses either this register (S2PICOCW3) or the S2PICOCW2 register (see page 12-41), depending on the state of bit 3. 1 = The write accesses the S2PICICW1 register (see page 12-39). Access is OCW3 Software must set this bit (IS_OCW3) and clear SLCT_ICW1 when writing this address (Port 0024h) to access this register (S2PICOCW3). 0 = The write accesses the S2PICOCW2 register (see page 12-41) if the SLCT_ICW1 bit is cleared. 1 = The write accesses this register (S2PICOCW3) if the SLCT_ICW1 bit is cleared. PIC Poll Command A system designer can choose to use the PIC in a non-interrupting mode. In this case, the interrupt controller can be polled for the status of pending interrupts. To support this mode of operation, the PIC supports a special poll command that is invoked by setting this bit. 0 = Not poll command 1 = Poll command Status Register Select 00 = No change from last state 01 = No change from last state 10 = Next Port 0024h read returns the S2PICIR register's contents (see page 12-37). 11 = Next Port 0024h read returns in the S2PICISR register's contents (see page 12-38). 3 IS_OCW3 2 P 1-0 RR_RIS[1-0] ElanTMSC520 Microcontroller Register Set Manual 12-43 Programmable Interrupt Controller Registers Programming Notes If the S5 bit in the MPICICW3 register is cleared (see page 12-33), then the Slave 2 controller is bypassed and programming this register does not affect other registers. I/O Port 0024h provides access to different Slave 2 PIC registers based on the data that is written. Table 12-8 provides a summary of bit patterns to write for access to each register. Table 12-8 Slave 2 PIC I/O Port 0024h Access Summary (Same as Table 12-6) Bits 7 x 0 0 0 0 6 x x 0 0 0 5 x x 0 0 0 4 0 0 0 0 1 3 0 1 1 1 x 2 x x 0 0 x 1 x 0 1 1 x 0 x x 0 1 x Port 0024h Register Written S2PICOCW2 (page 12-41) S2PICOCW3 (page 12-43) S2PICOCW3 S2PICOCW3 S2PICICW1 (page 12-39) Next Port 0024h Read Returns -- -- S2PICIR (page 12-37) S2PICISR (page 12-38) -- 12-44 ElanTMSC520 Microcontroller Register Set Manual Programmable Interrupt Controller Registers Slave 2 PIC Initialization Control Word 2 (S2PICICW2) Direct-Mapped I/O Address 0025h 7 Bit Reset R/W 6 5 T7-T3 4 3 2 1 A10-A8 0 x x x W x x x x W x Register Description This register is the second initialization register of the Slave 2 controller. Bit Definitions Bit 7-3 Name T7-T3 Function Bits 7-3 of Base Interrupt Vector Number for this PIC The PIC concatenates the T7-T3 bit field value to the 3-bit PIC interrupt request level (in the bit 2-0 position) to form the interrupt vector. For example, if bits T7-T3 are programmed to 11110b, the IR0 channel generates an interrupt F0h vector. A10-A8 of Interrupt Vector Software should write these to 0. 2-0 A10-A8 Programming Notes If the S5 bit in the MPICICW3 register is cleared (see page 12-33), then the Slave 2 controller is bypassed and programming this register does not affect other registers. The PIC's initialization control word (S2PICICWx) registers 1-4 must be programmed in sequence. Writing to Port 0024h with bit 4 = 1 causes the S2PICICW1 register to be written and also resets the PIC's internal state machine and the internal S2PICICWx register pointer. Then, S2PICICWx registers 2-4 can be programmed by sequential writes to Port 0025h. Each time Port 0025h is written to (following the write to S2PICICW1), the internal register pointer points to the next S2PICICWx register. S2PICICW1 and S2PICICW2 must always be programmed. Also, the S2PICICW3 register must always be programmed in this design because the SNGL bit in S2PICICW1 is internally fixed to 0. The S2PICICW4 register is skipped if the IC4 bit in S2PICICW1 is 0. ElanTMSC520 Microcontroller Register Set Manual 12-45 Programmable Interrupt Controller Registers Slave 2 PIC Initialization Control Word 3 (S2PICICW3) Direct-Mapped I/O Address 0025h 7 Bit Reset R/W 6 5 Reserved 4 3 2 1 ID2-ID0 0 x x x RSV! x x 1 0 W 1 Register Description This register is the third initialization register of the Slave 2 controller. Bit Definitions Bit 7-3 2-0 Name Reserved ID2-ID0 Function Reserved This bit field should be written to 0 for normal system operation. This bit field is write-only. Slave 2 PIC ID 2-0 These bits contain the binary Slave 2 PIC ID (000b-111b) that the PIC responds to on the cascade bus. In the ELANSC520 microcontroller, these bits are internally fixed to 101b. Programming Notes The PIC's initialization control word (S2PICICWx) registers 1-4 must be programmed in sequence. Writing to Port 0024h with bit 4 = 1 causes the S2PICICW1 register to be written and also resets the PIC's internal state machine and the internal S2PICICWx register pointer. Then, S2PICICWx registers 2-4 can be programmed by sequential writes to Port 0025h. Each time Port 0025h is written to (following the write to S2PICICW1), the internal register pointer points to the next S2PICICWx register. S2PICICW1 and S2PICICW2 must always be programmed. Also, the S2PICICW3 register must always be programmed in this design because the SNGL bit in S2PICICW1 is internally fixed to 0. The S2PICICW4 register is skipped if the IC4 bit in S2PICICW1 is 0. If the S5 bit is set in the MPICICW3 register (see page 12-33), a write to this register (S2PICICW3) is always expected in the ELANSC520 microcontroller because the SNGL bit is fixed to 0 in the S2PICICW1 register (page 12-40). If the S5 bit is cleared in the MPICICW3 register, then the Slave 2 controller is bypassed and the value of this register (S2PICICW3) has no effect. 12-46 ElanTMSC520 Microcontroller Register Set Manual Programmable Interrupt Controller Registers Slave 2 PIC Initialization Control Word 4 (S2PICICW4) Direct-Mapped I/O Address 0025h 7 Bit Reset R/W 6 Reserved 5 4 SFNM 3 2 1 AEOI 0 W 0 PM 1 W BUF_M/S[1-0] 0 W 0 x x RSV! x x W Register Description This register is the fourth initialization register of the Slave 2 controller. Bit Definitions Bit 7-5 4 Name Reserved SFNM Function Reserved This bit field should be written to 0 for normal system operation. This bit field is write-only. Special Fully Nested Mode Enable 0 = Normal nested mode 1 = Special fully nested mode Buffered Mode and Master/Slave Select 00 = Non buffered mode 01 = Non buffered mode 10 = Buffered mode/Slave 11 = Buffered mode/Master In the ELANSC520 microcontroller, these bits are internally fixed to 00b. Automatic EOI Mode 0 = Normal EOI: the interrupt handler must send an End of Interrupt command to the PIC(s). 1 = Auto EOI: the EOI is automatically performed after the second interrupt acknowledge signal from the CPU. In the ELANSC520 microcontroller, this bit is internally fixed to 0. The Slave 1 PIC and Slave 2 PIC do not support automatic EOI mode. Microprocessor Mode 0 = 8080/8085 mode 1 = 8086 mode In the ELANSC520 microcontroller design, this bit is internally fixed to 1. 3-2 BUF_M/S[1-0] 1 AEOI 0 PM Programming Notes The PIC's initialization control word (S2PICICWx) registers 1-4 must be programmed in sequence. Writing to Port 0024h with bit 4 = 1 causes the S2PICICW1 register to be written and also resets the PIC's internal state machine and the internal S2PICICWx register pointer. Then, S2PICICWx registers 2-4 can be programmed by sequential writes to Port 0025h. Each time Port 0025h is written to (following the write to S2PICICW1), the internal register pointer points to the next S2PICICWx register. S2PICICW1 and S2PICICW2 must always be programmed. Also, the S2PICICW3 register must always be programmed in this design because the SNGL bit in S2PICICW1 is internally fixed to 0. The S2PICICW4 register is skipped if the IC4 bit in S2PICICW1 is 0. Software is expected to initialize this register (S2PICICW4) if the IC4 bit is set in the S2PICICW1 register (see page 12-40). If the IC4 bit is cleared, the ELANSC520 microcontroller uses 01h for the value of this register (S2PICICW4). However, if the S5 bit in the MPICICW3 register is cleared (see page 12-33), then the Slave 2 controller is bypassed and the value of this register (S2PICICW4) has no effect. ElanTMSC520 Microcontroller Register Set Manual 12-47 Programmable Interrupt Controller Registers Slave 2 PIC Interrupt Mask (S2PICINTMSK) Direct-Mapped I/O Address 0025h 7 Bit Reset R/W 6 IM6 x R/W 5 IM5 x R/W 4 IM4 x R/W 3 IM3 x R/W 2 IM2 x R/W 1 IM1 x R/W 0 IM0 x R/W IM7 x R/W Register Description This register provides masking of individual interrupt requests for the Slave 2 controller. This register is also known as Operation Control Word 1 in other PC/AT-compatible designs. Bit Definitions Bit 7 Name IM7 Function IR7 Mask 0 = Unmask IR7 1 = Mask IR7 IR6 Mask 0 = Unmask IR6 1 = Mask IR6 IR5 Mask 0 = Unmask IR5 1 = Mask IR5 IR4 Mask 0 = Unmask IR4 1 = Mask IR4 IR3 Mask 0 = Unmask IR3 1 = Mask IR3 IR2 Mask 0 = Unmask IR2 1 = Mask IR2 IR1 Mask 0 = Unmask IR1 1 = Mask IR1 IR0 Mask 0 = Unmask IR0 1 = Mask IR0 6 IM6 5 IM5 4 IM4 3 IM3 2 IM2 1 IM1 0 IM0 Programming Notes If the S5 bit in the MPICICW3 register is cleared (see page 12-33), then the Slave 2 controller is bypassed and the value of this register (S2PICINTMSK) has no effect. This register (S2PICINTMSK) cannot be accessed during a Slave 2 PIC initialization control sequence, which is initiated by setting the SLCT_ICW1 bit in the S2PICICW1 register (see page 12-39). When the S2PICICWx register initialization sequence is not in effect, any read or write of Port 0025h accesses the S2PICINTMSK register. 12-48 ElanTMSC520 Microcontroller Register Set Manual Programmable Interrupt Controller Registers Slave 1 PIC Interrupt Request (S1PICIR) Direct-Mapped I/O Address 00A0h 7 Bit Reset R/W 6 IR6 x R 5 IR5 x R 4 IR4 x R 3 IR3 x R 2 IR2 x R 1 IR1 x R 0 IR0 x R IR7 x R Register Description This register provides a real-time status of the interrupt request inputs to the Slave 1 PIC. This register latches all incoming interrupt requests and provides individual status of the requests to be acknowledged. Bit Definitions Bit 7 Name IR7 Function Interrupt Request 7 0 = The IR7 input to the Slave 1 PIC is not asserted. 1 = The IR7 input is asserted. Interrupt Request 6 0 = The IR6 input to the Slave 1 PIC is not asserted. 1 = The IR6 input is asserted. Interrupt Request 5 0 = The IR5 input to the Slave 1 PIC is not asserted. 1 = The IR5 input is asserted. Interrupt Request 4 0 = The IR4 input to the Slave 1 PIC is not asserted. 1 = The IR4 input is asserted. Interrupt Request 3 0 = The IR3 input to the Slave 1 PIC is not asserted. 1 = The IR3 input is asserted. Interrupt Request 2 0 = The IR2 input to the Slave 1 PIC is not asserted. 1 = The IR2 input is asserted. Interrupt Request 1 0 = The IR1 input to the Slave 1 PIC is not asserted. 1 = The IR1 input is asserted. Interrupt Request 0 0 = The IR0 input to the Slave 1 PIC is not asserted. 1 = The IR0 input is asserted. 6 IR6 5 IR5 4 IR4 3 IR3 2 IR2 1 IR1 0 IR0 Programming Notes This register (S1PICIR) is accessed by first writing a value of 0Ah to Port 00A0h followed by a read-back from Port 00A0h. If the S2 bit in the MPICICW3 register is cleared (see page 12-34), then the Slave 1 controller is bypassed and any interrupt requests latched in this register (S1PICIR) are not propagated to the CPU. ElanTMSC520 Microcontroller Register Set Manual 12-49 Programmable Interrupt Controller Registers Slave 1 PIC In-Service (S1PICISR) Direct-Mapped I/O Address 00A0h 7 Bit Reset R/W 6 IS6 x R 5 IS5 x R 4 IS4 x R 3 IS3 x R 2 IS2 x R 1 IS1 x R 0 IS0 x R IS7 x R Register Description This register indicates the Slave 1 interrupt priority levels that are being serviced. Bit Definitions Bit 7 Name IS7 Function Interrupt Request 7 In-Service 0 = Interrupt request 7 is not being serviced. 1 = Interrupt request 7 is being serviced. Interrupt Request 6 In-Service 0 = Interrupt request 6 is not being serviced. 1 = Interrupt request 6 is being serviced. Interrupt Request 5 In-Service 0 = Interrupt request 5 is not being serviced. 1 = Interrupt request 5 is being serviced. Interrupt Request 4 In-Service 0 = Interrupt request 4 is not being serviced. 1 = Interrupt request 4 is being serviced. Interrupt Request 3 In-Service 0 = Interrupt request 3 is not being serviced. 1 = Interrupt request 3 is being serviced. Interrupt Request 2 In-Service 0 = Interrupt request 2 is not being serviced. 1 = Interrupt request 2 is being serviced. Interrupt Request 1 In-Service 0 = Interrupt request 1 is not being serviced. 1 = Interrupt request 1 is being serviced. Interrupt Request 0 In-Service 0 = Interrupt request 0 is not being serviced. 1 = Interrupt request 0 is being serviced. 6 IS6 5 IS5 4 IS4 3 IS3 2 IS2 1 IS1 0 IS0 Programming Notes This register (S1PICISR) is accessed by writing a value of 0Bh to Port 00A0h followed by a read back from Port 00A0h. If the S2 bit in the MPICICW3 register is cleared (see page 12-34), then the Slave 1 controller is bypassed and interrupt requests latched are not serviced. 12-50 ElanTMSC520 Microcontroller Register Set Manual Programmable Interrupt Controller Registers Slave 1 PIC Initialization Control Word 1 (S1PICICW1) Direct-Mapped I/O Address 00A0h 7 Bit Reset R/W 6 Reserved 5 4 SLCT_ ICW1 3 LTIM x W 2 ADI 1 W 1 SNGL 0 W 0 IC4 x W x x RSV! x x W Register Description This register is the first initialization register of the Slave 1 controller. Bit Definitions Bit 7-5 Name Reserved Function Reserved This bit field should be written to 0 for normal system operation. This I/O address changes functions when read. See the programming notes for this register (S1PICICW1) on page 12-52. Initialization Control Word 1 Select Software must set this bit to 1 when writing this address (Port 00A0h) to access this register (S1PICICW1). 0 = The write does not access this register (S1PICICW1). Instead, either the S1PICOCW2 register (see page 12-53) or the S1PICOCW3 register (see page 12-55) is written, depending on the state of bit 3. 1 = The write accesses this register (S1PICICW1). Subsequent writes to Port 00A1h access additional initialization control words. See the programming notes for this register (S1PICICW1) on page 12-52. 4 SLCT_ICW1 3 LTIM Level-Triggered Interrupt Mode This bit is the global interrupt mode selection for the Slave 1 PIC. 0 = Edge-sensitive interrupt request detection 1 = Level-sensitive interrupt request detection If the S1_GINT_MODE bit in the PICICR register is set (see page 12-5), the LTIM bit determines the interrupt mode for the Slave 1 PIC channels. If the S1_GINT_MODE bit is cleared, the Slave 1 LTIM bit has no meaning, and the Slave 1 PIC channel modes can be programmed individually via the SL1PICMODE register (see page 12-8). 2 ADI Address Interval 0 = Interrupt vectors are separated by eight locations. 1 = Interrupt vectors are separated by four locations. In the ELANSC520 microcontroller design, this PC/AT-compatible bit is internally fixed to 1. ElanTMSC520 Microcontroller Register Set Manual 12-51 Programmable Interrupt Controller Registers Bit 1 Name SNGL Function Single PIC 0 = Cascade mode; S1PICICW3 is expected. 1 = Single PIC in the system; S1PICICW3 is not expected (not valid in the ELANSC520 microcontroller). In the ELANSC520 microcontroller design, this bit is internally fixed to 0. Because this bit is internally fixed to 0, software must always write the S1PICICW3 register after writing S1PICICW2. See the programming notes on this page for details. 0 IC4 Initialization Control Word 4 Software uses this bit to indicate whether it intends to explicitly program the S1PICICW4 register (see page 12-59) after writing to the S1PICICW3 register (see page 12-58). See the programming notes on this page for details. 0 = The S1PICICW4 register is initialized internally when this register (S1PICICW1) is written. The PIC does not expect software to write to the S1PICICW4 register. 1 = The S1PICICW4 register is not initialized by the write to this register (S1PICICW1). Software is expected to initialize the S1PICICW4 register after writing to the S1PICICW3 register. Programming Notes The PIC's initialization control word (S1PICICWx) registers 1-4 must be programmed in sequence. Writing to Port 00A0h with bit 4 = 1 causes the S1PICICW1 register to be written and also resets the PIC's internal state machine and the internal S1PICICWx register pointer. Then, S1PICICWx registers 2-4 can be programmed by sequential writes to Port 00A1h. Each time Port 00A1h is written to (following the write to S1PICICW1), the internal register pointer points to the next S1PICICWx register. S1PICICW1 and S1PICICW2 must always be programmed. Also, the S1PICICW3 register must always be programmed in this design because the SNGL bit in S1PICICW1 is internally fixed to 0. The S1PICICW4 register is skipped if the IC4 bit in S1PICICW1 is 0. If the S2 bit in the MPICICW3 register is cleared (see page 12-34), then the Slave 1 controller is bypassed and programming this register does not affect other registers. I/O Port 00A0h provides access to different Slave 1 PIC registers based on the data that is written. Table 12-9 provides a summary of bit patterns to write for access to each register. Table 12-9 Slave 1 PIC I/O Port 00A0h Access Summary Bits 7 x 0 0 0 0 6 x x 0 0 0 5 x x 0 0 0 4 0 0 0 0 1 3 0 1 1 1 x 2 x x 0 0 x 1 x 0 1 1 x 0 x x 0 1 x Port 00A0h Register Written S1PICOCW2 (page 12-53) S1PICOCW3 (page 12-55) S1PICOCW3 S1PICOCW3 S1PICICW1 (page 12-51) Next Port 00A0h Read Returns -- -- S1PICIR (page 12-49) S1PICISR (page 12-50) -- 12-52 ElanTMSC520 Microcontroller Register Set Manual Programmable Interrupt Controller Registers Slave 1 PIC Operation Control Word 2 (S1PICOCW2) Direct-Mapped I/O Address 00A0h 7 Bit Reset R/W 6 R_SL_EOI[1-0] 5 4 SLCT_ ICW1 3 IS_OCW3 x W 2 1 LS[2-0] 0 x x W x x W x x W x Register Description This register provides control for various interrupt priority and end-of-interrupt (EOI) modes. It also controls write access for this register (S1PICOCW2) and for the S1PICOCW3 and S1PICICW1 registers (see page 12-55 and page 12-51). Bit Definitions Bit 7-5 Name R_SL_EOI[1-0] Function Interrupt Request EOI and Priority Rotation Controls 000 = Rotate in auto EOI mode (clear) 001 = Nonspecific EOI 010 = No operation 011 = Specific EOI 100 = Rotate in auto EOI mode (set) 101 = Rotate on nonspecific EOI command 110 = Set priority command 111 = Rotate on specific EOI command 4 SLCT_ICW1 Initialization Control Word 1 Select Software must clear this bit to 0 when writing this address (Port 00A0h) to access either this register (S1PICOCW2) or the S1PICOCW3 register. 0 = The write accesses either this register (S1PICOCW2) or the S1PICOCW3 register (see page 12-55), depending on the state of bit 3. 1 = The write accesses the S1PICICW1 register (see page 12-51). Access is OCW3 Software must clear this bit (IS_OCW3) and clear SLCT_ICW1 when writing this address (Port 00A0h) to access this register (S1PICOCW2). 0 = The write accesses this register (S1PICOCW2) if the SLCT_ICW1 bit is cleared. 1 = The write accesses the S1PICOCW3 register (see page 12-55) if the SLCT_ICW1 bit is cleared. 3 IS_OCW3 ElanTMSC520 Microcontroller Register Set Manual 12-53 Programmable Interrupt Controller Registers Bit 2-0 Name LS[2-0] Function Specific EOI Level Select Interrupt level that is acted upon when the SL bit = 1 (see bits 7-5] below: 000 = IR0 001 = IR1 010 = IR2 011 = IR3 100 = IR4 101 = IR5 110 = IR6 111 = IR7 Programming Notes If the S2 bit in the MPICICW3 register is cleared (see page 12-34), then the Slave 1 controller is bypassed and programming this register does not affect other registers. I/O Port 00A0h provides access to different Slave 1 PIC registers based on the data that is written. Table 12-10 provides a summary of bit patterns to write for access to each register. Table 12-10 Slave 1 PIC I/O Port 00A0h Access Summary (Same as Table 12-9) Bits 7 x 0 0 0 0 6 x x 0 0 0 5 x x 0 0 0 4 0 0 0 0 1 3 0 1 1 1 x 2 x x 0 0 x 1 x 0 1 1 x 0 x x 0 1 x Port 00A0h Register Written S1PICOCW2 (page 12-53) S1PICOCW3 (page 12-55) S1PICOCW3 S1PICOCW3 S1PICICW1 (page 12-51) Next Port 00A0h Read Returns -- -- S1PICIR (page 12-49) S1PICISR (page 12-50) -- 12-54 ElanTMSC520 Microcontroller Register Set Manual Programmable Interrupt Controller Registers Slave 1 PIC Operation Control Word 3 (S1PICOCW3) Direct-Mapped I/O Address 00A0h 7 Bit Reset R/W 6 5 4 SLCT_ ICW1 x W 3 IS_OCW3 x W 2 P x W 1 0 Reserved x RSV! ESMM_SMM[1-0] 1 W x RR_RIS[1-0] x W x Register Description This register controls the PIC's mask and poll modes. It also controls read access for the S1PICIR and S1PICISR registers (see page 12-49 and page 12-50), and write access for this register (S1PICOCW3) and for the S1PICOCW2 and S1PICICW1 registers (see page 12-53 and page 12-51). Bit Definitions Bit 7 Name Reserved Function Reserved This bit field should be written to 0 for normal system operation. This I/O address changes functions when read. See the programming notes for this register (S1PICICW1) on page 12-56. Special Mask Mode 00 = No operation 01 = No operation 10 = Reset special mask 11 =Set special mask 6-5 ESMM_SMM [1-0] 4 SLCT_ICW1 Initialization Control Word 1 Select Software must clear this bit to 0 when writing this address (Port 00A0h) to access either this register (S1PICOCW3) or the S1PICOCW2 register. 0 = The write accesses either this register (S1PICOCW3) or the S1PICOCW2 register (see page 12-53), depending on the state of bit 3. 1 = The write accesses the S1PICICW1 register (see page 12-51). Access is OCW3 Software must set this bit (IS_OCW3) and clear SLCT_ICW1 when writing this address (Port 00A0h) to access this register (S1PICOCW3). 0 = The write accesses the S1PICOCW2 register (see page 12-53) if the SLCT_ICW1 bit is cleared. 1 = The write accesses this register (S1PICOCW3) if the SLCT_ICW1 bit is cleared. PIC Poll Command A system designer can choose to use the PIC in a non-interrupting mode. In this case, the interrupt controller can be polled for the status of pending interrupts. To support this PC/ATincompatible mode of operation, the PIC supports a special poll command that is invoked by setting this bit. 0 = Not poll command 1 = Poll command Status Register Select 00 = No change from last state 01 = No change from last state 10 = Next Port 00A0h read returns the S1PICIR register's contents (see page 12-49). 11 = Next Port 00A0h read returns the S1PICISR register's contents (see page 12-50). 3 IS_OCW3 2 P 1-0 RR_RIS[1-0] ElanTMSC520 Microcontroller Register Set Manual 12-55 Programmable Interrupt Controller Registers Programming Notes If the S2 bit in the MPICICW3 register is cleared (see page 12-34), then the Slave 1 controller is bypassed and programming this register does not affect other registers. I/O Port 00A0h provides access to different Slave 1 PIC registers based on the data that is written. Table 12-11 provides a summary of bit patterns to write for access to each register. Table 12-11 Slave 1 PIC I/O Port 00A0h Access Summary (Same as Table 12-9) Bits 7 x 0 0 0 0 6 x x 0 0 0 5 x x 0 0 0 4 0 0 0 0 1 3 0 1 1 1 x 2 x x 0 0 x 1 x 0 1 1 x 0 x x 0 1 x Port 00A0h Register Written S1PICOCW2 (page 12-53) S1PICOCW3 (page 12-55) S1PICOCW3 S1PICOCW3 S1PICICW1 (page 12-51) Next Port 00A0h Read Returns -- -- S1PICIR (page 12-49) S1PICISR (page 12-50) -- 12-56 ElanTMSC520 Microcontroller Register Set Manual Programmable Interrupt Controller Registers Slave 1 PIC Initialization Control Word 2 (S1PICICW2) Direct-Mapped I/O Address 00A1h 7 Bit Reset R/W 6 5 T7-T3 4 3 2 1 A10-A8 0 x x x W x x x x W x Register Description This register is the second initialization register of the Slave 1 controller. Bit Definitions Bit 7-3 Name T7-T3 Function Bits 7-3 of Base Interrupt Vector Number for this PIC The PIC concatenates the T7-T3 bit field value to the 3-bit PIC interrupt request level (in the bit 2-0 position) to form the interrupt vector. For example, in a PC/AT-compatible system, bits T7-T3 for the Master PIC are programmed to 00001b so the Master PIC IR0 channel generates an interrupt 08h vector (PC/AT IRQ0); and bits T7-T3 for the Slave 1 PIC are programmed to 01110b so the Slave 1 PIC IR0 channel generates an interrupt 70h (PC/AT IRQ8). A10-A8 of Interrupt Vector This bit field should always be written to 0 for normal operation. (It is always 0 in a PC/AT-compatible system.) 2-0 A10-A8 Programming Notes If the S2 bit in the MPICICW3 register is cleared (see page 12-34), then the Slave 1 controller is bypassed and programming this register does not affect other registers. The PIC's initialization control word (S1PICICWx) registers 1-4 must be programmed in sequence. Writing to Port 00A0h with bit 4 = 1 causes the S1PICICW1 register to be written and also resets the PIC's internal state machine and the internal S1PICICWx register pointer. Then, S1PICICWx registers 2-4 can be programmed by sequential writes to Port 00A1h. Each time Port 00A1h is written to (following the write to S1PICICW1), the internal register pointer points to the next S1PICICWx register. S1PICICW1 and S1PICICW2 must always be programmed. Also, the S1PICICW3 register must always be programmed in this design because the SNGL bit in S1PICICW1 is internally fixed to 0. The S1PICICW4 register is skipped if the IC4 bit in S1PICICW1 is 0. ElanTMSC520 Microcontroller Register Set Manual 12-57 Programmable Interrupt Controller Registers Slave 1 PIC Initialization Control Word 3 (S1PICICW3) Direct-Mapped I/O Address 00A1h 7 Bit Reset R/W 6 5 Reserved 4 3 2 1 ID2-ID0 0 x x x RSV! x x 0 1 W 0 Register Description This register is the third initialization register of the Slave 1 controller. Bit Definitions Bit 7-3 2-0 Name Reserved ID2-ID0 Function Reserved This bit field should be written to 0 for normal system operation. This bit field is write-only. Slave 1 PIC ID 2-0 These bits contain the binary Slave 1PIC ID (000b-111b) that the PIC responds to on the cascade bus. In the ELANSC520 microcontroller design, these bits are internally fixed to 010b. Programming Notes The PIC's initialization control word (S1PICICWx) registers 1-4 must be programmed in sequence. Writing to Port 00A0h with bit 4 = 1 causes the S1PICICW1 register to be written and also resets the PIC's internal state machine and the internal S1PICICWx register pointer. Then, S1PICICWx registers 2-4 can be programmed by sequential writes to Port 00A1h. Each time Port 00A1h is written to (following the write to S1PICICW1), the internal register pointer points to the next S1PICICWx register. S1PICICW1 and S1PICICW2 must always be programmed. Also, the S1PICICW3 register must always be programmed in this design because the SNGL bit in S1PICICW1 is internally fixed to 0. The S1PICICW4 register is skipped if the IC4 bit in S1PICICW1 is 0. If the S2 bit in the MPICICW3 register is cleared (see page 12-34), a write to this register (S1PICICW3) is always expected in the ELANSC520 microcontroller because the SNGL bit is fixed to 0 in the S1PICICW1 register (page 12-52). If the S2 bit in the MPICICW3 register is cleared, then the Slave 1 controller is bypassed and the value of this register (S1PICICW3) has no effect. 12-58 ElanTMSC520 Microcontroller Register Set Manual Programmable Interrupt Controller Registers Slave 1 PIC Initialization Control Word 4 (S1PICICW4) Direct-Mapped I/O Address 00A1h 7 Bit Reset R/W 6 Reserved 5 4 SFNM 3 2 1 AEOI 0 W 0 PM 1 W BUF_M/S[1-0] 0 W 0 x x RSV! x x W Register Description This register is the fourth initialization register of the Slave 1 controller. Bit Definitions Bit 7-5 4 Name Reserved SFNM Function Reserved This bit field should be written to 0 for normal system operation. This bit field is write-only. Special Fully Nested Mode Enable 0 = Normal nested mode 1 = Special fully nested mode For PC/AT compatibility, this bit should be programmed as 0. Buffered Mode and Master/Slave Select 00 = Non buffered mode 01 = Non buffered mode 10 = Buffered mode/Slave 11 = Buffered mode/Master In the ELANSC520 microcontroller, these PC/AT-compatible bits are internally fixed to 00b. Automatic EOI Mode 0 = Normal EOI: the interrupt handler must send an End of Interrupt command to the PIC(s). 1 = Auto EOI: the EOI is automatically performed after the second interrupt acknowledge signal from the CPU. In the ELANSC520 microcontroller, this bit is internally fixed to 0. The Slave 1 PIC and Slave 2 PIC do not support automatic EOI mode. 3-2 BUF_M/S[1-0] 1 AEOI 0 PM Microprocessor Mode 0 = 8080/8085 mode 1 = 8086 mode In the ELANSC520 microcontroller design, this PC/AT-compatible bit is internally fixed to 1. Programming Notes The PIC's initialization control word (S1PICICWx) registers 1-4 must be programmed in sequence. Writing to Port 00A0h with bit 4 = 1 causes the S1PICICW1 register to be written and also resets the PIC's internal state machine and the internal S1PICICWx register pointer. Then, S1PICICWx registers 2-4 can be programmed by sequential writes to Port 00A1h. Each time Port 00A1h is written (following the write to S1PICICW1), the internal register pointer points to the next S1PICICWx register. S1PICICW1 and S1PICICW2 must always be programmed. Also, the S1PICICW3 register must always be programmed in this design because the SNGL bit in S1PICICW1 is internally fixed to 0. The S1PICICW4 register is skipped if the IC4 bit in S1PICICW1 is 0. Software is expected to initialize this register (S1PICICW4) if the IC4 bit is set in the S1PICICW1 register (see page 12-52). If the IC4 bit is cleared, the ELANSC520 microcontroller uses 01h for the value of this register (S1PICICW4). However, if the S2 bit is cleared in the MPICICW3 register (see page 12-34), then the Slave 1 controller is bypassed and programming this register (S1PICICW4) does not affect other registers. ElanTMSC520 Microcontroller Register Set Manual 12-59 Programmable Interrupt Controller Registers Slave 1 PIC Interrupt Mask (S1PICINTMSK) Direct-Mapped I/O Address 00A1h 7 Bit Reset R/W 6 IM6 x R/W 5 IM5 x R/W 4 IM4 x R/W 3 IM3 x R/W 2 IM2 x R/W 1 IM1 x R/W 0 IM0 x R/W IM7 x R/W Register Description This register provides masking of individual interrupt requests for the Slave 1 controller. This register is also known as Operation Control Word 1 in other PC/AT-compatible designs. Bit Definitions Bit 7 Name IM7 Function IR7 Mask 0 = Unmask IR7 1 = Mask IR7 IR6 Mask 0 = Unmask IR6 1 = Mask IR6 IR5 Mask 0 = Unmask IR5 1 = Mask IR5 IR4 Mask 0 = Unmask IR4 1 = Mask IR4 IR3 Mask 0 = Unmask IR3 1 = Mask IR3 IR2 Mask 0 = Unmask IR2 1 = Mask IR2 IR1 Mask 0 = Unmask IR1 1 = Mask IR1 IR0 Mask 0 = Unmask IR0 1 = Mask IR0 6 IM6 5 IM5 4 IM4 3 IM3 2 IM2 1 IM1 0 IM0 Programming Notes If the S2 bit in the MPICICW3 register is cleared (see page 12-34), then the Slave 1 controller is bypassed and the value of this register (S1PICINTMSK) has no effect. This register (S1PICINTMSK) cannot be accessed during a Slave 1 PIC initialization control sequence, which is initiated by setting the SLCT_ICW1 bit in the S1PICICW1 register (see page 12-51). When the S1PICICWx register initialization sequence is not in effect, any read or write of Port 00A1h accesses the S1PICINTMSK register. 12-60 ElanTMSC520 Microcontroller Register Set Manual Programmable Interrupt Controller Registers Floating Point Error Interrupt Clear (FPUERRCLR) Direct-Mapped I/O Address 00F0h 7 Bit Reset R/W 6 5 4 3 2 1 0 FPUERR_RST 0 0 0 0 W 0 0 0 0 Register Description This register is used to clear the Am5x86 CPU floating point unit (FPU) error interrupt request for DOS-compatible error handling. Bit Definitions Bit 7-0 Name FPUERR_RST Function Clear FPU Error Interrupt Request Any write to this register address clears the interrupt request that is generated by an Am5x86 CPU floating point unit error. (The CPU asserts the ferr signal internally.) At the conclusion of the write to this register, the CPU's ignne signal is asserted internally to allow non-control instructions to be executed. This function is provided for systems that require DOScompatible FPU error handling. Programming Notes ElanTMSC520 Microcontroller Register Set Manual 12-61 Programmable Interrupt Controller Registers 12-62 ElanTMSC520 Microcontroller Register Set Manual CHAPTER 13 13.1 PROGRAMMABLE INTERVAL TIMER REGISTERS OVERVIEW This chapter describes the programmable interval timer (PIT) registers of the ELANSC520 microcontroller. There are three PIT channels. The PIT module is one of four ELANSC520 microcontroller timer modules. The other timer modules are described in the following chapters: s Chapter 15, "Software Timer Registers" s Chapter 14, "General-Purpose Timer Registers" s Chapter 16, "Watchdog Timer Registers" The PIT register set consists of 10 direct-mapped I/O registers used to configure, control, and read status for the three PIT channels. It also includes the System Control Port B (SYSCTLB), which provides certain PIT-related functions. See the ElanTMSC520 Microcontroller User's Manual, order #22004, for details about the PIT channels. Table 13-1 lists the PIT registers in offset order, with the corresponding description's page number. 13.2 Table 13-1 REGISTERS Programmable Interval Timer Direct-Mapped Registers Register Name PIT Channel 0 Count PIT Channel 1 Count PIT Channel 2 Count PIT 0 Status PIT 1 Status PIT 2 Status PIT Mode Control PIT Counter Latch Command PIT Read-Back Command System Control Port B Mnemonic PIT0CNT PIT1CNT PIT2CNT PIT0STA PIT1STA PIT2STA PITMODECTL PITCNTLAT PITRDBACK SYSCTLB I/O Address 0040h 0041h 0042h 0040h 0041h 0042h 0043h 0043h 0043h 0061h Page Number page 13-2 page 13-3 page 13-4 page 13-5 page 13-5 page 13-5 page 13-7 page 13-10 page 13-11 page 13-13 ElanTMSC520 Microcontroller Register Set Manual 13-1 Programmable Interval Timer Registers PIT Channel 0 Count (PIT0CNT) Direct-Mapped I/O Address 0040h 7 Bit Reset R/W 6 5 4 3 2 1 0 CH0_CNT[15-0] 0 0 0 0 R/W 0 0 0 0 Register Description This register stores the current count values for PIT Channel 0. Bit Definitions Bit 7-0 Name CH0_CNT[15-0] Function 16-bit Counter for Programmable Interval Timer, Channel 0 This bit field provides read or write access to either the counter high byte only, low byte only, or low byte followed by high byte, as defined by the CTR_RW_LATCH bit field of the PITMODECTL register (see page 13-7). Either a latched or unlatched (free-running) count value can be read from this bit field (CH0_CNT). A latched count can be read immediately after a counter latch command is issued via the PITCNTLAT register (see page 13-10). After the one or two bytes of latched count data are read, subsequent reads return the unlatched count. A latched count can also be read immediately following a read-back command, issued via the PITRDBACK register, in which the LCNT bit is 0 and the CNT0 bit is 1 (see page 13-11). In this case also, after the one or two bytes of latched count are read, subsequent reads return the unlatched count. Programming Notes If a read-back command is issued by writing the PITRDBACK register with the LSTAT bit clear and the CNT0 bit set (see page 13-11), the subsequent read to this address (Port 0040h) returns the PIT0STA register status byte (see page 13-5). If a read-back command is issued in which PITRDBACK register bits LSTAT and LCNT are clear and bit CNT0 is set, the first subsequent read from this address (Port 0040h) returns the status byte, and the following one or two reads return latched count data as defined by the CTR_RW_LATCH bit field of the PITMODECTL register (see page 13-7). This counter can be configured for either binary-coded decimal (BCD) or 16-bit binary operation via the PITMODECTL register's BCD bit (see page 13-8). The counter range is 0-FFFFh in binary mode or 0-9999d in BCD. However, the maximum value in either mode can be achieved by clearing this register (PIT0CNT) to 0. All three PIT counters run at the same rate. If the CLK_PIN_DIR bit is 0 in the CLKSEL register (see page 20-9), the CLKTIMER input signal drives the PIT counters. Otherwise the PIT counters run at 1.1892 MHz. 13-2 ElanTMSC520 Microcontroller Register Set Manual Programmable Interval Timer Registers PIT Channel 1 Count (PIT1CNT) Direct-Mapped I/O Address 0041h 7 Bit Reset R/W 6 5 4 3 2 1 0 CH1_CNT[15-0] 0 0 0 0 R/W 0 0 0 0 Register Description This register stores the current count values for PIT Channel 1. Bit Definitions Bit 7-0 Name CH1_CNT[15-0] Function 16-bit Counter for Programmable Interval Timer, Channel 1 This bit field provides read or write access to either the counter high byte only, low byte only, or low byte followed by high byte, as defined by the CTR_RW_LATCH bit field of the PITMODECTL register (see page 13-7). Either a latched or unlatched (free-running) count value can be read from this bit field (CH1_CNT). A latched count can be read immediately after a counter latch command is issued via the PITCNTLAT register (see page 13-10). After the one or two bytes of latched count data are read, subsequent reads return the unlatched count. A latched count can also be read immediately following a read-back command, issued via the PITRDBACK register, in which the LCNT bit is 0 and the CNT1 bit is 1 (see page 13-11). In this case also, after the one or two bytes of latched count are read, subsequent reads return the unlatched count. Programming Notes If a read-back command is issued by writing the PITRDBACK register with the LSTAT bit clear and the CNT1 bit set (see page 13-11), the subsequent read to this address (Port 0041h) returns the PIT1STA register status byte (see page 13-5). If a read-back command is issued in which PITRDBACK register bits LSTAT and LCNT are clear and bit CNT1 is set, the first subsequent read from this address (Port 0041h) returns the status byte, and the following one or two reads return latched count data as defined by the CTR_RW_LATCH bit field of the PITMODECTL register (see page 13-7). This counter can be configured for either binary-coded decimal (BCD) or 16-bit binary operation via the PITMODECTL register's BCD bit (see page 13-8). The counter range is 0-FFFFh in binary mode or 0-9999d in BCD. However, the maximum value in either mode can be achieved by clearing this register (PIT1CNT) to 0. All three PIT counters run at the same rate. If the CLK_PIN_DIR bit is 0 in the CLKSEL register (see page 20-9), the CLKTIMER input signal drives the PIT counters. Otherwise the PIT counters run at 1.1892 MHz. ElanTMSC520 Microcontroller Register Set Manual 13-3 Programmable Interval Timer Registers PIT Channel 2 Count (PIT2CNT) Direct-Mapped I/O Address 0042h 7 Bit Reset R/W 6 5 4 3 2 1 0 CH2_CNT[15-0] 0 0 0 0 R/W 0 0 0 0 Register Description This register stores the current count values for PIT Channel 2. Bit Definitions Bit 7-0 Name CH2_CNT[15-0] Function 16-bit Counter for Programmable Interval Timer, Channel 2 This bit field provides read or write access to either the counter high byte only, low byte only, or low byte followed by high byte, as defined by the CTR_RW_LATCH bit field of the PITMODECTL register (see page 13-7). Either a latched or unlatched (free-running) count value can be read from this bit field (CH2_CNT). A latched count can be read immediately after a counter latch command is issued via the PITCNTLAT register (see page 13-10). After the one or two bytes of latched count data are read, subsequent reads return the unlatched count. A latched count can also be read immediately following a read-back command, issued via the PITRDBACK register, in which the LCNT bit is 0 and the CNT2 bit is 1 (see page 13-11). In this case also, after the one or two bytes of latched count are read, subsequent reads return the unlatched count. Programming Notes If a read-back command is issued by writing the PITRDBACK register with the LSTAT bit clear and the CNT2 bit set (see page 13-11), the subsequent read to this address (Port 0042h) returns the PIT2STA register status byte (see page 13-5). If a read-back command is issued in which PITRDBACK register bits LSTAT and LCNT are clear and bit CNT2 is set, the first subsequent read from this address (Port 0042h) returns the status byte, and the following one or two reads return latched count data as defined by the CTR_RW_LATCH bit field of the PITMODECTL register (see page 13-7). This counter can be configured for either binary-coded decimal (BCD) or 16-bit binary operation via the PITMODECTL register's BCD bit (see page 13-8). The counter range is 0-FFFFh in binary mode or 0-9999d in BCD. However, the maximum value in either mode can be achieved by clearing this register (PIT2CNT) to 0. All three PIT counters run at the same rate. If the CLK_PIN_DIR bit is 0 in the CLKSEL register (see page 20-9), the CLKTIMER input signal drives the PIT counters. Otherwise the PIT counters run at 1.1892 MHz. 13-4 ElanTMSC520 Microcontroller Register Set Manual Programmable Interval Timer Registers Direct-Mapped PIT 0 Status (PIT0STA) PIT 1 Status (PIT1STA) PIT 2 Status (PIT2STA) I/O Address 0040h I/O Address 0041h I/O Address 0042h 7 Bit Reset R/W 6 NULL_CNT 0 R 5 RW[1-0] 0 R 4 3 2 CTR_MODE_STA[2-0] 1 0 BCD OUTPUT 0 R 0 0 0 R 0 0 R Register Description These registers contain the programmed mode and the null count value for each timer channel. Bit Definitions Bit 7 Name OUTPUT Function Output State Output signal state for the timer channel. Each timer channel has an output that is driven High or Low based on the current mode. See the CTR_MODE_STA bit description on page 13-6 for a list of modes. 0 = Output is Low. 1 = Output is High. The three PIT outputs can be mapped individually to the microcontroller's internal programmable interrupt controller inputs. In addition, the PIT Channel 2 output can be enabled to drive the PITOUT2 pin. See the PIT_OUT2_ENB bit description on page 13-13. 6 NULL_CNT Null Count When programming a new count value into one of the timers, the new value does not take effect until it has actually been transferred to the counting element, which can take some time. When attempting to read back a count value, software can test this bit to determine whether the read-back value is valid or not. 0 = Counter is available for reading. 1 = Null count; read-back of the counter is invalid. Counter Read/Write Operation Control or Counter Latch Command Reflects the last bit setting that was programmed into the corresponding bits (5-4) of the PITMODECTL or PITCNTLAT register for this PIT channel (see page 13-7 and page 13-10). 00 = Counter Latch command (PITCNTLAT register). 01 = Read/write counter bits 7-0 only (PITMODECTL register). 10 = Read/write counter bits 15-8 only (PITMODECTL register). 11 = Read/write counter bits 7-0 followed immediately by bits 15-8 (PITMODECTL register). 5-4 RW[1-0] ElanTMSC520 Microcontroller Register Set Manual 13-5 Programmable Interval Timer Registers Bit 3-1 Name CTR_MODE_STA [2-0] Function Counter Mode Status Reflects the last counter mode setting for counters 0, 1, or 2 that was programmed into this channel via the CTR_MODE bit field of the PITMODECTL register (see page 13-8). Gate = High unless noted 000 = Mode 0: Interrupt on terminal count 001 = Mode 1: Hardware retriggerable one-shot 010 = Mode 2: Rate generator 011 = Mode 3: Square wave generator 100 = Mode 4: Software retriggerable strobe 101 = Mode 5: Hardware retriggerable strobe 110 = Alias for mode 2 111 = Alias for mode 3 See Table 13-2 on page 13-9 for more detail on counter modes. 0 BCD Binary Coded Decimal Select Status Reflects the last BCD setting for counters 0, 1, or 2 that was programmed into this channel via the BCD bit field of the PITMODECTL register (see page 13-8). 0 = 16-bit binary counter with a range of 0-FFFFh 1 = BCD counter with a range of 0-9999d Programming Notes The PITxSTA register is available only after a read-back command is issued by writing the PITRDBACK register with the LSTAT bit clear and the appropriate CNTx bit set (see page 13-11). 13-6 ElanTMSC520 Microcontroller Register Set Manual Programmable Interval Timer Registers PIT Mode Control (PITMODECTL) Direct-Mapped I/O Address 0043h 7 Bit Reset R/W 6 5 4 3 2 CTR_MODE[2-0] 1 0 BCD CTR_SEL[1-0] 0 W 0 CTR_RW_LATCH[1-0] 0 W 0 0 0 W 0 0 W Register Description This register stores the control word used to define the operation of the channels, including mode. Bit Definitions Bit 7-6 Name CTR_SEL[1-0] Function PIT Counter Select When this address (Port 0043h) is written with bits 7-6 11b and bits 5-4 00b, the PITMODECTL register is addressed, and this CTR_SEL bit field specifies which of the three PIT channels is affected by the settings written to bits 5-0. 00 = Select PIT counter 0. 01 = Select PIT counter 1. 10 = Select PIT counter 2. 11 = The PITRDBACK register is addressed (see page 13-11). When this address (Port 0043h) is written with bits 7-6 = 11b, this address is redefined (for the duration of the current I/O write) as the PITRDBACK register (see page 13-11). When this address (Port 0043h) is written with bits 7-6 11b, and bits 5-4 = 00b, this address is redefined (for the duration of the current I/O write) as the PITCNTLAT register (see page 13-10). 5-4 CTR_RW_LATCH [1-0] Counter Read/Write Operation Control When this address (Port 0043h) is written with bits 7-6 11b and bits 5-4 00b, the PITMODECTL register is addressed, and these CTR_RW_LATCH bits define what can be written to the PITxCNT register, where x is selected by bits 7-6 of this PITMODECTL register. 00 = The PITCNTLAT register is addressed (see page 13-10). 01 = Read/write counter bits 7-0 only. 10 = Read/write counter bits 15-8 only. 11 = Read/write counter bits 7-0 followed immediately by bits 15-8. See the PITxCNT register descriptions starting on page 13-2. Note that if a given PIT counter (as specified by the CTR_SEL bit field) is programmed for only eight bit accesses (i.e., this CTR_RW_LATCH bit field is 01b or 10b), a subsequent write to the count register automatically clears the eight bits of the associated internal 16-bit counting element that were not explicitly written to. ElanTMSC520 Microcontroller Register Set Manual 13-7 Programmable Interval Timer Registers Bit 3-1 Name CTR_MODE[2-0] Function Counter Mode When this address (Port 0043h) is written with bits 7-6 11b and bits 5-4 00b, the PITMODECTL register is addressed, and these bits control the counter operation: 000 = Mode 0: Interrupt on terminal count 001 = Mode 1: Hardware retriggerable one-shot (for PIT Channel 2) 010 = Mode 2: Rate generator 011 = Mode 3: Square wave generator 100 = Mode 4: Software retriggerable strobe 101 = Mode 5: Hardware retriggerable strobe (for PIT Channel 2) 110 = Alias for mode 2 111 = Alias for mode 3 See Table 13-2 on page 13-9 for more detail on this bit field. 0 BCD Binary Coded Decimal Select When this address (Port 0043h) is written with bits 7-6 11b and bits 5-4 00b, the PITMODECTL register is addressed, and this bit controls whether the counter indicated by bits 7-6 of this register counts in binary with a range of 0-FFFFh or in binary coded decimal (BCD) with a range of 0-9999d. 0 = 16-bit binary counter 1 = BCD counter Programming Notes Writing to this register (PITMODECTL) to change the mode for a particular counter resets the control logic and the associated output. Reads of this register return an undefined value. When a counter's current value is required, software should obtain it by issuing a counter latch or read-back command via the PITCNTLAT or PITRDBACK register (see page 13-10 or page 13-11). A counter latch or read-back command does not stop a counter from running, but rather takes a snapshot of the current value. Once the count has been latched, further latch commands are ignored until all latched count data is read back from the associated count register. A read-back command is a higher priority command than the counter latch command. The counter latch command is a subset of the read-back command because only one channel can have its counter latched per counter latch command. The programmable interval timer does not provide any way to read back the original count programmed into any of the three count registers. 13-8 ElanTMSC520 Microcontroller Register Set Manual Programmable Interval Timer Registers Table 13-2 PIT Counter Mode Settings Mode Name Interrupt on terminal count Description When the counter is programmed, the counter output transitions to 0. When the counter reaches 0, the counter output transitions to 1 and remains there until another count value is written. Before a counter is programmed to generate interrupts, the corresponding PITxMAP register (see page 12-21) must be configured to route the interrupt to the appropriate interrupt request level and priority. 001b = Mode 1 Hardware retriggerable one-shot1 Available for PIT Channel 2 only. When the Channel 2 counter is programmed, the Channel 2 output transitions to 1. After a Low-to-High transition of the internal gate 2 signal (controlled by the PITGATE2 signal or the PIT_GATE2 bit of the SYSCTLB register, see page 13-13), the counter output transitions to 0 until the count reaches 0, then the counter output transitions to 1 until the next Low-to-High transition on the gate input. Each time the count transitions to 1, the counter output transitions to 0 and remains there for one cycle of the input clock, and then the counter output transitions to 1. The count is automatically reloaded, and the process repeats. By default, PC/AT-compatible systems program Channel 0 for this mode. When the count is loaded, the counter output transitions to 1. When 1/2 of the count has expired, the counter output transitions to 0. When count transitions to 0, the counter output transitions to 1, and count is automatically reloaded. By default, PC/AT-compatible systems program Channels 1 and 2 to use this mode to drive DRAM refresh and the speaker, respectively. When the count is loaded, the counter output transitions to 1. When count transitions to 0, the counter output transitions to 0 for one clock period and then transitions to 1. Available for PIT Channel 2 only. The counter output behaves just as in mode 4 except that the triggering is done on a Low-to-High transition of the internal gate 2 signal (controlled by the PITGATE2 signal or the PIT_GATE2 bit of the SYSCTLB register, see page 13-13). A trigger seen during the count reloads the count to the initial value and then counting continues. Same as mode 2 Same as mode 3 CTR_MODE Bit Field Setting 000b = Mode 0 010b = Mode 2 Rate generator 011b = Mode 3 Square wave generator 100b = Mode 4 Software retriggerable strobe Hardware retriggerable strobe1 101b = Mode 5 110b 111b -- -- Notes: 1. Modes 1 and 5 require a rising edge on the gate input for each timer channel. Only PIT Channel 2 has a gate control (see the PIT_GATE2 bit in the SYSCTLB register, page 13-13) so only PIT Channel 2 is capable of running all modes. The gate controls for PIT channels 0 and 1 are fixed internally to 1, so they are capable of operation only in modes 0, 2, 3 and 4. ElanTMSC520 Microcontroller Register Set Manual 13-9 Programmable Interval Timer Registers PIT Counter Latch Command (PITCNTLAT) Direct-Mapped I/O Address 0043h 7 Bit Reset R/W 6 5 4 3 2 Reserved 1 0 CTR_SEL[1-0] 0 W 0 CTR_CMD[1-0] 0 W 0 0 0 0 RSV 0 Register Description This register allows the current count of the selected channel to be read. Bit Definitions Bit 7-6 Name CTR_SEL[1-0] Function PIT Counter Select When this address (Port 0043h) is written with bits 7-6 11b and bits 5-4 = 00b, the PITCNTLAT register is addressed, and this CTR_SEL bit field specifies which of the three counter elements to latch for read back from the associated count register: 00 = Select PIT counter 0. 01 = Select PIT counter 1. 10 = Select PIT counter 2. 11 = The PITRDBACK register is addressed (see page 13-11). When this address (Port 0043h) is written with bits 7-6 = 11b, this address is redefined (for the duration of the current I/O write) as the PITRDBACK register (see page 13-11). When this address (Port 0043h) is written with bits 7-6 11b and bits 5-4 00b, this address is redefined (for the duration of the current I/O write) as the PITMODECTL register (see page 13-7). 5-4 CTR_CMD[1-0] Counter Latch Command When this address (Port 0043h) is written with bits 7-6 11b and bits 5-4 = 00b, the PITCNTLAT register is addressed, and this CTR_CMD bit field invokes the counter latch command. 00 = The Counter Latch command is invoked. 01-11 = The PITMODECTL or PITRDBACK register is addressed (see page 13-7 and page 13-11). Latched counts are read back from the PITxCNT registers (see the descriptions starting on page 13-2) based on the current read/write mode selected for each counter via the CTR_RW_LATCH bit field of the PITMODECTL register (see page 13-7). 3-0 Reserved Reserved This bit field should be written to 0 for normal system operation. Programming Notes Reads of this register (PITCNTLAT) return an undefined value. When a counter's current value is required, software should obtain it by issuing a counter latch or read-back command via the PITCNTLAT or PITRDBACK register (see page 13-10 or page 13-11). A counter latch or read-back command does not stop a counter from running, but rather takes a snapshot of the current value. Once the count has been latched, further latch commands are ignored until all latched count data is read back from the associated count register. A read-back command is a higher priority command than the counter latch command. The counter latch command is a subset of the read-back command because only one channel can have its counter latched per counter latch command. The programmable interval timer does not provide any way to read back the original count programmed into any of the three count registers. 13-10 ElanTMSC520 Microcontroller Register Set Manual Programmable Interval Timer Registers PIT Read-Back Command (PITRDBACK) Direct-Mapped I/O Address 0043h 7 Bit Reset R/W 6 5 LCNT 0 W 4 LSTAT 0 W 3 CNT2 0 W 2 CNT1 0 W 1 CNT0 0 W 0 Reserved 0 RSV CTR_SEL[1-0] 0 W 0 Register Description This register allows the status and current count of each channel to be read. Bit Definitions Bit 7-6 Name CTR_SEL[1-0] Function PIT Counter Select/Read-back Command When this address (Port 0043h) is written with bits 7-6 = 11b, the PITRDBACK register is addressed, and this CTR_SEL bit field invokes the read-back command. 00-10 = The PITMODECTL or PITCNTLAT register is addressed (see page 13-7 and page 13-10). 11 = Read-back command: the values selected by bits 5-1 of this register are made available to be read back from the PITxCNT registers (see the descriptions starting on page 13-2) immediately following completion of the I/O write that invokes this read-back command. Latched counts are read back from the PITxCNT registers (see the descriptions starting on page 13-2) based on the current read/write mode selected for each counter via the CTR_RW_LATCH bit field of the PITMODECTL register (see page 13-7). The latched status bytes are returned in the PITxSTA register format (see page 13-5). If both LSTAT and LCNT = 0b, the status byte is made available at the respective PITxCNT register first. When this byte has been read, the latched count bytes are made available, bits 7-0 first, and then bits 15-8 (if the channel is set up to read back all 16 bits of count via the CTR_RW_LATCH bit field of the PITMODECTL). When this address (Port 0043h) is written with bits 7-6 11b and bits 5-4 00b, this address is redefined (for the duration of the current I/O write) as the PITMODECTL register (see page 13-7) When this address (Port 0043h) is written with bits 7-6 11b, and bits 5-4 = 00b, this address is redefined (for the duration of the current I/O write) as the PITCNTLAT register (see page 13-10). 5 LCNT Latch Count (Low True) 0 = Latch count data for the counters selected via bits CNT2-CNT0. 1 = Do not latch count data for the counters selected via bits CNT2-CNT0. Latch Status (Low True) 0 = Latch the status byte for the counters selected via bits CNT2-CNT0. 1 = Do not latch the status byte for the counters selected via bits CNT2-CNT0. Select Counter 2 0 = Counter 2 is not selected for operations specified by bits LCNT and LSTAT. 1 = Counter 2 is selected for operations specified by bits LCNT and LSTAT. Select Counter 1 0 = Counter 1 is not selected for operations specified by bits LCNT and LSTAT. 1 = Counter 1 is selected for operations specified by bits LCNT and LSTAT. Select Counter 0 0 = Counter 0 is not selected for operations specified by bits LCNT and LSTAT. 1 = Counter 0 is selected for operations specified by bits LCNT and LSTAT. 4 LSTAT 3 CNT2 2 CNT1 1 CNT0 ElanTMSC520 Microcontroller Register Set Manual 13-11 Programmable Interval Timer Registers Bit 0 Name Reserved Function Reserved This bit field should be written to 0 for normal system operation. Programming Notes Reads of this register (PITRDBACK) return an undefined value. When a counter's current value is required, software should obtain it by issuing a counter latch or read-back command via the PITCNTLAT or PITRDBACK register (see page 13-10 or page 13-11). A counter latch or read-back command does not stop a counter from running, but rather takes a snapshot of the current value. Once the count has been latched, further latch commands are ignored until all latched count data is read back from the associated count register. A read-back command is a higher priority command than the counter latch command. The counter latch command is a subset of the read-back command because only one channel can have its counter latched per counter latch command. The programmable interval timer does not provide any way to read back the original count programmed into any of the three count registers. 13-12 ElanTMSC520 Microcontroller Register Set Manual Programmable Interval Timer Registers System Control Port B (SYSCTLB) Direct-Mapped I/O Address 0061h 7 Bit Reset R/W 6 IOCHCK 0 R 5 PITOUT2_ STA 1 R 4 RFD x R 3 Reserved 0 RSV! 2 1 0 PERR 0 R PIT_OUT2_ PIT_GATE2 ENB 0 R/W 0 R/W Register Description This register contains the PC/AT-compatible System Control Port B register bits that pertain to the programmable interval timer (PIT). Bit Definitions Bit 7 6 5 Name PERR IOCHCK PIT_OUT2_STA Function PC/AT Parity Error Indicator This PC/AT-compatible bit is not supported (always reads back 0). PC/AT Channel Check Indicator This PC/AT-compatible bit is not supported (always reads back 0). PIT Timer 2 Output Pin State This status bit directly reflects the state of the output signal on Channel 2 of the programmable interval timer (PIT) and is sampled before the gate controlled by the PIT_OUT2_ENB bit. 0 = PIT Channel 2 output is Low. 1 = PIT Channel 2 output is High. DRAM Refresh Indicator On the original PC/AT, the PIT Channel 1 output was used to generate the refresh signal. In this design, this bit is tied directly to the 32-KHz clock source. Reserved This bit field is ignored in the ELANSC520 microcontroller. On the original PC/AT, this bit field was used to enable I/O channel check and RAM parity check. For software using this register to remain PC/AT-compatible, read-modify-write operations should be used to preserve this bit field's state. PIT Output Channel 2 Enable This bit enables the PIT Channel 2 output to the PITOUT2 pin. 0 = Do not propagate the PIT Channel 2 output to the PITOUT2 pin. The PITOUT2 pin is driven Low. 1 = Propagate the PIT Channel 2 output to the PITOUT2 pin. The PITOUT2 pin is connected to the system speaker in PC/AT-compatible systems. 4 RFD 3-2 Reserved 1 PIT_OUT2_ENB 0 PIT_GATE2 Timer 2 Gate Input Control This bit drives the gate input signal for PIT Channel 2. The PIT Channel 2 gate input controls the channel's operation if the mode is set appropriately via the channel's CTR_MODE bit field in the PITMODECTL register (see page 13-8). 0 = The PIT Channel 2 gate input is controlled by the PITGATE2 pin. 1 = The PIT Channel 2 gate input is asserted. If the PITGATE2 pin is configured for its alternate function, then the pin's input to the OR gate is held Low, and this bit (PIT_GATE2) effectively controls the Channel 2 gate input directly. Note: This bit (PIT_GATE2) is logically ORed with the PITGATE2 signal. Software using this bit should consider the configuration and state of the PITGATE2 pin. ElanTMSC520 Microcontroller Register Set Manual 13-13 Programmable Interval Timer Registers Programming Notes 13-14 ElanTMSC520 Microcontroller Register Set Manual CHAPTER 14 14.1 GENERAL-PURPOSE TIMER REGISTERS OVERVIEW This chapter describes the general-purpose (GP) timer registers of the ELANSC520 microcontroller. There are three GP timers. The GP timer module is one of four ELANSC520 microcontroller timer modules. The other timer modules are described in the following chapters: s Chapter 15, "Software Timer Registers" s Chapter 13, "Programmable Interval Timer Registers" s Chapter 16, "Watchdog Timer Registers" The GP timer register set consists of 12 memory-mapped configuration region (MMCR) registers used to configure and control each of the three GP timers. See the ElanTMSC520 Microcontroller User's Manual, order #22004, for details about the GP timers. Table 14-1 lists the GP timer registers in offset order, with the corresponding description's page number. 14.2 Table 14-1 REGISTERS General-Purpose Timer MMCR Registers Register Name GP Timers Status GP Timer 0 Mode/Control GP Timer 0 Count GP Timer 0 Maxcount Compare A GP Timer 0 Maxcount Compare B GP Timer 1 Mode/Control GP Timer 1 Count GP Timer 1 Maxcount Compare A GP Timer 1 Maxcount Compare B GP Timer 2 Mode/Control GP Timer 2 Count GP Timer 2 Maxcount Compare A Mnemonic GPTMRSTA GPTMR0CTL GPTMR0CNT GPTMR0MAXCMPA GPTMR0MAXCMPB GPTMR1CTL GPTMR1CNT GPTMR1MAXCMPA GPTMR1MAXCMPB GPTMR2CTL GPTMR2CNT GPTMR2MAXCMPA MMCR Offset Page Number C70h C72h C74h C76h C78h C7Ah C7Ch C7Eh C80h C82h C84h C8Eh page 14-2 page 14-3 page 14-6 page 14-7 page 14-8 page 14-9 page 14-12 page 14-13 page 14-14 page 14-15 page 14-17 page 14-18 ElanTMSC520 Microcontroller Register Set Manual 14-1 General-Purpose Timer Registers GP Timers Status (GPTMRSTA) Memory-Mapped MMCR Offset C70h 7 Bit Reset R/W 6 5 Reserved 4 3 2 T2_INT_ STA 1 T1_INT_ STA 0 R/W! 0 T0_INT_ STA 0 R/W! 0 0 0 RSV 0 0 0 R/W! Register Description This register contains the interrupt status information for the general-purpose timers. Bit Definitions Bit 7-3 2 Name Reserved T2_INT_STA Function Reserved This bit field should be written to 0 for normal system operation. GP Timer 2 Interrupt Status 0 = GP Timer 2 has not caused an interrupt, or software cleared this bit by writing 1. 1 = GP Timer 2 has caused an interrupt. This bit is set when the GP Timer 2 interrupt request is asserted. The interrupt request remains asserted until this status bit is cleared. Software must write a 1 to clear this bit. 1 T1_INT_STA GP Timer 1 Interrupt Status 0 = GP Timer 1 has not caused an interrupt, or software cleared this bit by writing 1. 1 = GP Timer 1 has caused an interrupt. This bit is set when the GP Timer 1 interrupt request is asserted. The interrupt request remains asserted until this status bit is cleared. Software must write a 1 to clear this bit. 0 T0_INT_STA GP Timer 0 Interrupt Status 0 = GP Timer 0 has not caused an interrupt, or software cleared this bit by writing 1. 1 = GP Timer 0 has caused an interrupt. This bit is set when the GP Timer 0 interrupt request is asserted. The interrupt request remains asserted until this status bit is cleared. Software must write a 1 to clear this bit. Programming Notes 14-2 ElanTMSC520 Microcontroller Register Set Manual General-Purpose Timer Registers GP Timer 0 Mode/Control (GPTMR0CTL) Memory-Mapped MMCR Offset C72h 15 Bit Reset R/W 14 P_ENB_WR 0 W 6 Reserved 13 INT_ENB 0 R/W 5 MAX_CNT 12 MAX_CNT_ RIU 0 R 4 RTG 0 R/W 11 10 Reserved 9 8 ENB 0 R/W! 7 0 0 RSV 0 0 3 PSC_SEL 0 R/W 2 EXT_CLK 0 R/W 1 ALT_CMP 0 R/W 0 CONT_ CMP 0 R/W Bit Reset R/W 0 RSV 0 0 R/W! Register Description This register is used to control the functionality and modes of operation of GP Timer 0 Bit Definitions Bit 15 Name ENB Function GP Timer 0 Enable 0 = GP Timer 0 is inhibited from counting. 1 = GP Timer 0 counting is enabled. If GP Timer 0 was previously enabled (via setting the ENB bit) and is operating, and then software clears the ENB bit by writing a 0, then GP Timer 0 is inhibited from counting but is not reset. The various timer status bits and the TMROUT0 output pin also remain stable. In this scenario, setting this ENB bit again causes the timer to continue from the state that it was in just prior to being disabled. This bit can only be modified (set or cleared) via software, if the P_ENB_WR bit of this register is set (i.e., written as 1) during the same write cycle access to this register. The ENB bit is automatically cleared by hardware under certain circumstances if noncontinuous mode is selected. See the CONT_CMP bit description on page 14-5. 14 P_ENB_WR GP Timer 0 Permit Enable Bit Write 0 = Software cannot modify the ENB bit in this write cycle. 1 = Software can modify the ENB bit in this write cycle. This bit allows selective software modifications of the ENB bit. When the P_ENB_WR bit is set during a write cycle access to this register, the ENB bit can be modified in that same write cycle. When the P_ENB_WR bit is written as a 0 during a write cycle access to this register, the ENB bit cannot be modified. This bit is always read back as a 0. ElanTMSC520 Microcontroller Register Set Manual 14-3 General-Purpose Timer Registers Bit 13 Name INT_ENB Function GP Timer 0 Interrupt Enable This bit allows the timer to generate an interrupt when the timer counter value reaches a maximum count compare register value. 0 = GP Timer 0 interrupt request generation is disabled. 1 = GP Timer 0 interrupt request generation is enabled. If the INT_ENB bit is 1, the T0_INT_STA bit is set in the GPTMRSTA register (see page 14-2) and an interrupt is generated when one of the following conditions occurs: s The ALT_CMP bit is 1 (see page 14-5) and the GPTMR0CNT register value (page 14-6) equals the value of either register GPTMR0MAXCMPA (page 14-7) or GPTMR0MAXCMPB (page 14-8). s The ALT_CMP bit is 0 and the GPTMR0CNT register value equals the value of the GPTMR0MAXCMPA register only. When the INT_ENB bit is 0, the timer does not cause the T0_INT_STA bit to be set in the GPTMRSTA register (see page 14-2), and therefore a timer interrupt is not generated. Before GP Timer 0 interrupts are enabled, the GPTMR0MAP register (see page 12-21) must be configured to route the interrupt to the appropriate interrupt request level and priority. 12 MAX_CNT_RIU GP Timer 0 Maxcount Compare Register In Use This bit can be used by software with the MAX_CNT bit to determine where the timer is in its current count sequence. 0 = Hardware clears this MAX_CNT_RIU bit when the GPTMR0MAXCMPA register (see page 14-7) is being used for comparison to the GP Timer 0 count value. 1 = Hardware sets this MAX_CNT_RIU bit when the GPTMR0MAXCMPB register (see page 14-8) is being used for comparison to the GP Timer 0 count value. Hardware also clears this bit any time hardware disables the timer by clearing the ENB bit (i.e., at the end of the timer count when in noncontinuous mode). See the CONT_CMP bit description on page 14-5. 11-6 5 Reserved MAX_CNT Reserved This bit field should be written to 0 for normal system operation. GP Timer 0 Maximum Count This bit can be used by software with the MAX_CNT_RIU bit to determine where the timer is in its current count sequence. 0 = Software must clear this bit by writing a 0 to it. This bit is never automatically cleared by hardware. 1 = This bit is set by hardware any time the timer count value reaches a maximum count value (maximum count value A or maximum count value B). This bit cannot be set by software. When GP Timer 0 is in alternate compare mode (the ALT_CMP bit = 1), the MAX_CNT bit is set whenever the timer 0 count value equals the value of either register GPTMR0MAXCMPA (see page 14-7) or GPTMR0MAXCMPB (page 14-8). The MAX_CNT bit is set for this condition regardless of the state of the INT_ENB bit. The MAX_CNT bit can be used to monitor timer status through software polling instead of making use of interrupt generation. 4 RTG GP Timer 0 Retrigger This bit determines the control function provided by the GP Timer 0 input pin (TMRIN0) when TMRIN0 is not configured as the timer clock source (i.e., when the EXT_CLK bit is 0). 0 = A high level on the TMRIN0 input pin allows the timer to count and a Low level on this pin holds the timer count value constant. 1 = If the timer is enabled, a 0 to 1 edge transition on the TMRIN0 pin resets the existing GP Timer 0 count value and then counting continues. This bit is ignored when external clocking is selected (i.e., when the EXT_CLK bit is 1). 14-4 ElanTMSC520 Microcontroller Register Set Manual General-Purpose Timer Registers Bit 3 Name PSC_SEL Function GP Timer 0 Prescaler This bit selects the GP Timer 0 clock source when the TMRIN0 input pin is not configured as the timer clock source (i.e., when the EXT_CLK bit is 0). 0 = The GP Timer 0 clock source is the internal clock (33.000 MHz or 33.333 MHz, depending on the crystal frequency). 1 = The GP Timer 0 is pre-scaled by GP Timer 2 (i.e., the internal GP Timer 2 output is used as the input clock source for GP Timer 0). This bit is ignored when external clocking is enabled (i.e., when the EXT_CLK bit is 1). 2 EXT_CLK GP Timer 0 External Clock This bit selects the external GP Timer 0 clock source. 0 = An internal GP Timer 0 clock source is used as configured via the PSC_SEL bit. When the timer clock is not being sourced from GP Timer 2, the timer advances every 4th CPU clock period. 1 = An external GP Timer 0 clock source is used (i.e., the TMRIN0 pin). GP Timer 0 advances upon every positive edge driven on the TMRIN0 input pin. In this mode, the maximum timer input clock frequency is 1/4th of the CPU clock speed. 1 ALT_CMP GP Timer 0 Alternate Compare This bit selects whether the GP Timer 0 count is compared to a single maximum count register value, or alternately to both maximum count register values. 0 = Single compare mode: the timer counts to the GPTMR0MAXCMPA register value (see page 14-7) and then resets the GPTMR0CNT register value to 0 (page 14-6). In this mode, the GPTMR0MAXCMPB register is not used. In single compare mode, the TMROUT0 pin is high while the counter is counting and being compared to the GPTMR0MAXCMPA register. The TMROUT0 pin is pulsed Low for a single CPU clock cycle after the maximum value is reached. 1 = Alternate compare (square wave) mode: if the timer is enabled, the timer counts to the GPTMR0MAXCMPA register value and then resets the GPTMR0CNT register to 0. Then the timer counts to the GPTMR0MAXCMPB register value (page 14-8) and then resets the GPTMR0CNT register value to 0. In alternate compare mode, the TMROUT0 pin is high while the counter is counting and being compared to the GPTMR0MAXCMPA register. The TMROUT0 pin is Low while the counter is counting and being compared to the GPTMR0MAXCMPB register. If the CONT_CMP bit is set, alternate compare mode generates a square wave signal on the TMROUT0 pin with a frequency and duty cycle determined by the two maximum count register values. Note: If external clocking is used and the clock is stopped during a count sequence, the timer output remains in its previous state (i.e., the state it was in prior to the clock stopping). The remaining timer status also remains the same and normal operation commences upon the external clock being driven again. See the CONT_CMP bit description for a more detailed description of how the comparison registers are used in continuous and noncontinuous modes. 0 CONT_CMP GP Timer 0 Continuous Mode This bit is used to configure GP Timer 0 for continuous or noncontinuous mode. 0 = Noncontinuous mode: the GPTMR0CNT register (see page 14-12) is cleared and the timer halts whenever the count reaches the maximum count value. The ENB bit is also cleared by hardware after every counter sequence. 1 = Continuous mode: The timer count is reset to 0 after it reaches the maximum count value (A or B), and the timer immediately begins counting again. If the CONT_CMP bit is cleared and the ALT_CMP bit is set, GP Timer 0 counts to the GPTMR0MAXCMPA register value (see page 14-13) and then resets the count value. After the timer count has been reset, the timer continues operation by counting to the GPTMR0MAXCMPB register value (page 14-14). When the timer count reaches the GPTMR0MAXCMPB register value, the timer clears its count value, clears the ENB bit and then halts. Programming Notes ElanTMSC520 Microcontroller Register Set Manual 14-5 General-Purpose Timer Registers GP Timer 0 Count (GPTMR0CNT) Memory-Mapped MMCR Offset C74h 15 Bit Reset R/W 14 13 12 11 10 9 8 CNT[15-8] 0 0 0 0 R/W 7 6 5 4 CNT[7-0] 0 0 0 0 R/W 0 0 0 0 3 2 1 0 0 0 0 0 Bit Reset R/W Register Description This register contains the current count of GP Timer 0. Bit Definitions Bit 15-0 Name CNT[15-0] Function GP Timer 0 Count Register This bit field contains the current count of GP Timer 0. The count rate depends on the value of the PSC_SEL and EXT_CLK bits in the GPTMR0CTL register (see page 14-5 and page 14-5). s If the EXT_CLK and PSC_SEL bits are both 0, the count is incremented every fourth processor clock cycle. s s If the EXT_CLK bit is 0 and the PSC_SEL bit is 1, the count is incremented each time the GP Timer 2 maxcount is reached. If the EXT_CLK bit is 1, the count is incremented on every positive edge driven on the TMRIN0 input pin (up to 1/4 of the CPU clock speed). This register (GPTMR0CNT) can be read at any time to determine the remaining count duration until a maximum count value is reached, at which time this register is reset by hardware. This register can also be written at any time. If this register is written while the counter is enabled, the new value is latched into the GP Timer 0 counter and counting proceeds from this new value. Programming Notes Each time this GPTMR0CNT register is incremented, its value is compared with the value of register GPTMR0MAXCMPA or GPTMR0MAXCMPB (see page 14-7 and page 14-8) and various actions are taken when a maximum count is reached. For details, see the GPTMR0CTL register bits INT_ENB, MAX_CNT_RIU, MAX_CNT, ALT_CMP, and CONT_CMP, starting on page 14-4. 14-6 ElanTMSC520 Microcontroller Register Set Manual General-Purpose Timer Registers GP Timer 0 Maxcount Compare A (GPTMR0MAXCMPA) Memory-Mapped MMCR Offset C76h 15 Bit Reset R/W 14 13 12 11 10 9 8 MCA[15-8] 0 0 0 0 R/W 7 6 5 4 MCA[7-0] 0 0 0 0 R/W 0 0 0 0 3 2 1 0 0 0 0 0 Bit Reset R/W Register Description This register contains one of the compare values for the GPTMR0CNT register (see page 14-6). Bit Definitions Bit 15-0 Name MCA[15-0] Function GP Timer 0 Maxcount Compare Register A This register contains one of the maximum values that GP Timer 0 can count to before resetting its count register to 0. Programming Notes GP Timer 0 and GP Timer 1 each have two maxcount compare registers, GPTMRxMAXCMPA and GPTMRxMAXCMPB. If the maxcount compare register that is in use contains the value 0000h and the timer is enabled, the timer counts to FFFFh, at which point the appropriate action occurs based on the timer configuration options that are set. For details, see the GPTMR0CTL register bits INT_ENB, MAX_CNT_RIU, MAX_CNT, ALT_CMP, and CONT_CMP, starting on page 14-4. If the maxcount compare register that is in use contains a value other than 0000h and the timer is enabled, the timer counts to the programmed maxcount value. ElanTMSC520 Microcontroller Register Set Manual 14-7 General-Purpose Timer Registers GP Timer 0 Maxcount Compare B (GPTMR0MAXCMPB) Memory-Mapped MMCR Offset C78h 15 Bit Reset R/W 14 13 12 11 10 9 8 MCB[15-8] 0 0 0 0 R/W 7 6 5 4 MCB[7-0] 0 0 0 0 R/W 0 0 0 0 3 2 1 0 0 0 0 0 Bit Reset R/W Register Description This register contains one of the compare values for the GPTMR0CNT register (see page 14-6). Bit Definitions Bit 15-0 Name MCB[15-0] Function GP Timer 0 Maxcount Compare Register B This register contains one of the maximum values that GP Timer 0 can count to before resetting its count register to 0. Programming Notes GP Timer 0 and GP Timer 1 each have two maxcount compare registers, GPTMRxMAXCMPA and GPTMRxMAXCMPB. If the maxcount compare register that is in use contains the value 0000h and the timer is enabled, the timer counts to FFFFh, at which point the appropriate action occurs based on the timer configuration options that are set. For details, see the GPTMR0CTL register bits INT_ENB, MAX_CNT_RIU, MAX_CNT, ALT_CMP, and CONT_CMP, starting on page 14-4. If the maxcount compare register that is in use contains a value other than 0000h and the timer is enabled, the timer counts to the programmed maxcount value. 14-8 ElanTMSC520 Microcontroller Register Set Manual General-Purpose Timer Registers GP Timer 1 Mode/Control (GPTMR1CTL) Memory-Mapped MMCR Offset C7Ah 15 Bit Reset R/W 14 P_ENB_WR 0 W 6 Reserved 13 INT_ENB 0 R/W 5 MAX_CNT 12 MAX_CNT_ RIU 0 R 4 RTG 0 R/W 11 10 Reserved 9 8 ENB 0 R/W! 7 0 0 RSV 0 0 3 PSC_SEL 0 R/W 2 EXT_CLK 0 R/W 1 ALT_CMP 0 R/W 0 CONT_ CMP 0 R/W Bit Reset R/W 0 RSV 0 0 R/W! Register Description This register is used to control the functionality and modes of operation of GP Timer 1. Bit Definitions Bit 15 Name ENB Function GP Timer 1 Enable 0 = GP Timer 1 is inhibited from counting. 1 = GP Timer 1 counting is enabled. If GP Timer 1 was previously enabled (via setting the ENB bit) and is operating, and then software clears the ENB bit by writing a 0, then GP Timer 1 is inhibited from counting but is not reset. The various timer status bits and the TMROUT1 output pin also remain stable. In this scenario, setting this ENB bit again causes the timer to continue from the state that it was in just prior to being disabled. This bit can only be modified (set or cleared) via software, if the P_ENB_WR bit of this register is set (i.e., written as 1) during the same write cycle access to this register. The ENB bit is automatically cleared by hardware under certain circumstances if noncontinuous mode is selected. See the CONT_CMP bit description on page 14-11. 14 P_ENB_WR GP Timer 1 Permit Enable Bit Write 0 = Software cannot modify the ENB bit in this write cycle. 1 = Software can modify the ENB bit in this write cycle. This bit allows selective software modifications of the ENB bit. When the P_ENB_WR bit is set during a write cycle access to this register, the ENB bit can be modified in that same write cycle. When the P_ENB_WR bit is written as a 0 during a write cycle access to this register, the ENB bit cannot be modified. This bit is always read back as a 0. ElanTMSC520 Microcontroller Register Set Manual 14-9 General-Purpose Timer Registers Bit 13 Name INT_ENB Function GP Timer 1 Interrupt Enable This bit allows the timer to generate an interrupt when the timer counter value reaches a maximum count compare register value. 0 = GP Timer 1 interrupt request generation is disabled. 1 = GP Timer 1 interrupt request generation is enabled. If the INT_ENB bit is 1, the T1_INT_STA bit is set in the GPTMRSTA register (see page 14-2) and an interrupt is generated when one of the following conditions occurs: s The ALT_CMP bit is 1 (see page 14-11) and the GPTMR1CNT register value (page 14-12) equals the value of either register GPTMR1MAXCMPA (page 14-13) or GPTMR1MAXCMPB (page 14-14). s The ALT_CMP bit is 0 and the GPTMR1CNT register value equals the value of the GPTMR1MAXCMPA register only. When the INT_ENB bit is 0, the timer does not cause the T1_INT_STA bit to be set in the GPTMRSTA register (see page 14-2), and therefore a timer interrupt is not generated. Before GP Timer 1 interrupts are enabled, the GPTMR1MAP register (see page 12-21) must be configured to route the interrupt to the appropriate interrupt request level and priority. 12 MAX_CNT_RIU GP Timer 1 Maxcount Compare Register In Use This bit can be used by software with the MAX_CNT bit to determine where the timer is in its current count sequence. 0 = Hardware clears this MAX_CNT_RIU bit when the GPTMR1MAXCMPA register (see page 14-13) is being used for comparison to the GP Timer 1 count value. 1 = Hardware sets this MAX_CNT_RIU bit when the GPTMR1MAXCMPB register (see page 14-14) is being used for comparison to the GP Timer 1 count value. Hardware also clears this bit any time hardware disables the timer by clearing the ENB bit (i.e., at the end of the timer count when in noncontinuous mode). See the CONT_CMP bit description on page 14-11. 11-6 5 Reserved MAX_CNT Reserved This bit field should be written to 0 for normal system operation. GP Timer 1 Maximum Count This bit can be used by software with the MAX_CNT_RIU bit to determine where the timer is in its current count sequence. 0 = Software must clear this bit by writing a 0 to it. This bit is never automatically cleared by hardware. 1 = This bit is set by hardware any time the timer count value reaches a maximum count value (maximum count value A or maximum count value B). This bit cannot be set by software. When GP Timer 1 is in alternate compare mode (the ALT_CMP bit = 1), the MAX_CNT bit is set whenever the GP Timer 1 count value equals the value of either register GPTMR1MAXCMPA (see page 14-13) or GPTMR1MAXCMPB (page 14-14). The MAX_CNT bit is set for this condition regardless of the state of the INT_ENB bit. The MAX_CNT bit can be used to monitor timer status through software polling instead of making use of interrupt generation. 4 RTG GP Timer 1 Retrigger This bit determines the control function provided by the GP Timer 1 input pin (TMRIN1) when TMRIN1 is not configured as the timer clock source (i.e., when the EXT_CLK bit is 0). 0 = A high level on the TMRIN1 input pin allows the timer to count and a Low level on this pin holds the timer count value constant. 1 = If the timer is enabled, a 0 to 1 edge transition on the TMRIN1 pin resets the existing GP Timer 1 count value and then counting continues. This bit is ignored when external clocking is selected (i.e., when the EXT_CLK bit is 1). 14-10 ElanTMSC520 Microcontroller Register Set Manual General-Purpose Timer Registers Bit 3 Name PSC_SEL Function GP Timer 1 Prescaler This bit selects the GP Timer 1 clock source when the TMRIN1 input pin is not configured as the timer clock source (i.e., when the EXT_CLK bit is 0). 0 = The GP Timer 1 clock source is the internal clock (33.000 MHz or 33.333 MHz, depending on the crystal frequency). 1 = The GP Timer 1 is pre-scaled by GP Timer 2 (i.e., the internal GP Timer 2 output is used as the input clock source for GP Timer 1). This bit is ignored when external clocking is enabled (i.e., the EXT_CLK bit is 1). 2 EXT_CLK GP Timer 1 External Clock This bit selects the external GP Timer 1 clock source. 0 = An internal GP Timer 1 clock source is used as configured via the PSC_SEL bit. When the timer clock is not being sourced from GP Timer 2, the timer advances every 4th CPU clock period. 1 = An external GP Timer 1 clock source is used (i.e., the TMRIN1 pin). GP Timer 1 advances upon every positive edge driven on the TMRIN1 input pin. In this mode, the maximum timer input clock frequency is 1/4th of the CPU clock speed. 1 ALT_CMP GP Timer 1 Alternate Compare This bit selects whether the GP Timer 1 count is compared to a single maximum count register value, or alternately to both maximum count register values. 0 = Single compare mode: the timer counts to the GPTMR1MAXCMPA register value (see page 14-13) and then resets the GPTMR1CNT register value to 0 (page 14-12). In this mode, the GPTMR1MAXCMPB register is not used. In single compare mode, the TMROUT1 pin is high while the counter is counting and being compared to the GPTMR1MAXCMPA register. The TMROUT1 pin is pulsed Low for a single CPU clock cycle after the maximum value is reached. 1 = Alternate compare (square wave) mode: if the timer is enabled, the timer counts to the GPTMR1MAXCMPA register value and then resets the GPTMR1CNT register to 0. Then the timer counts to the GPTMR1MAXCMPB register value (page 14-14) and then resets the GPTMR1CNT register value to 0. In alternate compare mode, the TMROUT1 pin is high while the counter is counting and being compared to the GPTMR1MAXCMPA register. The TMROUT1 pin is Low while the counter is counting and being compared to the GPTMR1MAXCMPB register. If the CONT_CMP bit is set, alternate compare mode generates a square wave signal on the TMROUT1 pin with a frequency and duty cycle determined by the two maximum count register values. Note: If external clocking is used and the clock is stopped during a count sequence, the timer output remains in its previous state (i.e., the state it was in prior to the clock stopping). The remaining timer status also remains the same and normal operation commences upon the external clock being driven again. See the Continuous mode bit description below for a more detailed description of how the comparison registers are used in continuous and noncontinuous modes. 0 CONT_CMP GP Timer 1 Continuous Mode This bit is used to configure GP Timer 1 for continuous or noncontinuous mode. 0 = Noncontinuous mode: the GPTMR1CNT register (see page 14-12) is cleared and the timer halts whenever the count reaches the maximum count value. The ENB bit is also cleared by hardware after every counter sequence. 1 = Continuous mode: The timer count is reset to 0 after it reaches the maximum count value (A or B), and the timer immediately begins counting again. If the CONT_CMP bit is cleared and the ALT_CMP bit is set, GP Timer 1 counts to the GPTMR1MAXCMPA register value (see page 14-13) and then resets the count value. After the timer count has been reset, the timer continues operation by counting to the GPTMR1MAXCMPB register value (page 14-14). When the timer count reaches the GPTMR1MAXCMPB register value, the timer clears its count value, clears the ENB bit and then halts. Programming Notes ElanTMSC520 Microcontroller Register Set Manual 14-11 General-Purpose Timer Registers GP Timer 1 Count (GPTMR1CNT) Memory-Mapped MMCR Offset C7Ch 15 Bit Reset R/W 14 13 12 11 10 9 8 CNT[15-8] 0 0 0 0 R/W 7 6 5 4 CNT[7-0] 0 0 0 0 R/W 0 0 0 0 3 2 1 0 0 0 0 0 Bit Reset R/W Register Description This register contain the current count of GP Timer 1. Bit Definitions Bit 15-0 Name CNT[15-0] Function GP Timer 1 Count Register This bit field contains the current count of GP Timer 1. The count rate depends on the value of the PSC_SEL and EXT_CLK bits in the GPTMR1CTL register (see page 14-11 and page 14-11). s If the EXT_CLK and PSC_SEL bits are both 0, the count is incremented every fourth processor clock cycle. s s If the EXT_CLK bit is 0 and the PSC_SEL bit is 1, the count is incremented each time the GP Timer 2 maxcount is reached. If the EXT_CLK bit is 1, the count is incremented on every positive edge driven on the TMRIN1 input pin (up to 1/4 of the CPU clock speed). This register (GPTMR1CNT) can be read at any time to determine the remaining count duration until a maximum count value is reached, at which time this register is reset by hardware. This register can also be written at any time. If this register is written while the counter is enabled, the new value is latched into the GP Timer 1 counter and counting proceeds from this new value. Programming Notes Each time this GPTMR1CNT register is incremented, its value is compared with the value of register GPTMR1MAXCMPA or GPTMR1MAXCMPB (see page 14-13 and page 14-14) and various actions are taken when a maximum count is reached. For details, see the GPTMR1CTL register bits INT_ENB, MAX_CNT_RIU, MAX_CNT, ALT_CMP, and CONT_CMP, starting on page 14-10. 14-12 ElanTMSC520 Microcontroller Register Set Manual General-Purpose Timer Registers GP Timer 1 Maxcount Compare A (GPTMR1MAXCMPA) Memory-Mapped MMCR Offset C7Eh 15 Bit Reset R/W 14 13 12 11 10 9 8 MCA[15-8] 0 0 0 0 R/W 7 6 5 4 MCA[7-0] 0 0 0 0 R/W 0 0 0 0 3 2 1 0 0 0 0 0 Bit Reset R/W Register Description This register contains one of the compare values for the GPTMR1CNT register (see page 14-12). Bit Definitions Bit 15-0 Name MCA[15-0] Function GP Timer 1 Maxcount Compare Register A This register contains one of the maximum values that GP Timer 1 can count to before resetting its count register to 0. Programming Notes GP Timer 0 and GP Timer 1 each have two maxcount compare registers, GPTMRxMAXCMPA and GPTMRxMAXCMPB. If the maxcount compare register that is in use contains the value 0000h and the timer is enabled, the timer counts to FFFFh, at which point the appropriate action occurs based on the timer configuration options that are set. For details, see the GPTMR1CTL register bits INT_ENB, MAX_CNT_RIU, MAX_CNT, ALT_CMP, and CONT_CMP, starting on page 14-10. If the maxcount compare register that is in use contains a value other than 0000h and the timer is enabled, the timer counts to the programmed maxcount value. ElanTMSC520 Microcontroller Register Set Manual 14-13 General-Purpose Timer Registers GP Timer 1 Maxcount Compare B (GPTMR1MAXCMPB) Memory-Mapped MMCR Offset C80h 15 Bit Reset R/W 14 13 12 11 10 9 8 MCB[15-8] 0 0 0 0 R/W 7 6 5 4 MCB[7-0] 0 0 0 0 R/W 0 0 0 0 3 2 1 0 0 0 0 0 Bit Reset R/W Register Description This register contains one of the compare values for the GPTMR1CNT register (see page 14-12). Bit Definitions Bit 15-0 Name MCB[15-0] Function GP Timer 1 Maxcount Compare Register B This register contains one of the maximum values that GP Timer 1 can count to before resetting its count register to 0. Programming Notes GP Timer 0 and GP Timer 1 each have two maxcount compare registers, GPTMRxMAXCMPA and GPTMRxMAXCMPB. If the maxcount compare register that is in use contains the value 0000h and the timer is enabled, the timer counts to FFFFh, at which point the appropriate action occurs based on the timer configuration options that are set. For details, see the GPTMR1CTL register bits INT_ENB, MAX_CNT_RIU, MAX_CNT, ALT_CMP, and CONT_CMP, starting on page 14-10. If the maxcount compare register that is in use contains a value other than 0000h and the timer is enabled, the timer counts to the programmed maxcount value. 14-14 ElanTMSC520 Microcontroller Register Set Manual General-Purpose Timer Registers GP Timer 2 Mode/Control (GPTMR2CTL) Memory-Mapped MMCR Offset C82h 15 Bit Reset R/W 14 P_ENB_WR 0 W 6 Reserved 13 INT_ENB 0 R/W 5 MAX_CNT 12 11 10 Reserved 9 8 ENB 0 R/W! 7 0 0 0 RSV 0 0 4 3 Reserved 2 1 0 CONT_ CMP Bit Reset R/W 0 RSV 0 0 R/W! 0 0 RSV 0 0 0 R/W Register Description This register is used to control the functionality and modes of operation of GP Timer 2. Bit Definitions Bit 15 Name ENB Function GP Timer 2 Enable 0 = GP Timer 2 is inhibited from counting. 1 = GP Timer 2 counting is enabled. If GP Timer 2 was previously enabled (via setting the ENB bit) and is operating, and then software clears the ENB bit by writing a 0, then GP Timer 2 is inhibited from counting but is not reset. The various timer status bits also remain stable. In this scenario, setting this ENB bit again causes the timer to continue from the state that it was in just prior to being disabled. This bit can only be modified (set or cleared) via software, if the P_ENB_WR bit of this register is set (i.e., written as 1) during the same write cycle access to this register. The ENB bit is automatically cleared by hardware under certain circumstances if noncontinuous mode is selected. See the CONT_CMP bit description on page 14-16. 14 P_ENB_WR GP Timer 2 Permit Enable Bit Write 0 = Software cannot modify the ENB bit in this write cycle. 1 = Software can modify the ENB bit in this write cycle. This bit allows selective software modifications of the ENB bit. When the P_ENB_WR bit is set during a write cycle access to this register, the ENB bit can be modified in that same write cycle. When the P_ENB_WR bit is written as a 0 during a write cycle access to this register, the ENB bit cannot be modified. This bit is always read back as a 0. ElanTMSC520 Microcontroller Register Set Manual 14-15 General-Purpose Timer Registers Bit 13 Name INT_ENB Function GP Timer 2 Interrupt Enable This bit allows the timer to generate an interrupt when the timer count value reaches the maximum count compare register value. 0 = GP Timer 2 interrupt request generation is disabled. 1 = GP Timer 2 interrupt request generation is enabled. If the INT_ENB bit is 1, the T2_INT_STA bit is set in the GPTMRSTA register (see page 14-2) and an interrupt is generated when the GPTMR2CNT register value (page 14-17) equals the value of the GPTMR2MAXCMPA register (page 14-18). When the INT_ENB bit is 0, the timer does not cause the T2_INT_STA bit to be set in the GPTMRSTA register (see page 14-2), and therefore a timer interrupt is not generated. Before GP Timer 2 interrupts are enabled, the GPTMR2MAP register (see page 12-21) must be configured to route the interrupt to the appropriate interrupt request level and priority. 12-6 5 Reserved MAX_CNT Reserved This bit field should be written to 0 for normal system operation. GP Timer 2 Maximum Count This bit can be used by software to determine where the timer is in its current count sequence. 0 = Software must clear this bit by writing a 0 to it. This bit is never automatically cleared by hardware. 1 = This bit is set by hardware any time the timer count value reaches its maximum count value (GPTMR2MAXCMPA register, see page 14-18). The MAX_CNT bit is set for this condition regardless of the state of the INT_ENB bit. The MAX_CNT bit can be used to monitor timer status through software polling instead of making use of interrupt generation. 4-1 0 Reserved CONT_CMP Reserved This bit field should be written to 0 for normal system operation. GP Timer 2 Continuous Mode This bit is used to configure GP Timer 2 for continuous or noncontinuous mode. 0 = Noncontinuous mode: the GPTMR2CNT register (see page 14-12) is cleared and the timer halts whenever the count reaches the maximum count value (GPTMR2MAXCMPA register, see page 14-18). The ENB bit is also cleared by hardware after every counter sequence. 1 = Continuous mode: The timer count is reset to 0 after it reaches the maximum count value, and the timer immediately begins counting again. Programming Notes 14-16 ElanTMSC520 Microcontroller Register Set Manual General-Purpose Timer Registers GP Timer 2 Count (GPTMR2CNT) Memory-Mapped MMCR Offset C84h 15 Bit Reset R/W 14 13 12 11 10 9 8 CNT[15-8] 0 0 0 0 R/W 7 6 5 4 CNT[7-0] 0 0 0 0 R/W 0 0 0 0 3 2 1 0 0 0 0 0 Bit Reset R/W Register Description This register contains the current count of GP Timer 2. Bit Definitions Bit 15-0 Name CNT[15-0] Function GP Timer 2 Count Register This bit field contains the current count of GP Timer 2. The count is incremented every fourth processor clock cycle. This register (GPTMR2CNT) can be read at any time to determine the remaining count duration until a maximum count value is reached, at which time this register is reset by hardware. This GPTMR2CNT register can also be written at any time. If this register is written while the counter is enabled, the new value is latched into the GP Timer 2 counter and counting proceeds from this new value. Programming Notes Each time this GPTMR2CNT register is incremented, its value is compared with the GPTMR2MAXCMPA register (see page 14-18) and various actions are taken when a maximum count is reached. For details, see the GPTMR2CTL register bits INT_ENB, MAX_CNT, and CONT_CMP, starting on page 14-16. ElanTMSC520 Microcontroller Register Set Manual 14-17 General-Purpose Timer Registers GP Timer 2 Maxcount Compare A (GPTMR2MAXCMPA) Memory-Mapped MMCR Offset C8Eh 15 Bit Reset R/W 14 13 12 11 10 9 8 MCA[15-8] 0 0 0 0 R/W 7 6 5 4 MCA[7-0] 0 0 0 0 R/W 0 0 0 0 3 2 1 0 0 0 0 0 Bit Reset R/W Register Description This register contains the single compare values for the GPTMR2CNT register (see page 14-17). Bit Definitions Bit 15-0 Name MCA[15-0] Function GP Timer 2 Maxcount Compare Register A This register contains the maximum value that GP Timer 2 can count to before resetting its count register to 0. Programming Notes GP Timer 2 has only one maxcount compare register. If this register (GPTMR2MAXCMPA) is written with the value 0000h and the timer is enabled, the timer counts to FFFFh, at which point the appropriate action occurs based on the timer configuration options that are set. For details, see the GPTMR2CTL register bits INT_ENB, MAX_CNT, and CONT_CMP, starting on page 14-16. If the maxcount compare register contains a value other than 0000h and the timer is enabled, the timer counts to the programmed maxcount value. 14-18 ElanTMSC520 Microcontroller Register Set Manual CHAPTER 15 15.1 SOFTWARE TIMER REGISTERS OVERVIEW This chapter describes the software timer registers of the ELANSC520 microcontroller. The software timer is one of four ELANSC520 microcontroller timer modules. The other timer modules are described in the following chapters: s Chapter 14, "General-Purpose Timer Registers" s Chapter 13, "Programmable Interval Timer Registers" s Chapter 16, "Watchdog Timer Registers" The software timer register set consists of three memory-mapped configuration region (MMCR) registers used access and control the timer. See the ElanTMSC520 Microcontroller User's Manual, order #22004, for details about the software timer. Table 15-1 lists the software timer registers in offset order, with the corresponding description's page number. 15.2 Table 15-1 REGISTERS Software Timer MMCR Registers Register Name Software Timer Millisecond Count Software Timer Microsecond Count Software Timer Configuration Mnemonic SWTMRMILLI SWTMRMICRO SWTMRCFG MMCR Offset Page Number C60h C62h C64h page 15-2 page 15-3 page 15-4 ElanTMSC520 Microcontroller Register Set Manual 15-1 Software Timer Registers Software Timer Millisecond Count (SWTMRMILLI) Memory-Mapped MMCR Offset C60h 15 Bit Reset R/W 14 13 12 11 10 9 8 MS_CNT[15-8] 0 0 0 0 R! 7 6 5 4 3 2 1 0 0 0 0 0 Bit Reset R/W MS_CNT[7-0] 0 0 0 0 R! 0 0 0 0 Register Description This register contains the current millisecond count of the software timer. Bit Definitions Bit 15-0 Name MS_CNT[15-0] Function 16-bit Millisecond Count This read-only bit field increments at a rate of 1000 counts per second. This millisecond counter is set to zero at system reset. Note: When read, this counter is automatically reset to 0. This millisecond counter is not reset when the US_CNT bit field in the SWTMRMICRO register is read (see page 15-3). In order to maintain a millisecond time base, this MS_CNT bit field must be read at least once every 65.5 seconds. When this MS_CNT bit field is read, the value in the internal free-running microsecond up counter is automatically latched into the US_CNT bit field in the SWTMRMICRO register. The internal microsecond counter increments at a rate of 1 MHz and counts from 0 to 999. It rolls over from 999 back to zero. Every time the microsecond counter rolls over, the MS_CNT bit field is incremented. Note that the XTAL_FREQ bit in the SWTMRCFG register (see page 15-4) must be set appropriately in order for the increment rate to be correct. Programming Notes A 32-bit read of the SWTMRMILLI register address is broken up into two 16-bit reads. The first 16-bit read returns the SWTMRMILLI register and latches the SWTMRMICRO register (see page 15-3). The second 16-bit read returns the (newly latched) SWTMRMICRO register contents. Thus, the 32-bit value returned includes the correct millisecond and microsecond values at the time of software's 32-bit read, with the millisecond value stored in the lower 16 bits and the microsecond value stored in the upper 16 bits. Byte (8-bit) reads of the SWTMRMILLI register are not allowed. 15-2 ElanTMSC520 Microcontroller Register Set Manual Software Timer Registers Software Timer Microsecond Count (SWTMRMICRO) Memory-Mapped MMCR Offset C62h 15 Bit Reset R/W 14 13 Reserved 12 11 10 9 8 US_CNT[9-8] 0 0 0 0 R 4 3 2 1 0 0 0 0 0 RSV 7 Bit Reset R/W 6 5 US_CNT[7-0] 0 0 0 0 R 0 0 0 0 Register Description This register contains the current latched microsecond count of the software timer. Bit Definitions Bit 15-10 9-0 Name Reserved US_CNT [9-0] Function Reserved This bit field should be written to 0 for normal system operation. SWT Microsecond Count This read-only bit field holds the latched microsecond count value from a free running microsecond counter. Each read of this bit field returns the currently latched microsecond count value. On each read of the SWTMRMILLI register (see page 15-2), the value in the internal microsecond counter is latched into this bit field (US_CNT). This US_CNT bit field is reset to 0 at system reset. The internal microsecond counter increments at a rate of 1 MHz and counts from 0 to 999. It rolls over from 999 back to 0. Every time the microsecond counter rolls over, the MS_CNT bit field in the SWTMRMILLI register is incremented (see page 15-2). Note that the XTAL_FREQ bit in the SWTMRCFG register (see page 15-4) must be set appropriately in order for the increment rate to be correct. Programming Notes ElanTMSC520 Microcontroller Register Set Manual 15-3 Software Timer Registers Software Timer Configuration (SWTMRCFG) Memory-Mapped MMCR Offset C64h 7 Bit Reset R/W 6 5 4 Reserved 3 2 1 0 XTAL_ FREQ 0 0 0 0 RSV 0 0 0 0 R/W Register Description This register is used to calibrate the software timer to the crystal frequency being used. Bit Definitions Bit 7-1 0 Name Reserved XTAL_FREQ Function Reserved This bit field should be written to 0 for normal system operation. Crystal Frequency This field is used to specify the frequency of the crystal used to drive the main system clock. Configure this bit appropriately to ensure that the software timer increments at the correct rate for the system. 0 = Specifies that the system is using a 33.333 MHz crystal. 1 = Specifies that the system is using a 33.000 MHz crystal. Note that this bit has no effect on the general-purpose timers, programmable interval timer, or watchdog timer. Programming Notes 15-4 ElanTMSC520 Microcontroller Register Set Manual CHAPTER 16 16.1 WATCHDOG TIMER REGISTERS OVERVIEW This chapter describes the watchdog timer registers of the ELANSC520 microcontroller. The watchdog timer is one of four ELANSC520 microcontroller timer modules. The other timer modules are described in the following chapters: s Chapter 15, "Software Timer Registers" s Chapter 14, "General-Purpose Timer Registers" s Chapter 13, "Programmable Interval Timer Registers" The watchdog timer register set consists of three memory-mapped configuration region (MMCR) registers used to configure, control, and monitor the status of the watchdog timer. See the ElanTMSC520 Microcontroller User's Manual, order #22004, for details about the watchdog timer. Table 16-1 lists the watchdog timer registers in offset order, with the corresponding description's page number. 16.2 Table 16-1 REGISTERS Watchdog Timer MMCR Registers Register Name Watchdog Timer Control Watchdog Timer Count Low Watchdog Timer Count High Reserved Mnemonic WDTMRCTL WDTMRCNTL WDTMRCNTH -- MMCR Offset CB0h CB2h CB4h CB6h Page Number page 16-2 page 16-4 page 16-5 -- ElanTMSC520 Microcontroller Register Set Manual 16-1 Watchdog Timer Registers Watchdog Timer Control (WDTMRCTL) Memory-Mapped MMCR Offset CB0h 15 Bit Reset R/W 14 WRST_ENB 1 R/W! 6 13 Reserved 0 RSV 5 12 IRQ_FLG 0 R/W! 4 11 10 Reserved 9 8 ENB 0 R/W! 7 0 0 RSV 0 0 3 2 1 0 Bit Reset R/W EXP_SEL[7-0] 1 0 0 0 R/W! 0 0 0 0 Register Description This register is used to control the watchdog timer. This register can only be accessed after writing special keyed sequences as described in the programming notes. Bit Definitions Bit 15 Name ENB Function Watchdog Timer Enable This is the watchdog timer enable bit. 0 = The watchdog timer is disabled. 1 = The watchdog timer is enabled. When this bit is set, the current count is automatically reset to 0, the WRST_ENB and EXP_SEL fields become read-only, and the watchdog timer counter begins counting. Before the watchdog timer is enabled with the WRST_ENB bit cleared, the WDTMAP register (see page 12-21) must be configured to route the interrupt to the appropriate interrupt request level and priority. 14 WRST_ENB Watchdog Timer Reset Enable This is a programmable bit to select between a reset or interrupt as the time-out action. 0 = The watchdog timer time-out generates an interrupt request if the IRQ_FLG bit is not already set. If IRQ_FLG bit is set, a system reset is generated instead. 1 = The watchdog timer time-out always generates a system reset. When the watchdog timer generates a system reset, the WDT_RST_DET bit is set in the RESSTA register (see page 3-5). 13 12 Reserved IRQ_FLG Reserved This bit field should be written to 0 for normal system operation. Interrupt Request Flag This bit provides an indication of interrupt events generated by the watchdog timer time-out. This bit is accessible even after the ENB bit is set. 0 = No watchdog timer interrupt has occurred. 1 = Watchdog timer interrupt has occurred. This bit is cleared by writing a 1. After a watchdog timer time-out occurs, if this bit is not cleared before a second time-out of the watchdog timer, a watchdog timer system reset is generated instead of a second interrupt request. 11-8 Reserved Reserved This bit field should be written to 0 for normal system operation. 16-2 ElanTMSC520 Microcontroller Register Set Manual Watchdog Timer Registers Bit 7-0 Name EXP_SEL[7-0] Function Exponent Select This bit field determines the duration of the watchdog timer time-out interval. Table 16-2 shows the values for the EXP_SEL field. The bit values shown in the table are programmed to select a time-out exponent as shown in the "Exponent" column. The selected exponent determines the time-out duration according to the following equation: Time-out duration = 2exponent / CPU Frequency where Time-out duration is the time-out period in seconds exponent is the value selected from Table 16-2 CPU Frequency is the operating speed of the CPU in Hz. When multiple bits are set in the EXP_SEL field, the least significant bit set is used to select the exponent. Table 16-2 Watchdog Timer Exponent Selections Bits Time-Out Interval 33.000 MHz Infinity 496 ms 508 ms 1.02 s 2.03 s 4.07 s 8.13 s 16.27 s 32.54 s Time-Out Interval 33.333 MHz Infinity 492 ms 503 ms 1.01 s 2.01 s 4.03 s 8.05 s 16.11 s 32.21 s 7 0 X X X X X X X 1 6 0 X X X X X X 1 0 5 0 X X X X X 1 0 0 4 0 X X X X 1 0 0 0 3 0 X X X 1 0 0 0 0 2 0 X X 1 0 0 0 0 0 1 0 X 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 Exponent N/A 14 24 25 26 27 28 29 30 For example, to program a maximum time-out of about 32 seconds, the EXP_SEL field is set to 80h. The time-out value can then be calculated as follows for the ELANSC520 microcontroller with a 33.000 MHz CPU clock. Time-out interval = 230 / (33.000 MHz crystal frequency) = 230 / (33,000,000) = 32.54 seconds. Programming Notes The watchdog timer can only be programmed after special keyed sequences are written to this address. Two special keyed sequences are recognized: s The key sequence of 3333h followed by CCCCh is called the write key and is used to open this Watchdog Timer Control (WDTMRCTL) register for a single write. s The key sequence of AAAAh followed by 5555h is called the clear-count key and is used to clear the current watchdog timer counter. Note: All keys are written to the WDTMRCTL register address (MMCR offset CB0h). Normally this register is read-only. The write key sequence must be written before a value can be programmed into this register; after this single value is written, the write key sequence must be applied again before another value can be programmed. The ENB bit must be 0 before the WRST_ENB bit or the EXP_SEL bit field can be written. When the microcontroller is in AMDebugTM technology mode, the WDTMRCTL register can still be accessed in the normal manner. However, the AMDebug technology stops the count registers from incrementing further to prevent the watchdog timer from causing an interrupt or reset in AMDebug technology mode. ElanTMSC520 Microcontroller Register Set Manual 16-3 Watchdog Timer Registers Watchdog Timer Count Low (WDTMRCNTL) Memory-Mapped MMCR Offset CB2h 15 Bit Reset R/W 14 13 12 11 10 9 8 COUNTL[15-8] 0 0 0 0 R 7 6 5 4 3 2 1 0 0 0 0 0 Bit Reset R/W COUNTL[7-0] 0 0 0 0 R 0 0 0 0 Register Description This read-only register contains the lower 16 bits of the watchdog timer counter. In normal operation the clear-count key sequence (AAAAh followed by 5555h) clears the watchdog timer counter. Note that the clear-count key is written to the WDTMRCTL register address (see page 16-2). Bit Definitions Bit 15-0 Name COUNTL[15-0] Function Current Count Low This field contains the low word [15-0] of the watchdog timer current count. The counter value is automatically reset when the watchdog timer is enabled. Programming Notes Although both the WDTMRCNTH and WDTMRCNTL registers can be read with a single 32-bit CPU instruction, the 32-bit access is split into two 16-bit accesses. See the GP Timer chapter in the ElanTMSC520 Microcontroller User's Manual, order #22004, for suggestions if it is necessary to read an accurate 32-bit value from the watchdog timer counter. 16-4 ElanTMSC520 Microcontroller Register Set Manual Watchdog Timer Registers Watchdog Timer Count High (WDTMRCNTH) Memory-Mapped MMCR Offset CB4h 15 Bit Reset R/W 14 13 12 11 COUNTH[14-8] 10 9 8 Reserved 0 RSV 7 6 5 4 0 0 0 0 R 3 0 0 0 2 1 0 Bit Reset R/W COUNTH[7-0] 0 0 0 0 R 0 0 0 0 Register Description This read-only register contains the higher 15 bits of the watchdog timer counter. In normal operation the clear-count key sequence (AAAAh followed by 5555h) clears the watchdog timer counter. Note that the clear-count key is written to the WDTMRCTL register address (see page 16-2). Bit Definitions Bit 15 14-0 Name Reserved COUNTH[14-0] Function Reserved This bit field should be written to 0 for normal system operation. Current Count High This field contains the high word [30-16] of the watchdog timer current count. The counter value is automatically reset when the watchdog timer is enabled. Programming Notes Although both the WDTMRCNTH and WDTMRCNTL registers can be read with a single 32-bit CPU instruction, the 32-bit access is split into two 16-bit accesses. See the GP Timer chapter in the ElanTMSC520 Microcontroller User's Manual, order #22004, for suggestions if it is necessary to read an accurate 32-bit value from the watchdog timer counter. ElanTMSC520 Microcontroller Register Set Manual 16-5 Watchdog Timer Registers 16-6 ElanTMSC520 Microcontroller Register Set Manual CHAPTER 17 17.1 REAL-TIME CLOCK REGISTERS OVERVIEW This chapter describes the real-time clock (RTC) registers of the ELANSC520 microcontroller. The ELANSC520 microcontroller includes a PC/AT-compatible RTC. The RTC register set includes two groups of registers: s Two direct-mapped I/O addresses used to access the RTC configuration space. s 14 RTC-indexed configuration registers used to set, read, and configure the RTC. s 114 bytes of RTC-indexed nonvolatile RAM locations used in PC/AT-compatible systems to store various system parameters. See the ElanTMSC520 Microcontroller User's Manual, order #22004, for details about the RTC. Table 17-1 and Table 17-2 list each type of RTC register in offset order, with the corresponding description's page number. 17.2 Table 17-1 REGISTERS Real-Time Clock Direct-Mapped Registers Register Name RTC/CMOS RAM Index RTC/CMOS RAM Data Port Mnemonic RTCIDX RTCDATA I/O Address 0070h 0071h Page Number page 17-2 page 17-3 Table 17-2 Real-Time Clock Indexed Registers Register Name RTC Current Second RTC Alarm Second RTC Current Minute RTC Alarm Minute RTC Current Hour RTC Alarm Hour RTC Current Day of the Week RTC Current Day of the Month RTC Current Month RTC Current Year RTC Control A RTC Control B RTC Status C RTC Status D General-Purpose CMOS RAM (114 bytes) Mnemonic RTCCURSEC RTCALMSEC RTCCURMIN RTCALMMIN RTCCURHR RTCALMHR RTCCURDOW RTCCURDOM RTCCURMON RTCCURYR RTCCTLA RTCCTLB RTCSTAC RTCSTAD RTCCMOS I/O Address 70h/71h 70h/71h 70h/71h 70h/71h 70h/71h 70h/71h 70h/71h 70h/71h 70h/71h 70h/71h 70h/71h 70h/71h 70h/71h 70h/71h 70h/71h RTC Index 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0E-7Fh Page Number page 17-4 page 17-5 page 17-6 page 17-7 page 17-8 page 17-9 page 17-10 page 17-11 page 17-12 page 17-13 page 17-14 page 17-16 page 17-18 page 17-20 page 17-21 ElanTMSC520 Microcontroller Register Set Manual 17-1 Real-Time Clock Registers RTC/CMOS RAM Index (RTCIDX) Direct-Mapped I/O Address 70h 7 Bit Reset R/W 6 5 4 3 CMOSIDX[6-0] 2 1 0 Reserved x RSV 0 0 0 0 W 0 0 0 Register Description This register is used to specify the RTC index address to be accessed via the RTCDATA register (see page 17-3). Bit Definitions Bit 7 6-0 Name Reserved CMOSIDX[6-0] Function Reserved RTC/CMOS RAM Index This bit field is used to specify the RTC or CMOS RAM index to be read or written via the RTCDATA register (see page 17-3). Programming Notes Bit 7 of this register is typically used as the NMI enable bit in PC/AT-compatible systems. In the ELANSC520 microcontroller this function has been moved to the NMI_ENB bit in the PICICR register (see page 12-4). See the programmable interrupt controller chapter of the ElanTMSC520 Microcontroller User's Manual, order #22004, for more information. 17-2 ElanTMSC520 Microcontroller Register Set Manual Real-Time Clock Registers RTC/CMOS RAM Data Port (RTCDATA) Direct-Mapped I/O Address 71h 7 Bit Reset R/W 6 5 4 3 2 1 0 CMOSDATA[7-0] x x x x R/W x x x x Register Description This register is the RTC data port used to access the RTC index specified in the RTCIDX register (see page 17-2) Bit Definitions Bit 7-0 Name CMOSDATA [7-0] Function RTC/CMOS Data Port This bit field is used to write to or read from the RTC index specified in the RTCIDX register (see page 17-2). Programming Notes ElanTMSC520 Microcontroller Register Set Manual 17-3 Real-Time Clock Registers RTC Current Second (RTCCURSEC) I/O Address 70h/71h RTC Index 00h 7 Bit Reset R/W 6 5 4 3 2 1 0 SECOND[7-0] x x x x R/W! x x x x Register Description This register is the RTC current second initialization and read-back register. Bit Definitions Bit 7-0 Name SECOND[7-0] Function RTC Current Second Software initializes the seconds value for the RTC by writing data to this bit field in binary or binary-coded decimal (BCD) format. The seconds component of the RTC time can be read from this bit field. The RTC logic updates this bit field once per second. Valid values for this bit field range from 0 to 59d. If a value greater than 59d is programmed, the bit field value increments up to FFh, wraps around to 0, and only then does the value remain in the valid range. Programming Notes Software can suspend updating of this register via the SET bit in the RTCCTLB register (see page 17-16). Software selects binary or BCD format via the DATE_MODE bit in the RTCCTLB register. 17-4 ElanTMSC520 Microcontroller Register Set Manual Real-Time Clock Registers RTC Alarm Second (RTCALMSEC) I/O Address 70h/71h RTC Index 01h 7 Bit Reset R/W 6 5 4 3 2 1 0 ALM_SECOND[7-0] x x x x R/W! x x x x Register Description This register is used to initialize and read back the RTC alarm second. Bit Definitions Bit 7-0 Name ALM_ SECOND[7-0] Function RTC Alarm Second Software initializes the alarm seconds value for the RTC by writing data to this bit field in either binary or binary-coded decimal (BCD) format. The alarm seconds component of the RTC time can be read from this bit field. Writing any value from C0h to FFh to this bit field makes the seconds component of the alarm a wild card. For example, setting the hours, minutes, and seconds alarm registers to C0h causes an RTC alarm event to be generated once per second. The wild card based once-persecond alarm does not occur unless the hours and minutes alarm settings are also wild cards. The RTC logic checks once per second to see if an alarm has occurred. Valid values for this bit field range from 0 to 59d and all wild card values. Programming Notes Software can suspend updating of the RTC via the SET bit in the RTCCTLB register (see page 17-16). Software selects binary or BCD format via the DATE_MODE bit in the RTCCTLB register. Software can enable the RTC alarm as an interrupt via the ALM_INT_ENB bit in the RTCCTLB register. The ALM_INT_FLG bit in the RTCSTAC register indicates whether an alarm event has occurred (see page 17-18). ElanTMSC520 Microcontroller Register Set Manual 17-5 Real-Time Clock Registers RTC Current Minute (RTCCURMIN) I/O Address 70h/71h RTC Index 02h 7 Bit Reset R/W 6 5 4 3 2 1 0 MINUTE[7-0] x x x x R/W! x x x x Register Description This register is used to initialize and read back the RTC current minute. Bit Definitions Bit 7-0 Name MINUTE[7-0] Function RTC Current Minute Software initializes the minutes value for the RTC by writing data to this bit field in either binary or binary-coded decimal (BCD) format. The minutes component of the RTC time can be read from this bit field. The RTC logic updates this bit field once per second. Valid values for this bit field range from 0 to 59d. If a value greater than 59d is programmed, the bit field value increments up to FFh, wraps around to 0, and only then does the value remain in the valid range. Programming Notes Software can suspend updating of the RTC via the SET bit in the RTCCTLB register (see page 17-16). Software selects binary or BCD format via the DATE_MODE bit in the RTCCTLB register. 17-6 ElanTMSC520 Microcontroller Register Set Manual Real-Time Clock Registers RTC Alarm Minute (RTCALMMIN) I/O Address 70h/71h RTC Index 03h 7 Bit Reset R/W 6 5 4 3 2 1 0 ALM_MINUTE[7-0] x x x x R/W! x x x x Register Description This register used to initialize and read back the RTC alarm minute. Bit Definitions Bit 7-0 Name ALM_ MINUTE[7-0] Function RTC Alarm Minute Software initializes the alarm minutes value for the RTC by writing data to this bit field in either binary or binary-coded decimal (BCD) format. The alarm minutes component of the RTC time can be read from this bit field. Writing a value of C0-FFh to this bit field makes the minutes component of the alarm a wild card. For example, setting the hours and minutes alarm registers to C0h causes an RTC alarm event to be generated once per minute. The wild card based once-per-minute alarm does not occur unless the hours alarm setting is also a wild card. The RTC logic checks once per second to see if an alarm has occurred. Valid values for this bit field range from 0 to 59d and all wild card values. Programming Notes Software can suspend updating of the RTC via the SET bit in the RTCCTLB register (see page 17-16). Software selects binary or BCD format via the DATE_MODE bit in the RTCCTLB register. Software can enable the RTC alarm as an interrupt via the ALM_INT_ENB bit in the RTCCTLB register. The ALM_INT_FLG bit in the RTCSTAC register indicates whether an alarm event has occurred (see page 17-18). ElanTMSC520 Microcontroller Register Set Manual 17-7 Real-Time Clock Registers RTC Current Hour (RTCCURHR) I/O Address 70h/71h RTC Index 04h 7 Bit Reset R/W 6 5 4 3 HOUR[6-0] 2 1 0 AM_PM x R/W! x x x x R/W! x x x Register Description This register used to initialize and read back the RTC current hour. Bit Definitions Bit 7 Name AM_PM Function RTC AM/PM Indicator If the HOUR_MODE_SEL bit is 0 in the RTCCTLB register (see page 17-17), the AM_PM bit is used to indicate whether the current hour is AM or PM. 0 = The current hour is AM (12-hour mode only). In 24-hour mode, always clear this bit to 0. 1 = The current hour is PM (12-hour mode only). The RTC logic updates this bit field once per second. 6-0 HOUR[6-0] RTC Current Hour Software initializes the hours value for the RTC by writing data to this bit field in either binary or binary-coded decimal (BCD) format. The hours component of the RTC time can be read from this bit field. The RTC logic updates this bit field once per second. In 24-hour mode, valid values for this bit field range from 0 to 23d. In 12-hour mode, valid values for this bit field range from 1 to 12d. If a value outside of the valid range is programmed, the register value (including the AM_PM bit) increments up to FFh, wraps around to 0, and only then does the value remain within the valid range. Programming Notes Software selects 12-hour or 24-hour mode via the HOUR_MODE_SEL bit in the RTCCTLB register (see page 17-17). Software can suspend updating of the RTC via the SET bit in the RTCCTLB register. Software selects binary or BCD format via the DATE_MODE bit in the RTCCTLB register. 17-8 ElanTMSC520 Microcontroller Register Set Manual Real-Time Clock Registers RTC Alarm Hour (RTCALMHR) I/O Address 70h/71h RTC Index 05h 7 Bit Reset R/W 6 5 4 3 ALM_HOUR[6-0] 2 1 0 ALM_ AM_PM x R/W! x x x x R/W! x x x Register Description This register used to initialize and read back the RTC alarm hour. Bit Definitions Bit 7 Name ALM_ AM_PM Function RTC Alarm AM/PM Indicator If the HOUR_MODE_SEL bit is 0 in the RTCCTLB register (see page 17-17), the ALM_AM_PM bit is used to indicate whether the alarm hour is AM or PM. 0 = The alarm hour is AM (12-hour mode only). In 24-hour mode, always clear this bit to 0 unless programming a wild card (see the ALM_HOUR bit description). 1 = The alarm hour is PM (12-hour mode only). The RTC logic checks this bit field once per second. 6-0 ALM_HOUR [6-0] RTC Alarm Hour Software initializes the alarm hour value for the RTC by writing data to this bit field in either binary or binary-coded decimal (BCD) format. The alarm hours component of the RTC time can be read from this bit field. Writing a value of C0-FFh to this register makes the hours component of the alarm a wild card. For example setting the hours alarm register to C0h causes an RTC alarm event to be generated once per hour. Note that if this register is written with a wild card when 12-hour mode is selected, the ALM_AM_PM bit is a "don't care" because an alarm occurs every hour regardless. The RTC logic checks once per second to see if an alarm has occurred. In 24-hour mode, valid values for this bit field range from 0 to 23d and all wild card values. In 12-hour mode, valid values for this bit field range from 1 to 12d and all wild card values. Programming Notes Software selects 12-hour or 24-hour mode via the HOUR_MODE_SEL bit in the RTCCTLB register (see page 17-17). Software can suspend updating of the RTC via the SET bit in the RTCCTLB register. Software selects binary or BCD format via the DATE_MODE bit in the RTCCTLB register. Software can enable the RTC alarm as an interrupt via the ALM_INT_ENB bit in the RTCCTLB register. The ALM_INT_FLG bit in the RTCSTAC register indicates whether an alarm event has occurred (see page 17-18). ElanTMSC520 Microcontroller Register Set Manual 17-9 Real-Time Clock Registers RTC Current Day of the Week (RTCCURDOW) I/O Address 70h/71h RTC Index 06h 7 Bit Reset R/W 6 5 4 3 2 1 0 DAY_OF_WEEK[7-0] x x x x R/W! x x x x Register Description This register used to initialize and read back the RTC current day of the week. Bit Definitions Bit 7-0 Name DAY_OF_ WEEK[7-0] Function RTC Current Day of the Week Software initializes the day of week value for the RTC by writing data to this bit field in either binary or binary-coded decimal (BCD) formats. The RTC logic updates this bit field once per second. Valid values for this bit field range from 1d to 7d where: 1d = Sunday 2d = Monday 3d = Tuesday 4d = Wednesday 5d = Thursday 6d = Friday 7d = Saturday If a value greater than 7d is programmed, the bit field value increments up to FFh, wraps around to 0, and only then does the value remain within the valid range. Programming Notes Software can suspend updating of the RTC via the SET bit in the RTCCTLB register (see page 17-16). Software selects binary or BCD format via the DATE_MODE bit in the RTCCTLB register. 17-10 ElanTMSC520 Microcontroller Register Set Manual Real-Time Clock Registers RTC Current Day of the Month (RTCCURDOM) I/O Address 70h/71h RTC Index 07h 7 Bit Reset R/W 6 5 4 3 2 1 0 DAY_OF_MTH[7-0] x x x x R/W! x x x x Register Description This register used to initialize and read back the RTC current day of the month. Bit Definitions Bit 7-0 Name DAY_OF_MTH [7-0] Function RTC Current Day of the Month Software initializes the day of month value for the RTC by writing data to this bit field in either binary or binary-coded decimal (BCD) formats. The RTC logic updates this bit field once per second. Valid values for this bit field range from 1 to 31. However, a value in this range is considered invalid if it is inappropriate for the month programmed in the MONTH bit field in the RTCCURMON register (see page 17-12). If a value greater than the number of days in the current month is programmed, the bit field value increments up to FFh, wraps around to 0, and only then does the value remain in the valid range. If the MONTH bit field in the RTCCURMON register is 2d (February), and the YEAR bit field value in the RTCCURYR register (see page 17-13) is a leap year, the DAY_OF_MTH bit field does leap year compensation automatically. Programming Notes Software can suspend updating of the RTC via the SET bit in the RTCCTLB register (see page 17-16). Software selects binary or BCD format via the DATE_MODE bit in the RTCCTLB register. ElanTMSC520 Microcontroller Register Set Manual 17-11 Real-Time Clock Registers RTC Current Month (RTCCURMON) I/O Address 70h/71h RTC Index 08h 7 Bit Reset R/W 6 5 4 3 2 1 0 MONTH[7-0] x x x x R/W! x x x x Register Description This register used to initialize and read back the RTC current month Bit Definitions Bit 7-0 Name MONTH[7-0] Function RTC Current Month Software initializes current month value for the RTC by writing data to this bit field in either binary or binary-coded decimal (BCD) formats. The RTC logic updates this bit field once per second. Valid values for this bit field range from 1d to 12d where: 1d = January 2d = February 3d = March 4d = April 5d = May 6d = June 7d = July 8d = August 9d = September 10d = October 11d = November 12d = December If a value greater than 12d is programmed, the bit field value increments up to FFh, wraps around to 0, and only then does the value remain within the valid range. Programming Notes Software can suspend updating of the RTC via the SET bit in the RTCCTLB register (see page 17-16). Software selects binary or BCD format via the DATE_MODE bit in the RTCCTLB register. 17-12 ElanTMSC520 Microcontroller Register Set Manual Real-Time Clock Registers RTC Current Year (RTCCURYR) I/O Address 70h/71h RTC Index 09h 7 Bit Reset R/W 6 5 4 YEAR[7-0] 3 2 1 0 x x x x R/W! x x x x Register Description This register used to initialize and read back the RTC current year Bit Definitions Bit 7-0 Name YEAR[7-0] Function RTC Current Year Software initializes current year value for the RTC by writing data to this bit field in either binary or binary-coded decimal (BCD) formats. The RTC logic updates this bit field once per second. Valid values for this bit field range from 0 to 99d. If a value greater than 99d is programmed, the bit field value increments up to FFh, wraps around to 0, and only then does the value remain within the valid range. Programming Notes Software can suspend updating of the RTC via the SET bit in the RTCCTLB register (see page 17-16). Software selects binary or BCD format via the DATE_MODE bit in the RTCCTLB register. Refer to the RTC chapter in the ElanTMSC520 Microcontroller User's Manual, order #22004, for guidelines on storing current century information to address year-2000 issues. ElanTMSC520 Microcontroller Register Set Manual 17-13 Real-Time Clock Registers RTC Control A (RTCCTLA) I/O Address 70h/71h RTC Index 0Ah 7 Bit Reset R/W 6 5 OSC_CTL[2-0] 4 3 2 1 0 UIP x R! x RATE_SEL[3-0] x x x R/W x x x R/W Register Description The RTC Control A register is used to determine if an RTC update is in progress, and to control the RTC internal oscillator and periodic interrupt rate. Bit Definitions Bit 7 Name UIP Function Update in Progress This bit is provided for use by software that needs to modify the time, calendar or alarm registers in the real-time clock. 0 = Software has a guaranteed minimum window of 244 ms in which modifications to the time, calendar, and alarm registers are allowed. While the UIP bit is 0, the time, calendar, and alarm information in RTC RAM is not in transition, and are fully available to software. 1 = The time, calendar, and alarm registers are unavailable for access by software because internal RTC logic is using them. Setting the SET bit in the RTCCTLB register (see page 17-16) inhibits RTC register update cycles and clears the UIP status bit. The UIP bit is a read-only bit and is not affected by reset. 6-4 OSC_CTL[2-0] Internal Oscillator Control Bits 010 = Enable the RTC divider chain to run at the internal time base frequency, which results in one time base update per second. This is the normal operational setting for the OSC_CTL bit. 110 = Hold the RTC divider chain in the reset state. In this mode, the time and date update cycles do not occur. This mode is useful for precision setting of the clock. Time and date update cycles begin 500 milliseconds after the value of 010b is written to this field. 111 = Same as 110b. All other values are reserved. Setting the OSC_CTL value to anything other than 11xb or 010b causes the RTC time base updates to occur at a frequency other than 1Hz. These three bits are not affected by an RTC-only reset, and must be initialized to ensure correct operation. 17-14 ElanTMSC520 Microcontroller Register Set Manual Real-Time Clock Registers Bit 3-0 Name RATE_SEL [3-0] Function Rate Selection The periodic interrupt output of the RTC is internally tied to the programmable interrupt controller (PIC) and is available for use. The RATE_SEL bit field controls the rate at which periodic interrupts are driven to PIC as follows: 0000 = Periodic interrupt disabled 0001 = 3.906 ms 0010 = 7.812 ms 0011 = 122.070 ms 0100 = 244.141 ms 0101 = 488.281 ms 0110 = 976.563 ms 0111 = 1.953 ms 1000 = 3.906 ms 1001 = 7.812 ms 1010 = 15.625 ms 1011 = 31.250 ms 1100 = 62.500 ms 1101 = 125.000 ms 1110 = 250.000 ms 1111 = 500.000 ms The periodic interrupt is enabled by the PER_INT_ENB bit field in the RTCCTLB register (see page 17-16). The PER_INT_FLG bit in the RTCSTAC register provides latched status for the RTC periodic interrupt event (see page 17-18). Programming Notes ElanTMSC520 Microcontroller Register Set Manual 17-15 Real-Time Clock Registers RTC Control B (RTCCTLB) I/O Address 70h/71h RTC Index 0Bh 7 Bit Reset R/W 6 PER_ INT_ENB 0 R/W 5 ALM_ INT_ENB 0 R/W 4 UPD_ INT_ENB 0 R/W 3 Reserved 0 RSV 2 DATE_ MODE x R/W 1 HOUR_ MODE_SEL x R/W 0 DS_ENB x R/W SET x R/W Register Description The RTC Control B register is used to temporarily inhibit RTC updates is in progress, to enable RTC interrupts, and to control date encoding, 12/24-hour mode, and daylight savings. . Bit Definitions Bit 7 Name SET Function Set 0 = Time and date update cycles are enabled and occur once per second. 1 = Time and date update cycles are disabled, and any update in progress is aborted. The SET bit feature is useful for allowing time and date registers to be updated by software without being disturbed by an automatic update cycle occurring during the change. Neither internal functions nor RTC-only resets affect the SET bit. The SET bit should be set to 1 while changing the DATE_MODE, HOUR_MODE_SEL, or DS_ENB bits; and cleared afterward. 6 PER_ INT_ENB Periodic Interrupt Enable 0 = No RTC periodic interrupt is generated. 1 = The RTC periodic interrupt is enabled. When the PER_INT_FLG bit in the RTCSTAC register transitions from 0 to 1 (see page 17-18), the RTC periodic interrupt latches the INT_FLG bit in the RTCSTAC register to 1 (see page 17-18). If the PER_INT_FLG bit is 1 when the PER_INT_ENB bit is set by software, the INT_FLG bit is asserted immediately. The PER_INT_ENB bit is not modified by any internal RTC functions, but is cleared by an RTC-only reset. The periodic interrupt rate is configured with the RATE_SEL bit field in the RTCCTLA register (see page 17-15). The PER_INT_FLG bit in the RTCSTAC register provides latched status for the RTC periodic event (see page 17-18). Before any RTC interrupt is enabled, the RTCMAP register (see page 12-21) must be configured to route the interrupt to the appropriate interrupt request level and priority. 5 ALM_ INT_ENB Alarm Interrupt Enable 0 = No RTC alarm interrupt is generated. 1 = The RTC alarm interrupt is enabled. When the ALM_INT_FLG bit in the RTCSTAC register transitions from 0 to 1 (see page 17-18), the RTC alarm interrupt latches the INT_FLG bit in the RTCSTAC register to 1 (see page 17-18). If the ALM_INT_FLG bit is 1 when the ALM_INT_ENB bit is set by software, the INT_FLG bit is asserted immediately. The ALM_INT_ENB bit is not modified by any internal RTC functions, but is cleared by an RTC-only reset. The alarm interrupt time is configured with the RTCALMSEC (page 17-5), RTCALMMIN (page 17-7), and RTCALMHR (page 17-9) registers. The ALM_INT_FLG bit in the RTCSTAC register provides latched status for the RTC alarm event (see page 17-18). Before any RTC interrupt is enabled, the RTCMAP register (see page 12-21) must be configured to route the interrupt to the appropriate interrupt request level and priority. 17-16 ElanTMSC520 Microcontroller Register Set Manual Real-Time Clock Registers Bit 4 Name UPD_ INT_ENB Function Update-Ended Interrupt Enable 0 = No RTC update ended interrupt is generated. 1 = The RTC update ended interrupt is enabled. When the UPD_INT_FLG bit in the RTCSTAC register transitions from 0 to 1 (see page 17-19), the RTC update ended interrupt latches the INT_FLG bit in the RTCSTAC register to 1 (see page 17-18). If the UPD_INT_FLG bit is 1 when the UPD_INT_ENB bit is set by software, the INT_FLG bit is asserted immediately. The UPD_INT_ENB bit is not modified by any internal RTC functions, but is cleared by an RTC-only reset, or by writing the SET bit to 1. The UPD_INT_FLG bit in the RTCSTAC register provides latched status for the RTC update ended event (see page 17-19). Before any RTC interrupt is enabled, the RTCMAP register (see page 12-21) must be configured to route the interrupt to the appropriate interrupt request level and priority. 3 2 Reserved DATE_MODE Reserved This bit field should be written to 0 for normal system operation. Date Mode The DATE_MODE bit selects whether time and calendar updates are to use binary or binarycoded decimal (BCD) formats. 0 = RTC time and calendar data use BCD encoding. 1 = RTC time and calendar data use binary encoding. Neither internal functions nor RTC-only resets affect this bit. The RTC time and date configuration registers (RTC indexes 0-9h) must be reinitialized after software changes the DATE_MODE bit. Software should set the SET bit to 1 before changing the DATE_MODE bit and then clear the SET bit afterward. 1 HOUR_ MODE_SEL 12/24-Hour Mode Select The HOUR_MODE_SEL bit selects whether the hours registers use 12- or 24-hour format. 0 = RTC hours registers use 12-hour format. The AM/PM bit of each hours register represents PM when 1 and AM when 0. 1 = RTC hours registers use 24-hour format. Neither internal functions nor RTC-only resets affect this bit. The RTCCURHR (page 17-8) and RTCALMHR (page 17-9) registers must be reinitialized after software changes the HOUR_MODE_SEL bit. Software should set the SET bit to 1 before changing the HOUR_MODE_SEL bit and then clear the SET bit afterward. 0 DS_ENB Daylight Savings Enable The DS_ENB bit enables special daylight savings time updates. 0 = Special daylight savings time updates do not occur. 1 = Two special time updates occur automatically when this bit is 1. On the first Sunday in April, the time reading that follows 1:59:59 AM is 3:00:00 AM. On the last Sunday in October, the time reading that follows 1:59:59 AM is 1:00:00 AM. Neither internal functions nor RTC-only resets affect this bit. Software should set the SET bit to 1 before changing the DS_ENB bit and then clear the SET bit afterward. Programming Notes ElanTMSC520 Microcontroller Register Set Manual 17-17 Real-Time Clock Registers RTC Status C (RTCSTAC) I/O Address 70h/71h RTC Index 0Ch 7 Bit Reset R/W 6 PER_ INT_FLG x R! 5 ALM_ INT_FLG x 4 UPD_ INT_FLG x 3 2 Reserved 1 0 INT_FLG 0 0 0 RSV 0 0 Register Description The RTC Status C provides RTC interrupt status. Bit Definitions Bit 7 Name INT_FLG Function Interrupt Request Flag 0 = The RTC interrupt request to the programmable interrupt controller (PIC) is driven inactive. 1 = When this bit transitions from 0 to 1, the RTC interrupt request to the PIC is driven active, which generates a CPU interrupt if the RTC interrupt source is enabled at the PIC. The INT_FLG bit is set to 1 when any one (or more) of the PER_INT_FLG, ALM_INT_FLG, or UPD_INT_FLG bits transition from 0 to 1 while the corresponding enable bit is asserted in the RTCCTLB register (see page 17-16). The INT_FLG bit is also set to 1 if an RTC interrupt source enable bit is written to 1 when the associated flag bit is already asserted. The INT_FLG bit is cleared after read, and is also cleared by an RTC-only reset. If the internal RTC is disabled (via the RTC_DIS bit in the ADDDECCTL register, see page 2-3), the internal signal associated with the INT_FLG status bit is not automatically disconnected from the PIC. If the intent is to use an external RTC to drive the RTC interrupt request, then all internal RTC interrupt enables (bits PER_INT_ENB, ALM_INT_ENB, and UPD_INT_ENB) must be cleared in the RTCCTLB register prior to disabling the internal RTC (see page 17-16). 6 PER_INT_FLG Periodic Interrupt Flag 0 = An RTC periodic event has not occurred since this bit was cleared. This bit is cleared after read and is also cleared by an RTC-only reset. 1 = An RTC periodic event has occurred. This bit is set when an RTC periodic event occurs regardless of the state of its interrupt enable bit (the PER_INT_ENB bit in the RTCCTLB register, page 17-16). The periodic interrupt rate is configured with the RATE_SEL bit field in the RTCCTLA register (see page 17-15). 5 ALM_INT_FLG Alarm Interrupt Flag 0 = An RTC alarm event has not occurred since this bit was cleared. This bit is cleared after read and is also cleared by an RTC-only reset. 1 = An RTC alarm event has occurred. This bit is set when an RTC alarm event occurs regardless of the state of its interrupt enable bit (the ALM_INT_ENB bit in the RTCCTLB register, page 17-16). Alarm events can only occur with a time resolution of one second. An alarm event occurs when the current time contained in the RTCCURSEC, RTCCURMIN, and RTCCURHR registers is equal to the alarm setting configured in the RTCALMSEC, RTCALMMIN, and RTCALMHR registers (see page 17-4 through page 17-9). The alarm time can contain wildcards for hour, minute, or second settings. A wildcard is any value from C0h to FFh. 17-18 ElanTMSC520 Microcontroller Register Set Manual Real-Time Clock Registers Bit 4 Name UPD_INT_FLG Function Update-Ended Interrupt Flag 0 = An RTC update-ended event has not occurred since this bit was cleared. This bit is cleared after read, and is also cleared by an RTC-only reset. 1 = An RTC update-ended event has occurred. This bit is set upon termination of each time/date update cycle. 3-0 Reserved Reserved This bit field should be written to 0 for normal system operation. Programming Notes ElanTMSC520 Microcontroller Register Set Manual 17-19 Real-Time Clock Registers RTC Status D (RTCSTAD) I/O Address 70h/71h RTC Index 0Dh 7 Bit Reset R/W 6 5 4 3 Reserved 2 1 0 RTC_VRT ? R 0 0 0 0 RSV 0 0 0 Register Description The RTC Status D register provides RTC voltage monitor status. Bit Definitions Bit 7 Name RTC_VRT Function Valid RAM and Time The Valid RAM and Time (RTC_VRT) bit is used to determine the validity of the RTC time, date and CMOS RAM registers. 0 = Indicates that the RTC backup battery, as sensed by the microcontroller's BBATSEN pin, was below a fixed reference voltage prior to the application of main system power. (See the ElanTMSC520 Microcontroller Data Sheet, order #22003, for the RTC voltage monitor reference voltage.) Because the RTC reference voltage is too low to keep the RTC logic operational, the RTC date, time, and CMOS RAM are invalid, and the microcontroller performed an RTC-only reset as a result. An RTC-only reset clears this latched status bit. 1 = Reading this bit causes it to be set to 1, and it remains set until an RTC-only reset occurs. Note that this bit is not a real-time indication of the state of the external RTC backup battery, although there can be a relationship. For example, if the RTC backup battery is removed while main system power is still applied, this bit still reads back 1 until main system power is cycled. This bit is always set to 0 upon RTC-only reset. This bit is always set to 1 after an initial read to this register is performed. This bit remains set to 1 until an RTC-only reset occurs. RTConly reset occurs any time the BBATSEN input is sampled to be below the RTC reference voltage during a power-on reset. 6-0 Reserved Reserved This bit field should be written to 0 for normal system operation. Programming Notes The default value for this register (RTCSTAD) depends on whether an RTC-only reset has occurred. The RTC-only reset occurs when the BBATSEN input is sampled to be below the RTC reference voltage prior to a power-on system reset. See the ElanTMSC520 Microcontroller Data Sheet, order #22003, for the RTC voltage monitor reference voltage. 17-20 ElanTMSC520 Microcontroller Register Set Manual Real-Time Clock Registers General-Purpose CMOS RAM (114 bytes) (RTCCMOS) I/O Address 70h/71h RTC Indexes 0E-7Fh 7 Bit Reset R/W 6 5 4 3 2 1 0 RTC_CMOS_REG_X[7-0] x x x x R/W x x x x Register Description These registers are the general-purpose CMOS RAM registers. Bit Definitions Bit 7-0 Name RTC_CMOS_ REG_X[7-0] Function CMOS RAM Location These are 114 bytes of general-purpose, battery-backed (nonvolatile) CMOS RAM available for use by system software, applications, etc. In a PC/AT-compatible system, many of these bytes can be used by the system BIOS. The number of bytes used and the meaning of data stored in a given CMOS RAM byte location can vary between different BIOS vendors or even between different versions of a single BIOS. Accesses to CMOS RAM locations can be performed without any regard for RTC operations. For example, DATE_MODE bit has no effect on CMOS RAM data. If the RTC is disabled (via the RTC_DIS bit in the ADDDECCTL register, see page 2-3), the CMOS RAM is unavailable, but not lost (unless both main and backup power to the internal RTC is removed). Re-enabling the RTC allows access to the CMOS RAM with its contents intact. Programming Notes ElanTMSC520 Microcontroller Register Set Manual 17-21 Real-Time Clock Registers 17-22 ElanTMSC520 Microcontroller Register Set Manual CHAPTER 18 18.1 UART SERIAL PORT REGISTERS OVERVIEW This chapter describes the universal asynchronous receiver/transmitter (UART) registers of the ELANSC520 microcontroller. The ELANSC520 microcontroller includes two industry-standard 16550-compatible UARTs. The UART register set includes two groups of registers: s Six memory-mapped configuration region (MMCR) registers are used to configure and control UART functions specific to the ELANSC520 microcontroller. s 24 direct-mapped I/O registers are used for industry-standard UART configuration, control, and status functions. See the ElanTMSC520 Microcontroller User's Manual, order #22004, for details about the UARTs. Table 18-1 and Table 18-2 list each type of UART register in offset order, with the corresponding description's page number. 18.2 Table 18-1 REGISTERS UART MMCR Registers Register Name UART 1 General Control UART 1 General Status UART 1 FIFO Control Shadow UART 2 General Control UART 2 General Status UART 2 FIFO Control Shadow Mnemonic UART1CTL UART1STA UART1FCRSHAD UART2CTL UART2STA UART2FCRSHAD MMCR Offset CC0h CC1h CC2h CC4h CC5h CC6h Page Number page 18-3 page 18-4 page 18-5 page 18-3 page 18-4 page 18-5 Table 18-2 UART Direct-Mapped Registers Register Name UART 2 Transmit Holding UART 2 Receive Buffer Mnemonic UART2THR UART2RBR I/O Address 02F8h 02F8h 02F8h 02F9h 02F9h 02FAh 02FAh 02FBh 02FCh 02FDh 02FEh Page Number page 18-7 page 18-8 page 18-9 page 18-10 page 18-11 page 18-12 page 18-15 page 18-17 page 18-19 page 18-21 page 18-23 UART 2 Baud Clock Divisor Latch LSB UART2BCDL UART 2 Baud Clock Divisor Latch MSB UART2BCDH UART 2 Interrupt Enable UART 2 Interrupt ID UART 2 FIFO Control UART 2 Line Control UART 2 Modem Control UART 2 Line Status UART 2 Modem Status UART2INTENB UART2INTID UART2FCR UART2LCR UART2MCR UART2LSR UART2MSR ElanTMSC520 Microcontroller Register Set Manual 18-1 UART Serial Port Registers Table 18-2 UART Direct-Mapped Registers (Continued) Register Name UART 2 Scratch Pad UART 1 Transmit Holding UART 1 Receive Buffer Mnemonic UART2SCRATCH UART1THR UART1RBR I/O Address 02FFh 03F8h 03F8h 03F8h 03F9h 03F9h 03FAh 03FAh 03FBh 03FCh 03FDh 03FEh 03FFh Page Number page 18-25 page 18-7 page 18-8 page 18-9 page 18-10 page 18-11 page 18-12 page 18-15 page 18-17 page 18-19 page 18-21 page 18-23 page 18-25 UART 1 Baud Clock Divisor Latch LSB UART1BCDL UART 1 Baud Clock Divisor Latch MSB UART1BCDH UART 1 Interrupt Enable UART 1 Interrupt ID UART 1 FIFO Control UART 1 Line Control UART 1 Modem Control UART 1 Line Status UART 1 Modem Status UART 1 Scratch Pad UART1INTENB UART1INTID UART1FCR UART1LCR UART1MCR UART1LSR UART1MSR UART1SCRATCH 18-2 ElanTMSC520 Microcontroller Register Set Manual UART Serial Port Registers Memory-Mapped UART 1 General Control (UART1CTL) UART 2 General Control (UART2CTL) MMCR Offset CC0h MMCR Offset CC4h 7 Bit Reset R/W 6 5 Reserved 4 3 2 CLK_SRC 1 0 RXTC_ENB TXTC_ENB 0 R/W 0 R/W 0 0 0 RSV 0 0 0 R/W Register Description This register is used to enable or disable the transmit and receive transfer count (TC) interrupt and also select from two internal baud-rate clock sources. Bit Definitions Bit 7-3 2 Name Reserved CLK_SRC Function Reserved This bit field should be written to 0 for normal system operation. UART x Clock Source Enable 0 = 18.432 MHz 1 = 1.8432 MHz UART x Receive TC Interrupt Enable 0 = Receive TC interrupt disable 1 = Receive TC interrupt enable UART x Transmit TC Interrupt Enable 0 = Transmit TC interrupt disable 1 = Transmit TC interrupt enable 1 RXTC_ENB 0 TXTC_ENB Programming Notes Each UART can generate an interrupt when the transfer count (GPTC) signal associated with DMA transfers is asserted. Table 18-5 on page 18-14 provides a summary of UART interrupt sources. ElanTMSC520 Microcontroller Register Set Manual 18-3 UART Serial Port Registers Memory-Mapped UART 1 General Status (UART1STA) UART 2 General Status (UART2STA) MMCR Offset CC1h MMCR Offset CC5h 7 Bit Reset R/W 6 5 Reserved 4 3 2 1 0 RXTC_DET TXTC_DET 0 0 0 0 R/W! 0 R/W! 0 0 0 RSV Register Description This register shows the status of transfer count (TC) interrupt detected for the UART. These bits are cleared by writing a 1 to them. Bit Definitions Bit 7-2 1 Name Reserved RXTC_DET Function Reserved This bit field should be written to 0 for normal system operation. UART x Receive TC Detected When reading: 0 = TC not detected 1 = TC detected This bit is cleared by writing a 1. 0 TXTC_DET UART x Transmit TC Detected When reading: 0 = TC not detected 1 = TC detected This bit is cleared by writing a 1. Programming Notes Each UART can generate an interrupt when the transfer count (GPTC) signal associated with DMA transfers is asserted. Table 18-5 on page 18-14 provides a summary of UART interrupt sources. 18-4 ElanTMSC520 Microcontroller Register Set Manual UART Serial Port Registers Memory-Mapped UART 1 FIFO Control Shadow (UART1FCRSHAD) UART 2 FIFO Control Shadow (UART2FCRSHAD) MMCR Offset CC2h MMCR Offset CC6h 7 Bit Reset R/W 6 RFRT[1-0] 5 Reserved 4 3 DMA_ MODE 2 TF_CLR 0 R 1 RF_CLR 0 R 0 FIFO_ENB 0 R 0 R 0 0 RSV 0 0 R Register Description This register is provided for reading the information written to the UART x FIFO Control (UARTxFCR) register (see page 18-15), because the UARTxFCR register is write-only. Writing to this shadow register has no effect. Bit Definitions Bit 7-6 Name RFRT[1-0] Function Receiver FIFO Register Trigger Bits In 16550-compatible mode, this bit field specifies the trigger level at which the INT_ID bit field in the UARTxINTID register (see page 18-13) reports that a received data available interrupt is pending. If received data available interrupts are enabled in the UARTxINTENB register (page 18-11), the system is interrupted when the receive FIFO fills to the trigger level as follows: 00 = 1 byte 01 = 4 bytes 10 = 8 bytes 11 = 14 bytes When the data in the receive FIFO falls below the specified trigger level, the interrupt is cleared. 5-4 3 Reserved DMA_MODE Reserved This bit field should be written to 0 for normal system operation. DMA Mode This bit is valid only in 16550-compatible mode. In 16450-compatible mode, the DMA operation is defined as if this bit were set to 0. 0 = The internal rxdrq signal to the DMA controller goes High when there is at least one character in the receiver FIFO or the UARTx Receive Buffer register (see page 18-8). The internal txdrq signal goes High when the transmitter FIFO (16550-compatible mode) or the UARTx Transmit Holding register (page 18-7) (16450-compatible mode) is not full. 1 = The internal rxdrq signal goes High when the trigger level or the time-out has been reached, and then it goes inactive when there are no more characters in the FIFO or holding register. For transmit, the internal txdrq signal goes High when the transmitter FIFO is not full and remains High until the transmitter FIFO is completely full. 2 1 TF_CLR RF_CLR Transmitter FIFO Clear Because the direct-mapped version of this bit is self-clearing, it always reads back 0. Receiver FIFO Clear Because the direct-mapped version of this bit is self-clearing, it always reads back 0. ElanTMSC520 Microcontroller Register Set Manual 18-5 UART Serial Port Registers Bit 0 Name FIFO_ENB Function FIFO Enabled (16550-Compatible Mode Enabled) 0 = The UART is in 16450-compatible mode. Accesses to receive and transmit FIFOs and to all FIFO control bits (except FIFO_ENB) in the write-only UART x FIFO Control (UARTxFCR) register are disabled (see page 18-15). 1 = The UART is in 16550-compatible mode. Accesses to receive and transmit FIFOs and to all FIFO control bits in the write-only UARTxFCR register are enabled. This bit must be 1 when other UARTxFCR register bits are written to or they cannot be programmed. Any mode switch clears both FIFOs. Programming Notes UARTxFCRSHAD is a shadow register for the write-only UART x FIFO Control (UARTxFCR) register (see page 18-15). 18-6 ElanTMSC520 Microcontroller Register Set Manual UART Serial Port Registers Direct-Mapped UART 2 Transmit Holding (UART2THR) UART 1 Transmit Holding (UART1THR) I/O Address 02F8h I/O Address 03F8h 7 Bit Reset R/W 6 5 4 THR[7-0] 3 2 1 0 0 0 0 0 W! 0 0 0 0 Register Description This is a write-only register used to write data to be transmitted. This register can be accessed only when the DLAB bit is 0 in the UARTxLCR register (see page 18-17). Bit Definitions Bit 7-0 Name THR[7-0] Function UART x Transmit Holding Register When the DLAB bit is 0 in the UART x Line Control (UARTxLCR) register (see page 18-17) and the THRE bit is 1 in the UART x Line Status (UARTxLSR) register (see page 18-21), writing a byte to this bit field causes the byte to be transmitted. Programming Notes When the DLAB bit is 0 in the UARTxLCR register (see page 18-17), reads from this address access the UART x Receive Buffer (UARTxRBR) register (see page 18-8), and writes to this address access the UART x Transmit Holding (UARTxTHR) register. When the DLAB bit is 1 in the UARTxLCR register, reads from and writes to this address access the UART x Baud Clock Divisor Latch LSB (UARTxBCDL) register (see page 18-9). ElanTMSC520 Microcontroller Register Set Manual 18-7 UART Serial Port Registers Direct-Mapped UART 2 Receive Buffer (UART2RBR) UART 1 Receive Buffer (UART1RBR) I/O Address 02F8h I/O Address 03F8h 7 Bit Reset R/W 6 5 4 RBR[7-0] 3 2 1 0 0 0 0 0 R! 0 0 0 0 Register Description This is a read-only register used to read received data. This register can be accessed only when the DLAB bit is 0 in the UARTxLCR register (see page 18-17). Bit Definitions Bit 7-0 Name RBR[7-0] Function UART x Receive Buffer When the DLAB bit is 0 in the UART x Line Control (UARTxLCR) register (see page 18-17) and the DR bit is 1 in the UART x Line Status (UARTxLSR) register (see page 18-21), this bit field contains valid data received over the serial line. Reading this bit field returns the last byte received (in 16450-compatible mode) or the head of the receive FIFO (in 16550-compatible mode). Programming Notes When the DLAB bit is 0 in the UARTxLCR register (see page 18-17), reads from this address access the UART x Receive Buffer (UARTxRBR) register, and writes to this address access the UART x Transmit Holding (UARTxTHR) register (see page 18-7). When the DLAB bit is 1 in the UARTxLCR register, reads from and writes to this address access the UART x Baud Clock Divisor Latch LSB (UARTxBCDL) register (see page 18-9). 18-8 ElanTMSC520 Microcontroller Register Set Manual UART Serial Port Registers Direct-Mapped UART 2 Baud Clock Divisor Latch LSB (UART2BCDL) UART 1 Baud Clock Divisor Latch LSB (UART1BCDL) I/O Address 02F8h I/O Address 03F8h 7 Bit Reset R/W 6 5 4 DIV[7-0] 3 2 1 0 0 0 0 0 R/W 0 0 0 0 Register Description This register contains bits DIV[7-0] of the16-bit baud-rate clock divisor used to generate the 16x baud clock. The baud-rate clock divisor can only be accessed when the DLAB bit is 1 in the UARTxLCR register (see page 18-17). The DIV[15-8] bits are located in the UARTxBCDH register (see page 18-10). Bit Definitions Bit 7-0 Name DIV[7-0] Function UART x Baud Clock Divisor Latch When the DLAB bit is 1 in the UARTxLCR register (see page 18-17), this bit field holds the least significant byte of a 16-bit baud-rate clock divisor that is used to generate the 16x baud clock. Programming Notes Setting the DIV[15-0] bit field to 0000h is not supported. When the DLAB bit is 0 in the UARTxLCR register (see page 18-17), reads from this address access the UART x Receive Buffer (UARTxRBR) register (see page 18-8), and writes to this address access the UART x Transmit Holding (UARTxTHR) register (see page 18-7). When the DLAB bit is 1 in the UARTxLCR register, reads from and writes to this address access the UART x Baud Clock Divisor Latch LSB (UARTxBCDL) register. The clock source frequency is selected by the CLK_SRC bit in the UARTxCTL register (see page 18-3). Table 183 lists the divisor value (in decimal and hexadecimal) to use with each clock frequency to achieve common baud rates. Table 18-3 Baud Rates, Divisors, and Clock Source Baud Rate 300 baud 600 baud 2400 baud 4800 baud 7200 baud 9600 baud 14.4 kbaud 19.2 kbaud 57.6 kbaud 115.2 kbaud 144 kbaud 192 kbaud 288 kbaud 576 kbaud 1.152 Mbaud DIV[15-0] (Decimal) 1.8432 MHz 18.432 MHz 384d 3840d 192d 1920d 48d 480d 24d 240d 16d 160d 12d 120d 8d 80d 6d 60d 2d 20d 1d 10d 8d 6d 4d 2d 1d DIV[15-0] (Hexadecimal) 1.8432 MHz 18.432 MHz 0180h 0F00h 00C0h 0780h 0030h 01E0h 0018h 00F0h 000Fh 00A0h 000Ch 0078h 0008h 0050h 0006h 003Ch 0002h 0014h 0001h 000Ah 0008h 0006h 0004h 0002h 0001h ElanTMSC520 Microcontroller Register Set Manual 18-9 UART Serial Port Registers Direct-Mapped UART 2 Baud Clock Divisor Latch MSB (UART2BCDH) UART 1 Baud Clock Divisor Latch MSB (UART1BCDH) I/O Address 02F9h I/O Address 03F9h 7 Bit Reset R/W 6 5 4 DIV[15-8] 3 2 1 0 0 0 0 0 R/W 0 0 0 0 Register Description This register contains bits DIV[15-8] of the16-bit baud-rate clock divisor used to generate the 16x baud clock. The baud-rate clock divisor can only be accessed when the DLAB bit is 1 in the UARTxLCR register (see page 18-17). The DIV[7-0] bits are located in the UARTxBCDL register (see page 18-9). Bit Definitions Bit 7-0 Name DIV[15-8] Function UART x Baud Clock Divisor Latch When the DLAB bit is 1 in the UARTxLCR register (see page 18-17), this bit field holds the most significant byte of the 16-bit baud-rate clock divisor that is used to generate the 16x baud clock. Programming Notes Setting the DIV[15-0] bit field to 0000h in the UARTxBCDL and UARTxBCDH registers is not supported. When the DLAB bit is 0 in the UARTxLCR register (see page 18-17), reads from and writes to this address access the UART x Interrupt Enable (UARTxINTENB) register (see page 18-11). When the DLAB bit is 1 in the UARTxLCR register, reads from and writes to this address access the UART x Baud Clock Divisor Latch MSB (UARTxBCDH) register. The clock source frequency is selected by the CLK_SRC bit in the UARTxCTL register (see page 18-3). Table 183 on page 18-9 lists the divisor value (in decimal and hexadecimal) to use with each clock frequency to achieve common baud rates. 18-10 ElanTMSC520 Microcontroller Register Set Manual UART Serial Port Registers Direct-Mapped UART 2 Interrupt Enable (UART2INTENB) UART 1 Interrupt Enable (UART1INTENB) I/O Address 02F9h I/O Address 03F9h 7 Bit Reset R/W 6 Reserved 5 4 3 EMSI 2 ERLSI 0 R/W 1 ETHREI 0 R/W 0 ERDAI 0 R/W 0 0 RSV 0 0 0 R/W Register Description This register enables the following serial port interrupts: modem status, receiver line status, transmitter holding register empty, received data available, and time-out interrupt. This register can be accessed only when the DLAB bit is 0 in the UARTxLCR register (see page 18-17). Each interrupt can individually activate the interrupt request signal. Bit Definitions Bit 7-4 3 Name Reserved EMSI Function Reserved This bit field should be written to 0 for normal system operation. Enable Modem Status Interrupt 0 = Disable modem status interrupt. 1 = Enable modem status interrupt. Enable Receiver Line Status Interrupt 0 = Disable receiver line status interrupt. 1 = Enable receiver line status interrupt. Enable Transmitter Holding Register Empty Interrupt 0 = Disable transmitter holding register empty interrupt. 1 = Enable transmitter holding register empty interrupt. Enable Received Data Available Interrupt 0 = Disable data available interrupt in 16450-compatible mode; in 16550-compatible mode, disable FIFO trigger level reached interrupt and time-out interrupt. 1 = Enable received data available interrupt in 16450-compatible mode; in 16550-compatible mode, this bit also enables FIFO trigger level reached interrupt and time-out interrupt. More detail on time-out interrupts can be found in the UARTxINTID register description (page 18-12). 2 ERLSI 1 ETHREI 0 ERDAI Programming Notes Table 18-5 on page 18-14 provides a summary of UART interrupt sources. When the DLAB bit is 0 in the UARTxLCR register (see page 18-17), reads from and writes to this address access the UART x Interrupt Enable (UARTxINTENB) register. When the DLAB bit is 1 in the UARTxLCR register, reads from and writes to this address access the UART x Baud Clock Divisor Latch MSB (UARTxBCDH) register (see page 18-10). ElanTMSC520 Microcontroller Register Set Manual 18-11 UART Serial Port Registers Direct-Mapped UART 2 Interrupt ID (UART2INTID) UART 1 Interrupt ID (UART1INTID) I/O Address 02FAh I/O Address 03FAh 7 Bit Reset R/W 6 5 Reserved 0 RSV 4 3 2 INT_ID[2-0] 1 0 INT_NOT_ PND FIFO_MODE[1-0] 0 R 0 R 0 0 R 0 R 0 R 1 R Register Description This read-only register is used to identify UART interrupts and the current FIFO mode. Writes to this address access the UART x FIFO Control (UARTxFCR) register (see page 18-15). Bit Definitions Bit 7-6 Name FIFO_MODE [1-0] Function FIFO Mode Indication FIFO is only present when 16550-compatible mode is enabled: 00 = 16450-compatible mode is enabled 01 = No significance 10 = No significance 11 = 16550-compatible mode is enabled The FIFO mode is selected by the FIFO_ENB bit in the UARTxFCR register (see page 18-16). 5-4 Reserved Reserved These bits always read back 00b. 18-12 ElanTMSC520 Microcontroller Register Set Manual UART Serial Port Registers Bit 3-1 Name INT_ID[2-0] Function Interrupt Identification Bit Field The INT_ID bit field indicates only the highest priority interrupt (as defined in Table 18-4) when two interrupt sources are pending simultaneously. When the interrupt source is cleared, a subsequent read from the INT_ID bit field returns the next highest priority interrupt source. The INT_ID bit field has no meaning if the INT_NOT_PND bit is 1. Table 18-4 INT_ID Bit Field 000b 001b 010b 011b 100b 101b 110b 111b UART Interrupt Identification and Priority Description Modem status Transmit holding register empty (16540-compatible mode)/Transmit FIFO empty (16550-compatible mode) Received data available (16540-compatible mode)/ Receiver FIFO trigger (16550-compatible mode) Receive line status Not used Not used FIFO time-out Not used Identification Priority Fourth (Lowest) Third Second First (Highest) -- -- Second -- In 16450-compatible mode, the INT_ID[2] bit always reads back 0. A receiver FIFO trigger occurs when the data in the receive FIFO fills to the level set in the RFRT bit field of the UARTxFCR register (see page 18-15). A FIFO time-out occurs when the receive FIFO is not empty, and more than four continuous character times have elapsed without more data being placed into or read out of the receive FIFO. Reading a character from the receive FIFO clears the time-out interrupt. See the UARTxLSR and UARTxMSR register descriptions on page 18-21 and page 18-23 for information about the other interrupt events identified by the INT_ID bit field. 0 INT_NOT_ PND No Serial Port Interrupt Pending 0 = Interrupt pending 1 = No Interrupt pending Programming Notes Table 18-5 on page 18-14 provides a summary of UART interrupt sources. Interrupts generated by the UART are cleared in a variety of ways, depending on the source event. For details about clearing a particular event, see the event's status bit description. Table 18-5 on page 18-14 lists interrupt status registers and bits. For additional information, see the ElanTMSC520 Microcontroller User's Manual, order #22004. ElanTMSC520 Microcontroller Register Set Manual 18-13 UART Serial Port Registers Table 18-5 UART Interrupt Programming Summary Enable Register1, 2 UARTxCTL, page 18-3 UARTxINTENB, page 18-11 Status Register3 UARTxSTA, page 18-4 UARTxMSR, page 18-23 Source Event UART x Receive TC Detected UART x Transmit TC Detected Delta data carrier detect Trailing edge ring indicator Delta data set ready Delta clear to send Polled Status Bit RXTC_DET TXTC_DET DDCD TERI DDSR DCTS BI FE PE OE THRE Interrupt Description Receive DMA transfer count Transmit DMA transfer count Modem status change Receiver line status UARTxLSR, page 18-21 Break indicator Framing error Parity error Overrun error Transmitter holding register empty Received data available --4 FIFO time-out5 Transmit holding register (16450compatible mode) or transmitter FIFO (16550-compatible mode) empty Data ready (16450-compatible mode) FIFO trigger level reached (16550-compatible mode) FIFO time-out (16550-compatible mode) DR -- -- Notes: 1. Before any UART interrupt is enabled, the corresponding UARTxMAP register (see page 12-21) must be configured to route the interrupt to the appropriate interrupt request level and priority. 2. The OUT2 bit in the UARTxMCR register (page 18-19) is used as a master control for UART interrupts. The OUT2 bit must be set for UART interrupts to be generated. Status bits can be read even when interrupts are disabled. 3. If two of the interrupts enabled in the UARTxINTENB register are pending simultaneously, the highest-priority interrupt is identified in the INT_ID bit field of the UARTxINTID register (see page 18-13). 4. There are no polled-status bits for the FIFO trigger level and FIFO time-out events. These events are indicated by the INT_ID bit field only (see page 18-13). 5. The FIFO time-out interrupt is enabled with the received data available interrupt by the ERDAI bit in the UARTxINTENB register (see page 18-11). 18-14 ElanTMSC520 Microcontroller Register Set Manual UART Serial Port Registers Direct-Mapped UART 2 FIFO Control (UART2FCR) UART 1 FIFO Control (UART1FCR) I/O Address 02FAh I/O Address 03FAh 7 Bit Reset R/W 6 RFRT[1-0] 5 Reserved 4 3 DMA_ MODE 2 TF_CLR 0 W 1 RF_CLR 0 W 0 FIFO_ENB 0 W 0 W 0 W 0 RSV 0 0 W Register Description This is a write-only register used to enable and control the FIFO in 16550-compatible mode. Reads to this address access the UART x Interrupt ID (UARTxINTID) register (see page 18-12). Bit Definitions Bit 7-6 Name RFRT[1-0] Function Receiver FIFO Register Trigger Bits In 16550-compatible mode, this bit field specifies the trigger level at which the INT_ID bit field in the UARTxINTID register (see page 18-13) reports that a received data available interrupt is pending. If received data available interrupts are enabled in the UARTxINTENB register (page 18-11), the system is interrupted when the receive FIFO fills to the trigger level as follows: 00 = 1 byte 01 = 4 bytes 10 = 8 bytes 11 = 14 bytes When the data in the receive FIFO falls below the specified trigger level, the interrupt is cleared. 5-4 3 Reserved DMA_MODE Reserved These bits should be written to 0 for normal system operation. DMA Mode This bit is valid only in 16550-compatible mode. In 16450-compatible mode, the DMA operation is defined as if this bit were set to 0. 0 = The internal rxdrq signal to the DMA controller goes High when there is at least one character in the receiver FIFO or the UARTx Receive Buffer register (see page 18-8). The txdrq signal goes High when the transmitter FIFO (16550-compatible mode) or the UARTx Transmit Holding register (page 18-7) (16450-compatible mode) is not full. 1 = The internal rxdrq signal goes High when the trigger level or the time-out has been reached, and then it goes inactive when there are no more characters in the FIFO or holding register. For transmit, the txdrq signal goes High when the transmitter FIFO is not full and remains High until the transmitter FIFO is completely full. 2 TF_CLR Transmitter FIFO Clear 0 = Writing a 0 to this bit has no effect. This bit is self-clearing and does not need to be reset by software. 1 = Writing a 1 to this bit position clears the transmit FIFO and resets the transmit FIFO counter logic. It does not clear the transmitter shift register. 1 RF_CLR Receiver FIFO Clear 0 = Writing a 0 to this bit has no effect. This bit is self-clearing and does not need to be reset by software. 1= Writing a 1 to this bit position clears the receive FIFO and resets the receive FIFO counter logic. It does not clear the receive shift register. ElanTMSC520 Microcontroller Register Set Manual 18-15 UART Serial Port Registers Bit 0 Name FIFO_ENB Function FIFO Enable 0 = Causes the UART to enter 16450-compatible mode. Disables accesses to receive and transmit FIFOs and all FIFO control bits, except this bit. 1 = Causes the UART to enter 16550-compatible mode. Enables receive and transmit FIFO buffers, and enables accesses to other FIFO control bits. Programming Notes The contents of this write-only register can be read back via the UART x FIFO Control Shadow (UARTxFCRSHAD) register (see page 18-5). 18-16 ElanTMSC520 Microcontroller Register Set Manual UART Serial Port Registers Direct-Mapped UART 2 Line Control (UART2LCR) UART 1 Line Control (UART1LCR) I/O Address 02FBh I/O Address 03FBh 7 Bit Reset R/W 6 SB 0 R/W 5 SP 0 R/W 4 EPS 0 R/W 3 PENB 0 R/W 2 STP 0 R/W 1 WLS[1-0] 0 R/W 0 DLAB 0 R/W 0 Register Description This register is used to configure the format of the UART frame for data transfer, including character length, stop bits, and parity. The DLAB bit is used to gain access to the baud-rate divisor latches or the UARTxTHR and UARTxRBR registers. Bit Definitions Bit 7 Name DLAB Function Divisor Latch Access 0 = Software can access the transmit holding, receive buffer, and interrupt enable registers: UARTxTHR (page 18-7), UARTxRBR (page 18-8), and UARTxINTENB (page 18-11). 1 = Software can access the baud rate divisor latch registers: UARTxBCDL (page 18-9) and UARTxBCDH (page 18-10). 6 SB Set Break Enable Setting this bit causes a break condition to be transmitted to the receiving UART. 0 = Disable set break. 1 = Force serial output to spacing state (logic 0) regardless of other transmitter activity. The break control acts on the SOUTx pin only and has no other effect on the transmitter logic. 5 SP Stick Parity Enable Stick parity forces the parity bit to be always 0 or 1. 0 = Stick Parity is disabled. If parity is enabled (by the PENB bit), normal parity is used: the parity bit dynamically changes so the number of 1 bits in the transmitted data is always odd or even (depending on the EPS bit). 1 = Stick Parity is enabled. If parity is enabled, the parity bit is always 0 or 1. If bits SP, EPS, and PENB are 1, the parity bit is generated and checked as 0. If bits SP and PENB are 1 and EPS is 0, the parity bit is generated and checked as 1. 4 EPS Even Parity Select Parity must be enabled via the PENB bit for this bit to have meaning: 0 = Odd parity. The parity bit is manipulated to force an odd number of 1 bits in the transmitted data and the same condition is checked for in the received data. 1 = Even parity. The parity bit is manipulated to force an even number of 1 bits in the transmitted data and the same condition is checked for in the received data. Start and stop bits are not included in the parity generation and checking scheme. 3 PENB Parity Enable 0 = Parity is disabled. 1 = Parity is enabled. A parity bit is generated in the transmitted data and checked in the received data. The parity bit is located between the last data-word bit and the first stop bit in the bit stream. ElanTMSC520 Microcontroller Register Set Manual 18-17 UART Serial Port Registers Bit 2 Name STP Function Stop Bits This bit sets the number of stop bits used, based on the character length set in the WSL bit field: If WSL = 00b (5-bit words): 0 = 1 stop bit 1 = 1.5 stop bits If WSL = 01-11b (6-, 7-, or 8-bit words): 0 = 1 stop bit 1 = 2 stop bits 1-0 WLS[1-0] Transmit/Receive Word Length Select This bit field sets the UART data word length. 00 = 5 bits 01 = 6 bits 10 = 7 bits 11 = 8 bits Programming Notes 18-18 ElanTMSC520 Microcontroller Register Set Manual UART Serial Port Registers Direct-Mapped UART 2 Modem Control (UART2MCR) UART 1 Modem Control (UART1MCR) I/O Address 02FCh I/O Address 03FCh 7 Bit Reset R/W 6 Reserved 5 4 LOOP 3 OUT2 0 R/W 2 OUT1 0 R/W 1 RTS 0 R/W 0 DTR 0 R/W 0 0 RSV 0 0 R/W Register Description This register is used to control the interface with the modem or peripheral device. It is used to enable interrupts from the UART, enable loopback diagnostic mode, or assert RTSx or DTRx. Bit Definitions Bit 7-5 4 Name Reserved LOOP Function Reserved This bit field should be written to 0 for normal system operation. Loopback Mode (Diagnostic Mode) Enable 0 = Loopback mode is disabled 1 = Loopback mode is enabled The following internal connections are made by setting this diagnostic bit: RTSx is internally connected to CTSx. DTRx is internally connected to DSRx. out1 is internally connected to RINx. out2 is internally connected to DCDx. Also, the SOUTx pin is driven High, the SIN input line is blocked, and interrupt generation to the PIC is disabled. The transmit shift register is directly connected to the receive shift register. In addition, the DTRx and RTSx signals, and the internal out1 and out2 signals are forced inactive. Modem status events (UARTxMSR register, see page 18-23) can be forced by setting the EMSI bit in the UARTxINTENB register (see page 18-11), and changing one of the bits OUT2, OUT1, RTS, or DTR in this register (UARTxMCR) in loopback mode. 3 OUT2 Enable UART x Interrupts This bit controls the internal out2 signal, which is used internally as a master enable for UART x interrupts when loopback mode is disabled. 0 = No UART x interrupt requests are sensed at the Programmable Interrupt Controller (PIC). 1 = UART x interrupt requests are enabled. In loopback mode, the internal out2 signal is internally connected to the DCDx signal, which can be read via the DCD bit in the UARTxMSR register (see page 18-23). 0 = In loopback mode, the out2 signal forces DCDx High (deasserted). 1 = In loopback mode, the out2 signal forces DCDx Low (asserted). 2 OUT1 out1 Control This bit controls the internal out1 signal, which is not used when loopback mode is disabled. It is provided for PC/AT compatibility and for use as part of the loopback diagnostics. 0 = In loopback mode, the out1 signal forces RINx High (deasserted). 1 = In loopback mode, the out1 signal forces RINx Low (asserted). In loopback mode, the internal out1 signal is internally connected to the RINx signal, which can be read via the RIN bit in the UARTxMSR register (see page 18-23). Other than that, the OUT1 bit has no effect on system operation and can be used as a scratch pad during normal system operation. ElanTMSC520 Microcontroller Register Set Manual 18-19 UART Serial Port Registers Bit 1 Name RTS Function Request To Send In normal operation (loopback mode disabled), this bit is the complement of the RTSx signal. 0 = RTSx is forced High, deasserting the signal. 1 = RTSx is forced Low, asserting the signal. In loopback mode, the RTSx signal is internally connected to the CTSx signal, which can be read via the CTS bit in the UARTxMSR register (see page 18-23). 0 DTR Data Terminal Ready In normal operation (loopback mode disabled), this bit is the complement of the DTRx signal. 0 = DTRx is forced High, deasserting the signal. 1 = DTRx is forced Low, asserting the signal. In loopback mode, the DTRx signal is internally connected to the DSRx signal, which can be read via the DSR bit in the UARTxMSR register (see page 18-23). Programming Notes 18-20 ElanTMSC520 Microcontroller Register Set Manual UART Serial Port Registers Direct-Mapped UART 2 Line Status (UART2LSR) UART 1 Line Status (UART1LSR) I/O Address 02FDh I/O Address 03FDh 7 Bit Reset R/W 6 TEMT 1 R! 5 THRE 1 R! 4 BI 0 R! 3 FE 0 R! 2 PE 0 R! 1 OE 0 R! 0 DR 0 R! ERR_IN_ FIFO 0 R! Register Description This read-only register shows the status of the data transfer, with indicators for transmitter or transmit holding register empty, break detected, framing error, parity error, overrun error, and received data ready. Bit Definitions Bit 7 Name ERR_IN_FIFO Function 16550-Compatible Mode Error 0 = In 16550-compatible mode, there is no parity error, framing error, or break condition in the receive FIFO. In 16450-compatible mode, this bit always reads back 0. 1 = At least one parity error, framing error or break condition is present in the receive FIFO (16550-compatible mode only). This bit is cleared by a read from this register (UARTxLSR) or by a read from the receiver FIFO when there are no more error conditions present in the FIFO. 6 TEMT Transmitter Empty Indicator 0 = The transmit shift register still has data to transmit. 1 = In 16450-compatible mode, both the transmit holding register and the transmit shift register are empty. In 16550-compatible mode, both the transmit FIFO and the transmit shift register are empty. 5 THRE Transmit Holding Register (16450-Compatible Mode) or Transmitter FIFO (16550Compatible Mode) Empty 0 = The transmitter still has data to place in the transmit shift register. 1 = In 16450-compatible mode, the transmit holding register is ready to accept a new character. In 16550-compatible mode, the transmit FIFO is completely empty. In 16450-compatible mode, this bit is automatically reset by a write to the UARTxTHR register (see page 18-7). In 16550-compatible mode, this interrupt is cleared when the transmit FIFO is written to. This bit can be used to generate an interrupt if programmed to do so via the Interrupt Enable register. 4 BI Break Indicator 0 = There is no break indication associated with the current character. 1 = In 16450-compatible mode, this bit is set when the UART has detected that the sending UART has transmitted a break condition for a period longer than the time it takes to receive start, data, parity and stop bits. In 16550-compatible mode, this bit is set when an entire word (start, data, parity, stop) that was received into the FIFO with break indication present is now at the top of the FIFO. Only one break indication is loaded into the FIFO regardless of the duration of the break condition. A new character is not loaded into the FIFO until the next valid start bit is detected. This latched status bit is automatically cleared by a read from this register (UARTxLSR). ElanTMSC520 Microcontroller Register Set Manual 18-21 UART Serial Port Registers Bit 3 Name FE Function Framing Error 0 = No framing error has been reported since line status was last read. 1 = In 16450-compatible mode, this bit is set to indicate that a received character did not have a valid stop bit. In 16550-compatible mode, this bit is set when a character that was received into the FIFO with a framing error is at the top of the receive FIFO. This latched status bit is automatically cleared by a read from this register (UARTxLSR). 2 PE Parity Error 0 = There is no parity error associated with the current character. 1 = In 16450-compatible mode, this bit is set upon receipt of data with incorrect parity. In 16550-compatible mode, this bit is set when a character that was received into the FIFO with bad parity is at the top of the receive FIFO. This latched status bit is automatically cleared by a read from this register (UARTxLSR). 1 OE Overrun Error 0 = No overrun error has been reported since line status was last read. 1 = In 16450-compatible mode, this bit is set if a new character is received into the receiver buffer before a previous character was read, thus resulting in lost data. In 16550compatible mode, this bit is set if a new character is completely received into the shift register when the FIFO is already 100% full. Data in the FIFO is not overwritten by this overrun. The data in the shift register is lost when the next character is received. This latched status bit is automatically cleared by a read from this register (UARTxLSR). 0 DR Data Ready 0 = There is no received data ready to read. 1 = In 16450-compatible mode, this bit is set when a character has been received and placed in the Receive Buffer register. In 16550-compatible mode, this bit is set when a character has been received and placed in the Receive FIFO. In 16450-compatible mode, this bit is automatically cleared by reading the UARTxRBR register (see page 18-8). In 16550-compatible mode, this bit is automatically cleared by reading the receiver FIFO, assuming that no more data is present in the FIFO. Programming Notes When a receiver line status interrupt is enabled and detected, bits BI, FE, PE, and OE in this register indicate the reason for the interrupt. The status bits are valid even when line status interrupts are not enabled. 18-22 ElanTMSC520 Microcontroller Register Set Manual UART Serial Port Registers Direct-Mapped UART 2 Modem Status (UART2MSR) UART 1 Modem Status (UART1MSR) I/O Address 02FEh I/O Address 03FEh 7 Bit Reset R/W 6 RI ? R 5 DSR ? R 4 CTS ? R 3 DDCD 0 R! 2 TERI 0 R! 1 DDSR 0 R! 0 DCTS 0 R! DCD ? R Register Description This read-only register contains both real-time and latched control line status bits for the UART's DCDx, RINx, DSRx and CTSx input signals. Bit Definitions Bit 7 Name DCD Function Data Carrier Detect In normal operation (loopback mode disabled), this bit is the complement of the DCDx signal. 0 = DCDx input signal is High (deasserted). 1 = DCDx input signal is Low (asserted). If in loopback mode, this bit tracks the OUT2 bit in the UARTxMCR register (see page 18-19). 6 RI Ring Indicator In normal operation (loopback mode disabled), this bit is the complement of the RINx signal. 0 = RINx input signal is High (deasserted). 1 = RINx input signal is Low (asserted). If in loopback mode, this bit tracks bit OUT1 bit in the UARTxMCR register (see page 18-19). 5 DSR Data Set Ready In normal operation (loopback mode disabled), this bit is the complement of the DSRx signal. 0 = DSRx input signal is High (deasserted). 1 = DSRx input signal is Low (asserted). If in loopback mode, this bit tracks bit DTR bit in the UARTxMCR register (see page 18-20). 4 CTS Clear To Send In normal operation (loopback mode disabled), this bit is the complement of the CTSx signal. 0 = CTSx input signal is High (deasserted). 1 = CTSx input signal is Low (asserted). If in loopback mode, this bit tracks bit RTS bit in the UARTxMCR register (see page 18-20). 3 DDCD Delta Data Carrier Detect 0 = Indicates that the DCDx signal has not changed since this register (UARTxMSR) was last read. 1 = Indicates that the DCDx signal changed since the UARTxMSR register was last read. Trailing Edge Ring Indicator 0 = Indicates that the RINx signal has not changed from an active to an inactive state since this register (UARTxMSR) was last read. 1 = Indicates that the RINx signal changed from an active to an inactive state since the UARTxMSR register was last read. 2 TERI ElanTMSC520 Microcontroller Register Set Manual 18-23 UART Serial Port Registers Bit 1 Name DDSR Function Delta Data Set Ready 0 = Indicates that the DSRx signal has not changed since this register (UARTxMSR) was last read. 1 = Indicates that the DSRx signal changed since the UARTxMSR register was last read. 0 DCTS Delta Clear To Send 0 = Indicates that the CTSx signal has not changed since this register (UARTxMSR) was last read. 1 = Indicates that the CTSx signal changed since the UARTxMSR register was last read. Programming Notes Bits DCD, RI, DSR, and CTS are real-time status indicators (inverted) for the corresponding UART input signals. DDCD, TERI, DDSR, and DCTS are latched status bits that generate an interrupt if modem status interrupts are unmasked in the UART x Interrupt Enable (UARTxINTENB) register. Reading this register (UARTxMSR) clears these bits and the associated interrupt. 18-24 ElanTMSC520 Microcontroller Register Set Manual UART Serial Port Registers Direct-Mapped UART 2 Scratch Pad (UART2SCRATCH) UART 1 Scratch Pad (UART1SCRATCH) I/O Address 02FFh I/O Address 03FFh 7 Bit Reset R/W 6 5 4 3 2 1 0 SCRATCH[7-0] 0 0 0 0 R/W 0 0 0 0 Register Description This location can be used to hold temporary data and is not required for serial data transfer. Bit Definitions Bit 7-0 Name SCRATCH [7-0] Function Scratch Bits General-purpose I/O location, not required for serial data transfer. Programming Notes ElanTMSC520 Microcontroller Register Set Manual 18-25 UART Serial Port Registers 18-26 ElanTMSC520 Microcontroller Register Set Manual CHAPTER 19 19.1 SYNCHRONOUS SERIAL INTERFACE REGISTERS OVERVIEW This chapter describes the synchronous serial interface (SSI) registers of the ELANSC520 microcontroller. The SSI provides efficient full-duplex or half-duplex bidirectional communication with peripheral devices that use a 4-pin or 3-pin serial interface. The SSI register set consists of five memory-mapped configuration region (MMCR) registers used for SSI control, transmit, command, status, and receive functions. See the ElanTMSC520 Microcontroller User's Manual, order #22004, for details about the SSI. Table 19-1 lists the SSI registers in offset order, with the corresponding description's page number. 19.2 Table 19-1 REGISTERS SSI MMCR Registers Register Name SSI Control SSI Transmit SSI Command SSI Status SSI Receive Mnemonic SSICTL SSIXMIT SSICMD SSISTA SSIRCV MMCR Offset CD0h CD1h CD2h CD3h CD4h Page Number page 19-2 page 19-4 page 19-5 page 19-6 page 19-7 ElanTMSC520 Microcontroller Register Set Manual 19-1 Synchronous Serial Interface Registers SSI Control (SSICTL) Memory-Mapped MMCR Offset CD0h 7 Bit Reset R/W 6 5 CLK_SEL[2-0] 4 3 TC_INT_ ENB 2 PHS_INV_ ENB 0 R/W 1 0 Reserved 0 RSV 0 CLK_INV_ MSBF_ENB ENB 0 R/W 0 R/W 0 R/W 0 0 R/W Register Description This register controls the bit order, clock idle state, clock phase (for data drive and latch), interrupt enable, and clock speed of the SSI. Bit Definitions Bit 7 6-4 Name Reserved CLK_SEL[2-0] Function Reserved This bit field should be written to 0 for normal system operation. SSI Clock Speed Select The SSI clock (SSI_CLK pin) frequency is derived from the system clock. The CLK_SEL bit field selects the frequency of the SSI clock as shown in Table 19-2. Table 19-2 CLK_SEL Bit Field 000b 001b 010b 011b 100b 101b 110b 111b SSI Clock Speed Selections Selected Divisor 4d 8d 16d 32d 64d 128d 256d 512d Nominal Bit Rate 8 MHz 4 MHz 2 MHz 1 MHz 512 kHz 256 kHz 128 kHz 64 kHz Actual Bit Rate with a 33.000-MHz System Clock 8.250 MHz 4.125 MHz 2.063 MHz 1.031 MHz 516.6 kHz 257.8 kHz 128.9 kHz 64.5 kHz Actual Bit Rate with a 33.333-MHz System CLock 8.333 MHz 4.167 MHz 2.083 MHz 1.042 MHz 520.8 kHz 260.4 kHz 130.2 kHz 65.1 kHz 3 TC_INT_ENB Transaction Complete Interrupt Enable This bit is used to enable the TC_INT bit of the SSISTA register (see page 19-6) to generate an interrupt request. 0 = No interrupt is generated when the transaction is complete. 1 = The SSI issues an interrupt request when the transaction is complete. If the interrupt is disabled, software should poll the BSY bit in the SSISTA register (see page 19-6). Before the SSI interrupt is enabled, the SSIMAP register (see page 12-21) must be configured to route the interrupt to the appropriate interrupt request level and priority. 19-2 ElanTMSC520 Microcontroller Register Set Manual Synchronous Serial Interface Registers Bit 2 Name PHS_INV_ENB Function SSI Inverted Phase Mode Enable This bit configures the SSI clock phase relationship with the incoming and outgoing data. 0 = Non-inverted phase mode: data is driven on odd edges of the SSI_CLK signal and latched on even edges. When writing data, the first bit of a transaction is shifted out on the SSI_DO pin on the first (odd) SSI clock edge, and the remaining bits are shifted out on odd clock edges. When reading data, the SSI_DI pin state is latched on the eight even edges (2,4,6,8,10,12,14,16) of the SSI clock. The transaction is complete one half of an SSI_CLK period after the last clock transition. 1 = Inverted-phase mode: data is driven on even edges of the SSI_CLK signal and latched on odd edges. When writing data, the first bit of a transaction is shifted out on the SSI_DO pin one half of an SSI_CLK period before the first (odd) SSI clock edge, and the remaining bits are shifted out on even clock edges. When reading data, the SSI_DI pin state is latched on the eight odd edges (1, 3, 5, 7, 9, 11, 13, 15) of the SSI clock. The transaction is complete on the last transition of the SSI clock. 1 CLK_INV_ENB SSI Inverted Clock Mode Enable This bit controls the idle state of the SSI clock. The clock idle state is independent of the phase of the SSI clock. 0 = The clock is not inverted, and the idle state is High. The SSI clock pulses Low eight times. 1 = The clock is inverted, and the idle state is Low. The SSI clock pulses High eight times. 0 MSBF_ENB SSI Most Significant Bit First Mode Enable This bit controls the bit order of data transfers. 0 = Bits are transmitted and received least significant bit (LSB) first. In this mode, the SSI shifts out the LSB of the transmit byte first. The first data bit received is stored in the LSB of the receive register and the last data bit received is stored in the most significant bit of the receive register. 1 = Bits are transmitted and received most significant bit (MSB) first. In this mode, the SSI shifts out the MSB of the transmit byte first. The first data bit received is stored in the MSB of the receive register and the last data bit received is stored in the LSB of the receive register. The configuration applies to both transmit and receive operations. Programming Notes This register should not be written while the BSY bit is set in the SSISTA register (see page 19-6). ElanTMSC520 Microcontroller Register Set Manual 19-3 Synchronous Serial Interface Registers SSI Transmit (SSIXMIT) Memory-Mapped MMCR Offset CD1h 7 Bit Reset R/W 6 5 4 3 2 1 0 DAT_OUT[7-0] 0 0 0 0 R/W 0 0 0 0 Register Description This register is used to write data to be transmitted. Bit Definitions Bit 7-0 Name DAT_OUT[7-0] Function SSI Data Out Software uses this bit field to write eight bits to be shifted out on the SSI_DO pin. After writing to this bit field, software must write a Transmit command or a Simultaneous Transmit/Receive command to the SSICMD register (see page 19-5) to send the data. The contents of this bit field (DAT_OUT) are not destroyed when transmitted, so the user can repeatedly transmit the same data by writing the appropriate transmit command to the SSICMD register. Programming Notes This register should not be written while the BSY bit is set in the SSISTA register (see page 19-6). 19-4 ElanTMSC520 Microcontroller Register Set Manual Synchronous Serial Interface Registers SSI Command (SSICMD) Memory-Mapped MMCR Offset CD2h 7 Bit Reset R/W 6 5 Reserved 4 3 2 1 0 CMD_SEL[1-0] 0 0 0 0 R/W 0 0 0 0 RSV Register Description This register is used to write the transfer command to be executed. Bit Definitions Bit 7-2 1-0 Name Reserved CMD_SEL[1-0] Function Reserved This bit field should be written to 0 for normal system operation. SSI Command Select Three commands are available to initiate an SSI transaction. 00 = Reserved 01 = Transmit command: initiate a transaction in which the contents of the SSIXMIT register are shifted out (see page 19-4). 10 = Receive command: initiate a transaction in which data is shifted in to the SSIRCV register (see page 19-7). 11 = Simultaneous Transmit/Receive command: initiate a transaction in which both transmit and receive happen simultaneously. When read, this bit field returns the last command written to it. Programming Notes This register should not be written while the BSY bit is set in the SSISTA register (see page 19-6). The CMD_SEL bit field is decoded and the command executed after the command is written. Software should load the SSIXMIT register (if necessary) before writing the command. The SSIRCV register can be read after the transaction is complete. There is at least one 33-MHz clock period idle time between transactions. A slave device should be enabled (if necessary) before a transmit or receive transaction is initiated, and the device should be disabled (if necessary) after the transaction is complete. Software can use programmable I/O (PIO) pins to implement device enable signals. See Chapter 20, "Programmable Input/Output Registers" for details about configuring PIO pins. ElanTMSC520 Microcontroller Register Set Manual 19-5 Synchronous Serial Interface Registers SSI Status (SSISTA) Memory-Mapped MMCR Offset CD3h 7 Bit Reset R/W 6 5 Reserved 4 3 2 1 BSY 0 TC_INT 0 R/W! 0 0 0 RSV 0 0 0 0 R Register Description This register reports SSI port busy status and a latched transaction complete status. Bit Definitions Bit 7-2 1 Name Reserved BSY Function Reserved This bit field should be written to 0 for normal system operation. SSI Busy This bit reports SSI activity status. 0 = The port is not busy. 1 = The port is busy. The port is busy (active) while a receive or transmit operation is in progress. This bit is set by the SSI hardware after a command is written, and cleared by hardware when the transaction is complete. Transaction complete status is also indicated by the TC_INT bit. Writes to the BSY bit have no effect. 0 TC_INT SSI Transaction Complete Interrupt This bit indicates transaction complete status. 0 = No transaction has completed since software cleared this bit. 1 = A transaction has completed since software cleared this bit. Software must clear this bit by writing a 1. The TC_INT bit remains set until software acknowledges this completion by writing a 1. When the TC_INT bit is set, an interrupt request is generated if enabled via the TC_INT_ENB bit in the SSICTL register (see page 19-2). SSI activity is also indicated by the BSY bit. Programming Notes This register (SSISTA) should not be written while the BSY bit is set. Also, unreliable operation occurs if the SSICTL, SSIXMIT, or SSICMD registers are written, or if the SSIRCV register is read, while the BSY bit is set. Hardware updates the BSY and TC_INT bits to indicate non-busy status (transaction complete) one half SSI_CLK period after the last edge of a receive transaction, or one full SSI_CLK period after the last edge of a transmit transaction. The TC_INT bit should be used for interrupt operation, i.e., if the TC_INT_ENB bit is enabled in the SSICTL register (see page 19-2). Software must acknowledge (clear) the TC_INT bit by writing a 1 to it after each SSI transaction. The BSY bit should be used for polled operation. Although the TC_INT bit can be used for polled operation, using the BSY bit is more efficient because it does not need to be cleared by software after each transaction. Note that if only the polled operation is used, the TC_INT_ENB bit should not be enabled in the SSICTL register (see page 19-2). 19-6 ElanTMSC520 Microcontroller Register Set Manual Synchronous Serial Interface Registers SSI Receive (SSIRCV) Memory-Mapped MMCR Offset CD4h 7 Bit Reset R/W 6 5 4 3 2 1 0 DAT_IN[7-0] 0 0 0 0 R 0 0 0 0 Register Description This register is used to read data received from a peripheral device. Bit Definitions Bit 7-0 Name DAT_IN[7-0] Function SSI Data IN Software uses this bit field to read the eight bits shifted in from the SSI_DI pin by the last Receive command or Simultaneous Transmit/Receive command that was issued via the SSICMD register (see page 19-5). After writing a receive command, software must wait until the receive transaction is complete before reading this bit field. Transaction complete status is indicated by the BSY and TC_INT bits in the SSISTA register (see page 19-6), or by an interrupt if enabled via the TC_INT_ENB bit in the SSICTL register (see page 19-2). Writes to this bit field (DAT_IN) have no effect. Programming Notes This register should not be read while the BSY bit is set in the SSISTA register (see page 19-6). ElanTMSC520 Microcontroller Register Set Manual 19-7 Synchronous Serial Interface Registers 19-8 ElanTMSC520 Microcontroller Register Set Manual CHAPTER 20 20.1 PROGRAMMABLE INPUT/OUTPUT REGISTERS OVERVIEW This chapter describes the programmable input/output (PIO) pins and other multiplexed or configurable pins of the ELANSC520 microcontroller. The PIO register set consists of 13 memory-mapped configuration region (MMCR) registers used to configure the programmable I/O pins (PIO31-PIO0), to enable interface functions for PIO pins and other multiplexed pins, and to adjust the drive strength of SDRAM interface pins. See the ElanTMSC520 Microcontroller User's Manual, order #22004, for details about PIO pins. Table 20-1 lists the PIO registers in offset order, with the corresponding description's page number. Table 20-2 on page 20-2 provides an overview of how bits in the PIO pin configuration registers are used to control individual PIO pins. 20.2 Table 20-1 REGISTERS Programmable I/O MMCR Registers Register Name PIO15-PIO0 Pin Function Select PIO31-PIO16 Pin Function Select Chip Select Pin Function Select Clock Select Drive Strength Control PIO15-PIO0 Direction PIO31-PIO16 Direction PIO15-PIO0 Data PIO31-PIO16 Data PIO15-PIO0 Set PIO31-PIO16 Set PIO15-PIO0 Clear PIO31-PIO16 Clear Mnemonic PIOPFS15_0 PIOPFS31_16 CSPFS CLKSEL DSCTL PIODIR15_0 PIODIR31_16 PIODATA15_0 PIODATA31_16 PIOSET15_0 PIOSET31_16 PIOCLR15_0 PIOCLR31_16 MMCR Offset Page Number C20h C22h C24h C26h C28h C2Ah C2Ch C30h C32h C34h C36h C38h C3Ah page 20-3 page 20-5 page 20-7 page 20-9 page 20-10 page 20-12 page 20-14 page 20-16 page 20-18 page 20-20 page 20-22 page 20-24 page 20-26 ElanTMSC520 Microcontroller Register Set Manual 20-1 Programmable Input/Output Registers Table 20-2 Function Select Register Bit PIO Register Programming Summary Data Register Bit (Writes) Set Register Bit Clear Register Bit Data Register Bit (Reads)1 Direction Register Bit Resulting Programmable I/O Pin Function The pin is not a PIO; it uses its interface function. The value of the pin can be read at the Data bit, but writes to the Direction, Data, Set, and Clear bits have no effect. The PIO is an input. The state of the pin can be read at the Data bit. Writes to the Data, Set and Clear bits have no effect. The PIO is an output. The 1 that is written to the Clear bit causes this PIO pin to be driven Low. The state of the pin can be read at the Data bit, (in this case the pin is Low). The PIO is an output. The 1 that is written to the Set bit causes this PIO pin to be driven High. The state of the pin can be read at the Data bit, (in this case the pin is High). The PIO is an output. The 0 that is written to the Data bit causes this PIO pin to be driven Low. The state of the pin can be read at the Data bit, (in this case the pin is Low). The PIO is an output. The 1 that is written to the Data bit causes this PIO pin to be driven High. The state of the pin can be read at the Data bit, (in this case the pin is High). 1 X2 X X X ?3 0 0 X X X 14 ? 0 1 X X 0 0 1 X 1 X 1 0 1 0 X X 0 0 1 1 X X 1 Notes: 1. The Data Register Bit (Reads) column shows the resulting state of the Data register bit and the corresponding PIO pin. 2. X = Not used in this operation. 3. ? = Input value. (The Data register bit state always reflects the corresponding pin state, whether input or output.) 4. For a particular PIO output operation, only one of the pin's Data, Set, or Clear bits can be used. The state of the unused bits is not important, but subsequent writes to these bits can change the PIO pin state. 20-2 ElanTMSC520 Microcontroller Register Set Manual Programmable Input/Output Registers PIO15-PIO0 Pin Function Select (PIOPFS15_0) Memory-Mapped MMCR Offset C20h 15 Bit Reset R/W 14 PIO14_ FNC 0 R/W 6 PIO6_ FNC 0 R/W 13 PIO13_ FNC 0 R/W 5 PIO5_ FNC 0 R/W 12 PIO12_ FNC 0 R/W 4 PIO4_ FNC 0 R/W 11 PIO11_ FNC 0 R/W 3 PIO3_ FNC 0 R/W 10 PIO10_ FNC 0 R/W 2 PIO2_ FNC 0 R/W 9 PIO9_ FNC 0 R/W 1 PIO1_ FNC 0 R/W 8 PIO8_ FNC 0 R/W 0 PIO0_ FNC 0 R/W PIO15_ FNC 0 R/W 7 Bit Reset R/W PIO7_ FNC 0 R/W Register Description This register allows the programmer to choose the functionality of programmable I/O pins PIO15-PIO0. Bit Definitions Bit 15 Name PIO15_FNC Function PIO15 or GPIRQ8 Function Select This bit is used to select the functionality of the PIO15 pin. 0 = The pin is PIO15. 1 = The pin is GPIRQ8. PIO14 or GPIRQ9 Function Select This bit is used to select the functionality of the PIO14 pin. 0 = The pin is PIO14. 1 = The pin is GPIRQ9. PIO13 or GPIRQ10 Function Select This bit is used to select the functionality of the PIO13 pin. 0 = The pin is PIO13. 1 = The pin is GPIRQ10. PIO12 or GPDACK0 Function Select This bit is used to select the functionality of the PIO12 pin. 0 = The pin is PIO12. 1 = The pin is GPDACK0. PIO11 or GPDACK1 Function Select This bit is used to select the functionality of the PIO11 pin. 0 = The pin is PIO11. 1 = The pin is GPDACK1. PIO10 or GPDACK2 Function Select This bit is used to select the functionality of the PIO10 pin. 0 = The pin is PIO10. 1 = The pin is GPDACK2. PIO9 or GPDACK3 Function Select This bit is used to select the functionality of the PIO9 pin. 0 = The pin is PIO9. 1 = The pin is GPDACK3. 14 PIO14_FNC 13 PIO13_FNC 12 PIO12_FNC 11 PIO11_FNC 10 PIO10_FNC 9 PIO9_FNC ElanTMSC520 Microcontroller Register Set Manual 20-3 Programmable Input/Output Registers Bit 8 Name PIO8_FNC Function PIO8 or GPDRQ0 Function Select This bit is used to select the functionality of the PIO8 pin. 0 = The pin is PIO8. 1 = The pin is GPDRQ0. PIO7 or GPDRQ1 Function Select This bit is used to select the functionality of the PIO7 pin. 0 = The pin is PIO7. 1 = The pin is GPDRQ1. PIO6 or GPDRQ2 Function Select This bit is used to select the functionality of the PIO6 pin. 0 = The pin is PIO6. 1 = The pin is GPDRQ2. PIO5 or GPDRQ3 Function Select This bit is used to select the functionality of the PIO5 pin. 0 = The pin is PIO5. 1 = The pin is GPDRQ3. PIO4 or GPTC Function Select This bit is used to select the functionality of the PIO4 pin. 0 = The pin is PIO4. 1 = The pin is GPTC. PIO3 or GPAEN Function Select This bit is used to select the functionality of the PIO3 pin. 0 = The pin is PIO3. 1 = The pin is GPAEN. PIO2 or GPRDY Function Select This bit is used to select the functionality of the PIO2 pin. 0 = The pin is PIO2. 1 = The pin is GPRDY. PIO1 or GPBHE Function Select This bit is used to select the functionality of the PIO1 pin. 0 = The pin is PIO1. 1 = The pin is GPBHE. PIO0 or GPALE Function Select This bit is used to select the functionality of the PIO0 pin. 0 = The pin is PIO0. 1 = The pin is GPALE. 7 PIO7_FNC 6 PIO6_FNC 5 PIO5_FNC 4 PIO4_FNC 3 PIO3_FNC 2 PIO2_FNC 1 PIO1_FNC 0 PIO0_FNC Programming Notes This register (PIOPFS15_0) should be written early in the microcontroller's initialization routine. The bit values to write depend on which pins are to be used for PIO functions, as opposed to interface functions. This depends on how the microcontroller is used in each particular system design. On reset, each PIO pin is an input with a pullup or pulldown resistance for termination. See the pin list summary table in the ElanTMSC520 Microcontroller Data Sheet, order #22003. Software writes a 1 to the corresponding bit in this register to change a pin to its interface function. For example, PIO2 shares a pin with the GP bus GPRDY signal, so before GPRDY can be used, a 1 must be written to the PIO2_FNC bit. To summarize: s A bit must be cleared to use the corresponding pin as a programmable I/O pin. s A bit must be set to 1 to use the corresponding pin for its interface function. Although software can perform a 32-bit access of MMCR offset C20h to select all 32 PIO pin functions with a single instruction, the 32-bit access is split into two separate 16-bit accesses, with the PIOPFS15_0 register being accessed prior to the PIOPFS31_16 register. The two accesses are not simultaneous. 20-4 ElanTMSC520 Microcontroller Register Set Manual Programmable Input/Output Registers PIO31-PIO16 Pin Function Select (PIOPFS31_16) Memory-Mapped MMCR Offset C22h 15 Bit Reset R/W 14 PIO30_ FNC 0 R/W 6 PIO22_ FNC 0 R/W 13 PIO29_ FNC 0 R/W 5 PIO21_ FNC 0 R/W 12 PIO28_ FNC 0 R/W 4 PIO20_ FNC 0 R/W 11 PIO27_ FNC 0 R/W 3 PIO19_ FNC 0 R/W 10 PIO26_ FNC 0 R/W 2 PIO18_ FNC 0 R/W 9 PIO25_ FNC 0 R/W 1 PIO17_ FNC 0 R/W 8 PIO24_ FNC 0 R/W 0 PIO16_ FNC 0 R/W PIO31_ FNC 0 R/W 7 Bit Reset R/W PIO23_ FNC 0 R/W Register Description This register allows the programmer to choose the functionality of programmable I/O pins PIO31-PIO16. Bit Definitions Bit 15 Name PIO31_FNC Function PIO31 or RIN2 Function Select This bit is used to select the functionality of the PIO31 pin. 0 = The pin is PIO31. 1 = The pin is RIN2. PIO30 or DCD2 Function Select This bit is used to select the functionality of the PIO30 pin. 0 = The pin is PIO30. 1 = The pin is DCD2. PIO29 or DSR2 Function Select This bit is used to select the functionality of the PIO29 pin. 0 = The pin is PIO29. 1 = The pin is DSR2. PIO28 or CTS2 Function Select This bit is used to select the functionality of the PIO28 pin. 0 = The pin is PIO28. 1 = The pin is CTS2. PIO27 or GPCS0 Function Select This bit is used to select the functionality of the PIO27 pin. 0 = The pin is PIO27. 1 = The pin is GPCS0. PIO26 or GPMEMCS16 Function Select This bit is used to select the functionality of the PIO26 pin. 0 = The pin is PIO26. 1 = The pin is GPMEMCS16. PIO25 or GPIOCS16 Function Select This bit is used to select the functionality of the PIO25 pin. 0 = The pin is PIO25. 1 = The pin is GPIOCS16. 14 PIO30_FNC 13 PIO29_FNC 12 PIO28_FNC 11 PIO27_FNC 10 PIO26_FNC 9 PIO25_FNC ElanTMSC520 Microcontroller Register Set Manual 20-5 Programmable Input/Output Registers Bit 8 Name PIO24_FNC Function PIO24 or GPDBUFOE Function Select This bit is used to select the functionality of the PIO24 pin. 0 = The pin is PIO24. 1 = The pin is GPDBUFOE. PIO23 or GPIRQ0 Function Select This bit is used to select the functionality of the PIO23 pin. 0 = The pin is PIO23. 1 = The pin is GPIRQ0. PIO22 or GPIRQ1 Function Select This bit is used to select the functionality of the PIO22 pin. 0 = The pin is PIO22. 1 = The pin is GPIRQ1. PIO21 or GPIRQ2 Function Select This bit is used to select the functionality of the PIO21 pin. 0 = The pin is PIO21. 1 = The pin is GPIRQ2. PIO20 or GPIRQ3 Function Select This bit is used to select the functionality of the PIO20 pin. 0 = The pin is PIO20. 1 = The pin is GPIRQ3. PIO19 or GPIRQ4 Function Select This bit is used to select the functionality of the PIO19 pin. 0 = The pin is PIO19. 1 = The pin is GPIRQ4. PIO18 or GPIRQ5 Function Select This bit is used to select the functionality of the PIO18 pin. 0 = The pin is PIO18. 1 = The pin is GPIRQ5. PIO17 or GPIRQ6 Function Select This bit is used to select the functionality of the PIO17 pin. 0 = The pin is PIO17. 1 = The pin is GPIRQ6. PIO16 or GPIRQ7 Function Select This bit is used to select the functionality of the PIO16 pin. 0 = The pin is PIO16. 1 = The pin is GPIRQ7. 7 PIO23_FNC 6 PIO22_FNC 5 PIO21_FNC 4 PIO20_FNC 3 PIO19_FNC 2 PIO18_FNC 1 PIO17_FNC 0 PIO16_FNC Programming Notes This register (PIOPFS31_16) should be written early in the microcontroller's initialization routine. The bit values to write depend on which pins are to be used for PIO functions, as opposed to interface functions. This depends on how the microcontroller is used in each particular system design. On reset, each PIO pin is an input with a pullup or pulldown resistance for termination. See the pin list summary table in the ElanTMSC520 Microcontroller Data Sheet, order #22003. Software writes a 1 to the corresponding bit in this register to change a pin to its interface function. For example, PIO18 shares a pin with the GP bus GPIRQ5 signal, so before GPIRQ5 can be used, a 1 must be written to the PIO18_FNC bit. To summarize: s A bit must be cleared to use the corresponding pin as a programmable I/O pin. s A bit must be set to 1 to use the corresponding pin for its interface function. Although software can perform a 32-bit access of MMCR offset C20h to select all 32 PIO pin functions with a single instruction, the 32-bit access is split into two separate 16-bit accesses, with the PIOPFS15_0 register being accessed prior to the PIOPFS31_16 register. The two accesses are not simultaneous. 20-6 ElanTMSC520 Microcontroller Register Set Manual Programmable Input/Output Registers Chip Select Pin Function Select (CSPFS) Memory-Mapped MMCR Offset C24h 7 Bit Reset R/W 6 GPCS6_ SEL 0 R/W 5 GPCS5_ SEL 0 R/W 4 GPCS4_ SEL 0 R/W 3 GPCS3_ SEL 0 R/W 2 GPCS2_ SEL 0 R/W 1 GPCS1_ SEL 0 R/W 0 Reserved 0 RSV GPCS7_ SEL 0 R/W Register Description This register selects the pin functionality for pins that have general-purpose chip selects (GPCSx) as their alternate function. Bit Definitions Bit 7 Name GPCS7_SEL Function TMROUT0 or GPCS7 Function Select This bit is used to make either the TMROUT0 signal or the GPCS7 signal available on the pin. The default on reset is TMROUT0. 0 = The pin is TMROUT0. 1 = The pin is GPCS7. TMROUT1 or GPCS6 Function Select This bit is used to make either the TMROUT1 signal or the GPCS6 signal available on the pin. The default on reset is TMROUT1. 0 = The pin is TMROUT1. 1 = The pin is GPCS6. TMRIN0 or GPCS5 Function Select This bit is used to make either the TMRIN0 signal or the GPCS5 signal available on the pin. The default on reset is TMRIN0. 0 = The pin is TMRIN0. 1 = The pin is GPCS5. TMRIN1 or GPCS4 Function Select This bit is used to make either the TMRIN1 signal or the GPCS4 signal available on the pin. The default on reset is TMRIN1. 0 = The pin is TMRIN1. 1 = The pin is GPCS4. PITGATE2 or GPCS3 Function Select This bit is used to make either the PITGATE2 signal or the GPCS3 signal available on the pin. The default on reset is PITGATE2. 0 = The pin is PITGATE2. 1 = The pin is GPCS3. ROMCS2 or GPCS2 Function Select This bit is used to make either the ROMCS2 signal or the GPCS2 signal available on the pin. The default on reset is ROMCS2. 0 = The pin is ROMCS2. 1 = The pin is GPCS2. 6 GPCS6_SEL 5 GPCS5_SEL 4 GPCS4_SEL 3 GPCS3_SEL 2 GPCS2_SEL ElanTMSC520 Microcontroller Register Set Manual 20-7 Programmable Input/Output Registers Bit 1 Name GPCS1_SEL Function ROMCS1 or GPCS1 Function Select This bit is used to make either the ROMCS1 signal or the GPCS1 signal available on the pin. The default on reset is ROMCS1. 0 = The pin is ROMCS1. 1 = The pin is GPCS1. 0 Reserved Reserved This bit field should be written to 0 for normal system operation. Programming Notes The GPCS0 signal is shared with the PIO27 signal on one pin, so it is selected through the PIOPFS31_16 register (see page 20-5). This register (CSPFS) should be written early in the microcontroller's initialization routine. The bit values to write depend on which function is to be used for each pin. This depends on how the microcontroller is used in each particular system design. On reset, each pin's primary function is selected. See the pin list summary table in the ElanTMSC520 Microcontroller Data Sheet, order #22003. Software writes a 1 to the corresponding bit in this register to change a pin to its alternate function. For example, TMROUT0 shares a pin with the GP bus GPCS7 signal, so before GPCS7 can be used, a 1 must be written to the GPCS7_SEL bit. To summarize: s A bit must be cleared to use the corresponding pin for its primary function. s A bit must be set to 1 to use the corresponding pin for its alternate function. 20-8 ElanTMSC520 Microcontroller Register Set Manual Programmable Input/Output Registers Clock Select (CLKSEL) Memory-Mapped MMCR Offset C26h 7 Bit Reset R/W 6 5 CLK_TST_SEL[2-0] 4 3 Reserved 2 1 CLK_PIN_ DIR 0 CLK_PIN_ ENB 0 R/W Reserved 0 RSV 1 1 R/W 1 0 RSV 0 0 R/W Register Description This register is used to set up the CLKTIMER[CLKTEST] pin. Bit Definitions Bit 7 6-4 Name Reserved CLK_TST_ SEL[2-0] Function Reserved This bit field should be written to 0 for normal system operation. CLKTEST Pin Output Clock Select 000 = 32.768 kHz (RTC clock) 001 = 1.8432 MHz (UART clock) 010 = 18.432 MHz (UART clock) 011 = 1.1892 MHz (PIT clock) 100 = 1.47456 MHz (PLL1 output) 101 = 36.864 MHz (PLL2 output) 110-111 = Disabled (pin stays Low) 3-2 1 Reserved CLK_PIN_DIR Reserved This bit field should be written to 0 for normal system operation. CLKTIMER[CLKTEST] Pin Direction This bit determines whether the CLKTIMER[CLKTEST] pin is an input (CLKTIMER) or output (CLKTEST). As an input this pin provides the clock for the programmable interval timer (PIT). As an output, this pin drives the clock selected by the CLK_TST_SEL bit field externally. 0 = Input (CLKTIMER) 1 = Output (CLKTEST) CLKTIMER[CLKTEST] Pin Enable The CLKTIMER[CLKTEST] pin is disabled on reset and must be enabled to function. 0 = Disabled 1 = Enabled 0 CLK_PIN_ ENB Programming Notes The CLKTIMER[CLKTEST] pin can be configured as an output (CLKTEST) to drive any of the several internal clocks externally for testing, or to drive an external device. Caution should be exercised because there is no logic to avoid spurious pulses while enabling this pin as an output or changing clock frequencies. The target device should be held in reset while the CLK_TST_SEL, CLK_PIN_DIR, and CLK_PIN_ENB bit fields are configured to enable the pin as an output with the desired frequency, then the target device can be released from reset. The CLKTIMER[CLKTEST] pin can be enabled as an input (CLKTIMER) if an external oscillator is to be used for the programmable interval timer (PIT). For example, a 1.19318-MHz CLKTIMER input can be used to provide PC/ AT-compatible time-of-day operation without changing PIT counter values. (See the PIT chapter of the ElanTMSC520 Microcontroller User's Manual, order #22004, for details.) While the pin is being enabled as an input, it is synchronized to the CPU clock to prevent spurious pulses from occurring in the PIT. ElanTMSC520 Microcontroller Register Set Manual 20-9 Programmable Input/Output Registers Drive Strength Control (DSCTL) Memory-Mapped MMCR Offset C28h 15 Bit Reset R/W 14 13 Reserved 12 11 10 9 8 SCS_DRIVE[1-0] 0 0 0 1 R/W 4 3 2 1 0 0 0 0 0 RSV 7 Bit Reset R/W 6 5 SRCW_DRIVE[1-0] 0 R/W 0 SDQM_DRIVE[1-0] 0 R/W 0 MA_DRIVE[1-0] 0 R/W 0 DATA_DRIVE[1-0] 0 R/W 0 Register Description This register controls the drive strengths for the SDRAM interface signals. Independent drive strength control is provided for the address bus (MA12-MA0), bank select bus (BA1-BA0), SDQM3-SDQM0 bus, and SCS3-SCS0. The SRASA-SRASB, SCASA-SCASB and SWEA-SWEB control signals are grouped into a single drive strength control. The data bus (MD31-MD0) and ECC bus (MECC6-MECC0) are also grouped into a single drive strength control. Note: A programmable reset preserves this register's state. See the PRG_RST_ENB bit description on page 3-3. Bit Definitions Bit 15-10 9-8 Name Reserved SCS_DRIVE [1-0] Function Reserved This bit field should be written to 0 for normal system operation. I/O Pad Drive Strength for SCS3-SCS0 These bits select the drive strength of I/O pads for the SCS3-SCS0 signals. 00 = Reserved 01 = 18-mA pads 10 = 12-mA pads (default) 11 = Reserved Note: Default state of SCS3-SCS0 drive strength is 12 mA. 7-6 SRCW_DRIVE [1-0] I/O Pad Drive Strength for SRASA-SRASB, SCASA-SCASB and SWEA-SWEB These bits select the drive strength of I/O pads for the SRASA-SRASB, SCASA-SCASB, and SWEA-SWEB signals. 00 = 24-mA pads (default) 01 = 18-mA pads 10 = 12-mA pads 11 = Reserved 5-4 SDQM_DRIVE [1-0] I/O Pad Drive Strength for SDQM3-SDQM0 These bits select the drive strength of I/O pads for the SDQM3-SDQM0 signals. 00 = 24-mA pads (default) 01 = 18-mA pads 10 = 12-mA pads 11 = Reserved 20-10 ElanTMSC520 Microcontroller Register Set Manual Programmable Input/Output Registers 3-2 MA_DRIVE [1-0] I/O Pad Drive Strength for MA12-MA0 and BA1-BA0 These bits select the drive strength of I/O pads for the MA12-MA0 and BA1-BA0 signals. 00 = 24-mA pads (default) 01 = 18-mA pads 10 = 12-mA pads 11 = Reserved 1-0 DATA_DRIVE [1-0] I/O Pad Drive Strength for MD31-MD0 and MECC6-MECC0 These bits select the drive strength of I/O pads for the MD31-MD0 and MECC6-MECC0 signals. 00 = 24-mA pads (default) 01 = 18-mA pads 10 = 12-mA pads 11 = Reserved Programming Notes ElanTMSC520 Microcontroller Register Set Manual 20-11 Programmable Input/Output Registers PIO15-PIO0 Direction (PIODIR15_0) Memory-Mapped MMCR Offset C2Ah 15 Bit Reset R/W 14 PIO14_ DIR 0 R/W 6 PIO6_ DIR 0 R/W 13 PIO13_ DIR 0 R/W 5 PIO5_ DIR 0 R/W 12 PIO12_ DIR 0 R/W 4 PIO4_ DIR 0 R/W 11 PIO11_ DIR 0 R/W 3 PIO3_ DIR 0 R/W 10 PIO10_ DIR 0 R/W 2 PIO2_ DIR 0 R/W 9 PIO9_ DIR 0 R/W 1 PIO1_ DIR 0 R/W 8 PIO8_ DIR 0 R/W 0 PIO0_ DIR 0 R/W PIO15_ DIR 0 R/W 7 Bit Reset R/W PIO7_ DIR 0 R/W Register Description This register contains the direction bits for pins PIO15-PIO0. Bit Definitions Bit 15 Name PIO15_DIR Function PIO15 Input or Output Select This bit programs PIO15 as an input or output. 0 = Input 1 = Output PIO14 Input or Output Select This bit programs PIO14 as an input or output. 0 = Input 1 = Output PIO13 Input or Output Select This bit programs PIO13 as an input or output. 0 = Input 1 = Output PIO12 Input or Output Select This bit programs PIO12 as an input or output. 0 = Input 1 = Output PIO11 Input or Output Select This bit programs PIO11 as an input or output. 0 = Input 1 = Output PIO10 Input or Output Select This bit programs PIO10 as an input or output. 0 = Input 1 = Output 14 PIO14_DIR 13 PIO13_DIR 12 PIO12_DIR 11 PIO11_DIR 10 PIO10_DIR 20-12 ElanTMSC520 Microcontroller Register Set Manual Programmable Input/Output Registers Bit 9 Name PIO9_DIR Function PIO9 Input or Output Select This bit programs PIO9 as an input or output. 0 = Input 1 = Output 8 PIO8_DIR PIO8 Input or Output Select This bit programs PIO8 as an input or output. 0 = Input 1 = Output 7 PIO7_DIR PIO7 Input or Output Select This bit programs PIO7 as an input or output. 0 = Input 1 = Output 6 PIO6_DIR PIO6 Input or Output Select This bit programs PIO6 as an input or output. 0 = Input 1 = Output 5 PIO5_DIR PIO5 Input or Output Select This bit programs PIO5 as an input or output. 0 = Input 1 = Output 4 PIO4_DIR PIO4 Input or Output Select This bit programs PIO4 as an input or output. 0 = Input 1 = Output 3 PIO3_DIR PIO3 Input or Output Select This bit programs PIO3 as an input or output. 0 = Input 1 = Output 2 PIO2_DIR PIO2 Input or Output Select This bit programs PIO2 as an input or output. 0 = Input 1 = Output 1 PIO1_DIR PIO1 Input or Output Select This bit programs PIO1 as an input or output. 0 = Input 1 = Output 0 PIO0_DIR PIO0 Input or Output Select This bit programs PIO0 as an input or output. 0 = Input 1 = Output Programming Notes The PIOx_DIR bit for each PIO pin chooses if the pin is an input or output. After reset, all of the PIO signals are inputs with pullup or pulldown termination. Before any PIO can be used as an output, this register (PIODIR15_0) must be programmed to change the PIO from an input to an output. The PIOx_DIR bit for a pin has no effect if the corresponding PIOx_FNC bit is set in the PIOPFS15_0 register (see page 20-3). If the PIOx_FNC bit is set, the corresponding pin is assigned its interface function, not its PIO function. Although software can perform a 32-bit access of MMCR offset C2Ah to set the direction for all 32 PIO pins with a single instruction, the 32-bit access is split into two separate 16-bit accesses, with the PIODIR15_0 register being accessed prior to the PIODIR31_16 register. The two accesses are not simultaneous. ElanTMSC520 Microcontroller Register Set Manual 20-13 Programmable Input/Output Registers PIO31-PIO16 Direction (PIODIR31_16) Memory-Mapped MMCR Offset C2Ch 15 Bit Reset R/W 14 PIO30_ DIR 0 R/W 6 PIO22_ DIR 0 R/W 13 PIO29_ DIR 0 R/W 5 PIO21_ DIR 0 R/W 12 PIO28_ DIR 0 R/W 4 PIO20_ DIR 0 R/W 11 PIO27_ DIR 0 R/W 3 PIO19_ DIR 0 R/W 10 PIO26_ DIR 0 R/W 2 PIO18_ DIR 0 R/W 9 PIO25_ DIR 0 R/W 1 PIO17_ DIR 0 R/W 8 PIO24_ DIR 0 R/W 0 PIO16_ DIR 0 R/W PIO31_ DIR 0 R/W 7 Bit Reset R/W PIO23_ DIR 0 R/W Register Description This register contains the direction bits for pins PIO31-PIO16. Bit Definitions Bit 15 Name PIO31_DIR Function PIO31 Input or Output Select This bit programs PIO31 as an input or output. 0 = Input 1 = Output PIO30 Input or Output Select This bit programs PIO30 as an input or output. 0 = Input 1 = Output PIO29 Input or Output Select This bit programs PIO29 as an input or output. 0 = Input 1 = Output PIO28 Input or Output Select This bit programs PIO28 as an input or output. 0 = Input 1 = Output PIO27 Input or Output Select This bit programs PIO27 as an input or output. 0 = Input 1 = Output PIO26 Input or Output Select This bit programs PIO26 as an input or output. 0 = Input 1 = Output 14 PIO30_DIR 13 PIO29_DIR 12 PIO28_DIR 11 PIO27_DIR 10 PIO26_DIR 20-14 ElanTMSC520 Microcontroller Register Set Manual Programmable Input/Output Registers Bit 9 Name PIO25_DIR Function PIO25 Input or Output Select This bit programs PIO25 as an input or output. 0 = Input 1 = Output 8 PIO24_DIR PIO24 Input or Output Select This bit programs PIO24 as an input or output. 0 = Input 1 = Output 7 PIO23_DIR PIO23 Input or Output Select This bit programs PIO23 as an input or output. 0 = Input 1 = Output 6 PIO22_DIR PIO22 Input or Output Select This bit programs PIO22 as an input or output. 0 = Input 1 = Output 5 PIO21_DIR PIO21 Input or Output Select This bit programs PIO21 as an input or output. 0 = Input 1 = Output 4 PIO20_DIR PIO20 Input or Output Select This bit programs PIO20 as an input or output. 0 = Input 1 = Output 3 PIO19_DIR PIO19 Input or Output Select This bit programs PIO19 as an input or output. 0 = Input 1 = Output 2 PIO18_DIR PIO18 Input or Output Select This bit programs PIO18 as an input or output. 0 = Input 1 = Output 1 PIO17_DIR PIO17 Input or Output Select This bit programs PIO17 as an input or output. 0 = Input 1 = Output 0 PIO16_DIR PIO16 Input or Output Select This bit programs PIO16 as an input or output. 0 = Input 1 = Output Programming Notes The PIOx_DIR bit for each PIO pin chooses if the pin is an input or output. After reset, all of the PIO signals are inputs with pullup or pulldown termination. Before any PIO can be used as an output, this register (PIODIR31_16) must be programmed to change the PIO from an input to an output. The PIOx_DIR bit for a pin has no effect if the corresponding PIOx_FNC bit is set in the PIOPFS31_16 register (see page 20-5). If the PIOx_FNC bit is set, the corresponding pin is assigned its interface function, not its PIO function. Although software can perform a 32-bit access of MMCR offset C2Ah to set the direction for all 32 PIO pins with a single instruction, the 32-bit access is split into two separate 16-bit accesses, with the PIODIR15_0 register being accessed prior to the PIODIR31_16 register. The two accesses are not simultaneous. ElanTMSC520 Microcontroller Register Set Manual 20-15 Programmable Input/Output Registers PIO15-PIO0 Data (PIODATA15_0) Memory-Mapped MMCR Offset C30h 15 Bit Reset R/W 14 PIO14_ DATA ? R/W! 6 PIO6_ DATA ? R/W! 13 PIO13_ DATA ? R/W! 5 PIO5_ DATA ? R/W! 12 PIO12_ DATA ? R/W! 4 PIO4_ DATA ? R/W! 11 PIO11_ DATA ? R/W! 3 PIO3_ DATA ? R/W! 10 PIO10_ DATA ? R/W! 2 PIO2_ DATA ? R/W! 9 PIO9_ DATA ? R/W! 1 PIO1_ DATA ? R/W! 8 PIO8_ DATA ? R/W! 0 PIO0_ DATA ? R/W! PIO15_ DATA ? R/W! 7 Bit Reset R/W PIO7_ DATA ? R/W! Register Description This register is used to read or write the value for pins PIO15-PIO0. Bit Definitions Bit 15 Name PIO15_DATA Function Read or Write the PIO15 Pin 0 = PIO15 is Low 1 = PIO15 is High Read or Write the PIO14 Pin 0 = PIO14 is Low 1 = PIO14 is High Read or Write the PIO13 Pin 0 = PIO13 is Low 1 = PIO13 is High Read or Write the PIO12 Pin 0 = PIO12 is Low 1 = PIO12 is High Read or Write the PIO11 Pin 0 = PIO11 is Low 1 = PIO11 is High Read or Write the PIO10 Pin 0 = PIO10 is Low 1 = PIO10 is High Read or Write the PIO9 Pin 0 = PIO9 is Low 1 = PIO9 is High Read or Write the PIO8 Pin 0 = PIO8 is Low 1 = PIO8 is High 14 PIO14_DATA 13 PIO13_DATA 12 PIO12_DATA 11 PIO11_DATA 10 PIO10_DATA 9 PIO9_DATA 8 PIO8_DATA 20-16 ElanTMSC520 Microcontroller Register Set Manual Programmable Input/Output Registers Bit 7 Name PIO7_DATA Function Read or Write the PIO7 Pin 0 = PIO7 is Low 1 = PIO7 is High 6 PIO6_DATA Read or Write the PIO6 Pin 0 = PIO6 is Low 1 = PIO6 is High 5 PIO5_DATA Read or Write the PIO5 Pin 0 = PIO5 is Low 1 = PIO5 is High 4 PIO4_DATA Read or Write the PIO4 Pin 0 = PIO4 is Low 1 = PIO4 is High 3 PIO3_DATA Read or Write the PIO3 Pin 0 = PIO3 is Low 1 = PIO3 is High 2 PIO2_DATA Read or Write the PIO2 Pin 0 = PIO2 is Low 1 = PIO2 is High 1 PIO1_DATA Read or Write the PIO1 Pin 0 = PIO1 is Low 1 = PIO1 is High 0 PIO0_DATA Read or Write the PIO0 Pin 0 = PIO0 is Low 1 = PIO0 is High Programming Notes Each PIOx_DATA bit is used to read or write the value of the corresponding pin. If the pin is configured as a PIO output, then writing to this register selects the output level of the pin. Note that the output state of a pin programmed to be a PIO can also be controlled via the PIOSET15_0 and PIOCLR15_0 registers (see page 20-20 and page 20-24). Reading a pin's PIOx_DATA bit when the PIO is an output returns the state the pin was programmed for (High or Low). Reading a pin's PIOx_DATA bit when the pin's interface function is selected (via the corresponding PIOx_FCN bit in the PIOPFS15_0 register, see page 20-3) returns the state of the pin. In other words, reading a PIOx_DATA bit returns the state of the corresponding PIO pin regardless of how the other PIO registers are programmed. Although software can perform a 32-bit access of MMCR offset C30h to read or write all 32 PIO pins with a single instruction, the 32-bit access is split into two separate 16-bit accesses, with the PIODATA15_0 register being accessed prior to the PIODATA31_16 register. The two accesses are not simultaneous. ElanTMSC520 Microcontroller Register Set Manual 20-17 Programmable Input/Output Registers PIO31-PIO16 Data (PIODATA31_16) Memory-Mapped MMCR Offset C32h 15 Bit Reset R/W 14 PIO30_ DATA ? R/W! 6 PIO22_ DATA ? R/W! 13 PIO29_ DATA ? R/W! 5 PIO21_ DATA ? R/W! 12 PIO28_ DATA ? R/W! 4 PIO20_ DATA ? R/W! 11 PIO27_ DATA ? R/W! 3 PIO19_ DATA ? R/W! 10 PIO26_ DATA ? R/W! 2 PIO18_ DATA ? R/W! 9 PIO25_ DATA ? R/W! 1 PIO17_ DATA ? R/W! 8 PIO24_ DATA ? R/W! 0 PIO16_ DATA ? R/W! PIO31_ DATA ? R/W! 7 Bit Reset R/W PIO23_ DATA ? R/W! Register Description This register is used to read or write the value for pins PIO31-PIO16. Bit Definitions Bit 15 Name PIO31_DATA Function Read or Write the PIO31 Pin 0 = PIO31 is Low 1 = PIO31 is High Read or Write the PIO30 Pin 0 = PIO30 is Low 1 = PIO30 is High Read or Write the PIO29 Pin 0 = PIO29 is Low 1 = PIO29 is High Read or Write the PIO28 Pin 0 = PIO28 is Low 1 = PIO28 is High Read or Write the PIO27 Pin 0 = PIO27 is Low 1 = PIO27 is High Read or Write the PIO26 Pin 0 = PIO26 is Low 1 = PIO26 is High Read or Write the PIO25 Pin 0 = PIO25 is Low 1 = PIO25 is High Read or Write the PIO24 Pin 0 = PIO24 is Low 1 = PIO24 is High 14 PIO30_DATA 13 PIO29_DATA 12 PIO28_DATA 11 PIO27_DATA 10 PIO26_DATA 9 PIO25_DATA 8 PIO24_DATA 20-18 ElanTMSC520 Microcontroller Register Set Manual Programmable Input/Output Registers Bit 7 Name PIO23_DATA Function Read or Write the PIO23 Pin 0 = PIO23 is Low 1 = PIO23 is High 6 PIO22_DATA Read or Write the PIO22 Pin 0 = PIO22 is Low 1 = PIO22 is High 5 PIO21_DATA Read or Write the PIO21 Pin 0 = PIO21 is Low 1 = PIO21 is High 4 PIO20_DATA Read or Write the PIO20 Pin 0 = PIO20 is Low 1 = PIO20 is High 3 PIO19_DATA Read or Write the PIO19 Pin 0 = PIO19 is Low 1 = PIO19 is High 2 PIO18_DATA Read or Write the PIO18 Pin 0 = PIO18 is Low 1 = PIO18 is High 1 PIO17_DATA Read or Write the PIO17 Pin 0 = PIO17 is Low 1 = PIO17 is High 0 PIO16_DATA Read or Write the PIO16 Pin 0 = PIO16 is Low 1 = PIO16 is High Programming Notes Each PIOx_DATA bit is used to read or write the value of the corresponding pin. If the pin is configured as a PIO output, then writing to this register selects the output level of the pin. Note that the output state of a pin programmed to be a PIO can also be controlled via the PIOSET31_16 and PIOCLR31_16 registers (see page 20-22 and page 20-26). Reading a pin's PIOx_DATA bit when the PIO is an output returns the state the pin was programmed for (High or Low). Reading a pin's PIOx_DATA bit when the pin's interface function is selected (via the corresponding PIOx_FCN bit in the PIOPFS31_16 register, see page 20-5) returns the state of the pin. In other words, reading a PIOx_DATA bit returns the state of the corresponding PIO pin regardless of how the other PIO registers are programmed. Although software can perform a 32-bit access of MMCR offset C30h to read or write all 32 PIO pins with a single instruction, the 32-bit access is split into two separate 16-bit accesses, with the PIODATA15_0 register being accessed prior to the PIODATA31_16 register. The two accesses are not simultaneous. ElanTMSC520 Microcontroller Register Set Manual 20-19 Programmable Input/Output Registers PIO15-PIO0 Set (PIOSET15_0) Memory-Mapped MMCR Offset C34h 15 Bit Reset R/W 14 PIO14_ SET x W! 6 PIO6_ SET x W! 13 PIO13_ SET x W! 5 PIO5_ SET x W! 12 PIO12_ SET x W! 4 PIO4_ SET x W! 11 PIO11_ SET x W! 3 PIO3_ SET x W! 10 PIO10_ SET x W! 2 PIO2_ SET x W! 9 PIO9_ SET x W! 1 PIO1_ SET x W! 8 PIO8_ SET x W! 0 PIO0_ SET x W! PIO15_ SET x W! 7 Bit Reset R/W PIO7_ SET x W! Register Description This register is used to make the output level High selectively for pins PIO15-PIO0. Bit Definitions Bit 15 Name PIO15_SET Function PIO15 Set 0 = No effect. 1 = Set thePIO15 signal High. PIO14 Set 0 = No effect. 1 = Set the PIO14 signal High. PIO13 Set 0 = No effect. 1 = Set the PIO13 signal High. PIO12 Set 0 = No effect. 1 = Set the PIO12 signal High. PIO11 Set 0 = No effect. 1 = Set the PIO11 signal High. PIO10 Set 0 = No effect. 1 = Set the PIO10 signal High. PIO9 Set 0 = No effect. 1 = Set the PIO9 signal High. PIO8 Set 0 = No effect. 1 = Set the PIO8 signal High. 14 PIO14_SET 13 PIO13_SET 12 PIO12_SET 11 PIO11_SET 10 PIO10_SET 9 PIO9_SET 8 PIO8_SET 20-20 ElanTMSC520 Microcontroller Register Set Manual Programmable Input/Output Registers Bit 7 Name PIO7_SET Function PIO7 Set 0 = No effect. 1 = Set the PIO7 signal High. 6 PIO6_SET PIO6 Set 0 = No effect. 1 = Set the PIO6 signal High. 5 PIO5_SET PIO5 Set 0 = No effect. 1 = Set the PIO5 signal High. 4 PIO4_SET PIO4 Set 0 = No effect. 1 = Set the PIO4 signal High. 3 PIO3_SET PIO3 Set 0 = No effect. 1 = Set the PIO3 signal High. 2 PIO2_SET PIO2 Set 0 = No effect. 1 = Set the PIO2 signal High. 1 PIO1_SET PIO1 Set 0 = No effect. 1 = Set the PIO1 signal High. 0 PIO0_SET PIO0 Set 0 = No effect. 1 = Set the PIO0 signal High. Programming Notes Each PIOx_SET bit is used to drive the corresponding PIO output High. Writing a 1 to any bit of this register causes the corresponding PIO pin to be driven High if it is programmed to be an output (via the corresponding PIOx_DIR bit in the PIODIR15_0 register, see page 20-12). Writing 1 to a pin's PIOx_SET bit overrides any previous write to the pin's PIOx_DATA or PIOx_CLR bit (see page 20-16 and page 20-24). Writing 0 to any bit in this register has no effect. If a PIO pin is programmed to be an input, or if the pin is programmed for its interface function (via the corresponding PIOx_FNC bit in the PIOPFS15_0 register, see page 20-3), then writing to the pin's PIOx_SET bit has no effect. Although software can perform a 32-bit access of MMCR offset C34h to set bits across all 32 PIO pins with a single instruction, the 32-bit access is split into two separate 16-bit accesses, with the PIOSET15_0 register being accessed prior to the PIOSET31_16 register. The two writes are not simultaneous. ElanTMSC520 Microcontroller Register Set Manual 20-21 Programmable Input/Output Registers PIO31-PIO16 Set (PIOSET31_16) Memory-Mapped MMCR Offset C36h 15 Bit Reset R/W 14 PIO30_ SET x W! 6 PIO22_ SET x W! 13 PIO29_ SET x W! 5 PIO21_ SET x W! 12 PIO28_ SET x W! 4 PIO20_ SET x W! 11 PIO27_ SET x W! 3 PIO19_ SET x W! 10 PIO26_ SET x W! 2 PIO18_ SET x W! 9 PIO25_ SET x W! 1 PIO17_ SET x W! 8 PIO24_ SET x W! 0 PIO16_ SET x W! PIO31_ SET x W! 7 Bit Reset R/W PIO23_ SET x W! Register Description This register is used to make the output level High selectively for pins PIO31-PIO16. Bit Definitions Bit 15 Name PIO31_SET Function PIO31 Set 0 = No effect. 1 = Set the PIO31 signal High. PIO30 Set 0 = No effect. 1 = Set the PIO30 signal High. PIO29 Set 0 = No effect. 1 = Set the PIO29 signal High. PIO28 Set 0 = No effect. 1 = Set the PIO28 signal High. PIO27 Set 0 = No effect. 1 = Set the PIO27 signal High. PIO26 Set 0 = No effect. 1 = Set the PIO26 signal High. PIO25 Set 0 = No effect. 1 = Set the PIO25 signal High. PIO24 Set 0 = No effect. 1 = Set the PIO24 signal High. 14 PIO30_SET 13 PIO29_SET 12 PIO28_SET 11 PIO27_SET 10 PIO26_SET 9 PIO25_SET 8 PIO24_SET 20-22 ElanTMSC520 Microcontroller Register Set Manual Programmable Input/Output Registers Bit 7 Name PIO23_SET Function PIO23 Set 0 = No effect. 1 = Set the PIO23 signal High. 6 PIO22_SET PIO22 Set 0 = No effect. 1 = Set the PIO22 signal High. 5 PIO21_SET PIO21 Set 0 = No effect. 1 = Set the PIO21 signal High. 4 PIO20_SET PIO20 Set 0 = No effect. 1 = Set the PIO20 signal High. 3 PIO19_SET PIO19 Set 0 = No effect. 1 = Set the PIO19 signal High. 2 PIO18_SET PIO18 Set 0 = No effect. 1 = Set the PIO18 signal High. 1 PIO17_SET PIO17 Set 0 = No effect. 1 = Set the PIO17 signal High. 0 PIO16_SET PIO16 Set 0 = No effect. 1 = Set the PIO16 signal High. Programming Notes Each PIOx_SET bit is used to drive the corresponding PIO output High. Writing a 1 to any bit of this register causes the corresponding PIO pin to be driven High if it is programmed to be an output (via the corresponding PIOx_DIR bit in the PIODIR31_16 register, see page 20-14). Writing 1 to a pin's PIOx_SET bit overrides any previous write to the pin's PIOx_DATA or PIOx_CLR bit (see page 20-18 and page 20-26). Writing 0 to any bit in this register has no effect. If a PIO pin is programmed to be an input, or if the pin is programmed for its interface function (via the corresponding PIOx_FNC bit in the PIOPFS31_16 register, see page 20-5), then writing to the pin's PIOx_SET bit has no effect. Although software can perform a 32-bit access of MMCR offset C34h to set bits across all 32 PIO pins with a single instruction, the 32-bit access is split into two separate 16-bit accesses, with the PIOSET15_0 register being accessed prior to the PIOSET31_16 register. The two writes are not simultaneous. ElanTMSC520 Microcontroller Register Set Manual 20-23 Programmable Input/Output Registers PIO15-PIO0 Clear (PIOCLR15_0) Memory-Mapped MMCR Offset C38h 15 Bit Reset R/W 14 PIO14_ CLR x W! 6 PIO6_ CLR x W! 13 PIO13_ CLR x W! 5 PIO5_ CLR x W! 12 PIO12_ CLR x W! 4 PIO4_ CLR x W! 11 PIO11_ CLR x W! 3 PIO3_ CLR x W! 10 PIO10_ CLR x W! 2 PIO2_ CLR x W! 9 PIO9_ CLR x W! 1 PIO1_ CLR x W! 8 PIO8_ CLR x W! 0 PIO0_ CLR x W! PIO15_ CLR x W! 7 Bit Reset R/W PIO7_ CLR x W! Register Description This register is used to make the output level Low selectively for pins PIO15-PIO0. Bit Definitions Bit 15 Name PIO15_CLR Function PIO15 Clear 0 = No effect. 1 = Drive the PIO15 signal Low. PIO14 Clear 0 = No effect. 1 = Drive the PIO14 signal Low. PIO13 Clear 0 = No effect. 1 = Drive the PIO13 signal Low. PIO12 Clear 0 = No effect. 1 = Drive the PIO12 signal Low. PIO11 Clear 0 = No effect. 1 = Drive the PIO11 signal Low. PIO10 Clear 0 = No effect. 1 = Drive the PIO10 signal Low. PIO9 Clear 0 = No effect. 1 = Drive the PIO9 signal Low. PIO8 Clear 0 = No effect. 1 = Drive the PIO8 signal Low. 14 PIO14_CLR 13 PIO13_CLR 12 PIO12_CLR 11 PIO11_CLR 10 PIO10_CLR 9 PIO9_CLR 8 PIO8_CLR 20-24 ElanTMSC520 Microcontroller Register Set Manual Programmable Input/Output Registers Bit 7 Name PIO7_CLR Function PIO7 Clear 0 = No effect. 1 = Drive the PIO7 signal Low. 6 PIO6_CLR PIO6 Clear 0 = No effect. 1 = Drive the PIO6 signal Low. 5 PIO5_CLR PIO5 Clear 0 = No effect. 1 = Drive the PIO5 signal Low. 4 PIO4_CLR PIO4 Clear 0 = No effect. 1 = Drive the PIO4 signal Low. 3 PIO3_CLR PIO3 Clear 0 = No effect. 1 = Drive the PIO3 signal Low. 2 PIO2_CLR PIO2 Clear 0 = No effect. 1 = Drive the PIO2 signal Low. 1 PIO1_CLR PIO1 Clear 0 = No effect. 1 = Drive the PIO1 signal Low. 0 PIO0_CLR PIO0 Clear 0 = No effect. 1 = Drive the PIO0 signal Low. Programming Notes Each PIOx_CLR bit is used to drive the corresponding PIO output Low. Writing a 1 to any bit of this register causes the corresponding PIO pin to be driven Low if it is programmed to be an output (via the corresponding PIOx_DIR bit in the PIODIR15_0 register, see page 20-12). Writing 1 to a pin's PIOx_CLR bit overrides any previous write to the pin's PIOx_DATA or SET bit (see page 20-16 and page 20-20). Writing 0 to any bit in this register has no effect. If a PIO pin is programmed to be an input, or if the pin is programmed for its interface function (via the corresponding PIOx_FNC bit in the PIOPFS15_0 register, see page 20-3), then writing to the pin's PIOx_CLR bit has no effect. Although software can perform a 32-bit access of MMCR offset C38h to clear bits across all 32 PIO pins with a single instruction, the 32-bit access is split into two separate 16-bit accesses, with the PIOCLR15_0 register being accessed prior to the PIOCLR31_16 register. The two writes are not simultaneous. ElanTMSC520 Microcontroller Register Set Manual 20-25 Programmable Input/Output Registers PIO31-PIO16 Clear (PIOCLR31_16) Memory-Mapped MMCR Offset C3Ah 15 Bit Reset R/W 14 PIO30_ CLR x W! 6 PIO22_ CLR x W! 13 PIO29_ CLR x W! 5 PIO21_ CLR x W! 12 PIO28_ CLR x W! 4 PIO20_ CLR x W! 11 PIO27_ CLR x W! 3 PIO19_ CLR x W! 10 PIO26_ CLR x W! 2 PIO18_ CLR x W! 9 PIO25_ CLR x W! 1 PIO17_ CLR x W! 8 PIO24_ CLR x W! 0 PIO16_ CLR x W! PIO31_ CLR x W! 7 Bit Reset R/W PIO23_ CLR x W! Register Description This register is used to make the output level Low selectively for pins PIO31-PIO16. Bit Definitions Bit 15 Name PIO31_CLR Function PIO31 Clear 0 = No effect. 1 = Drive the PIO31 signal Low. PIO30 Clear 0 = No effect. 1 = Drive the PIO30 signal Low. PIO29 Clear 0 = No effect. 1 = Drive the PIO29 signal Low. PIO28 Clear 0 = No effect. 1 = Drive the PIO28 signal Low. PIO27 Clear 0 = No effect. 1 = Drive the PIO27 signal Low. PIO26 Clear 0 = No effect. 1 = Drive the PIO26 signal Low. PIO25 Clear 0 = No effect. 1 = Drive the PIO25 signal Low. PIO24 Clear 0 = No effect. 1 = Drive the PIO24 signal Low. 14 PIO30_CLR 13 PIO29_CLR 12 PIO28_CLR 11 PIO27_CLR 10 PIO26_CLR 9 PIO25_CLR 8 PIO24_CLR 20-26 ElanTMSC520 Microcontroller Register Set Manual Programmable Input/Output Registers Bit 7 Name PIO23_CLR Function PIO23 Clear 0 = No effect. 1 = Drive the PIO23 signal Low. 6 PIO22_CLR PIO22 Clear 0 = No effect. 1 = Drive the PIO22 signal Low. 5 PIO21_CLR PIO21 Clear 0 = No effect. 1 = Drive the PIO21 signal Low. 4 PIO20_CLR PIO20 Clear 0 = No effect. 1 = Drive the PIO20 signal Low. 3 PIO19_CLR PIO19 Clear 0 = No effect. 1 = Drive the PIO19 signal Low. 2 PIO18_CLR PIO18 Clear 0 = No effect. 1 = Drive the PIO18 signal Low. 1 PIO17_CLR PIO17 Clear 0 = No effect. 1 = Drive the PIO17 signal Low. 0 PIO16_CLR PIO16 Clear 0 = No effect. 1 = Drive the PIO16 signal Low. Programming Notes Each PIOx_CLR bit is used to drive the corresponding PIO output Low. Writing a 1 to any bit of this register causes the corresponding PIO pin to be driven Low if it is programmed to be an output (via the corresponding PIOx_DIR bit in the PIODIR31_16 register, see page 20-14). Writing 1 to a pin's PIOx_CLR bit overrides any previous write to the pin's PIOx_DATA or SET bit (see page 20-18 and page 20-22). Writing 0 to any bit in this register has no effect. If a PIO pin is programmed to be an input, or if the pin is programmed for its interface function (via the corresponding PIOx_FNC bit in the PIOPFS31_16 register, see page 20-5), then writing to the pin's PIOx_CLR bit has no effect. Although software can perform a 32-bit access of MMCR offset C38h to clear bits across all 32 PIO pins with a single instruction, the 32-bit access is split into two separate 16-bit accesses, with the PIOCLR15_0 register being accessed prior to the PIOCLR31_16 register. The two writes are not simultaneous. ElanTMSC520 Microcontroller Register Set Manual 20-27 Programmable Input/Output Registers 20-28 ElanTMSC520 Microcontroller Register Set Manual INDEX Numerics 12/24-Hour Mode Select bit field, 17-17 16550-Compatible Mode Error bit field, 18-21 16-bit Counter for Programmable Interval Timer Channel 0 bit field, 13-2 Channel 1 bit field, 13-3 Channel 2 bit field, 13-4 16-bit Millisecond Count bit field, 15-2 66 MHz Capable bit field, 6-20 66M_CAP bit field, 6-20 A A10-A8 bit field in MPICICW2 register, 12-32 in S1PICICW2 register, 12-57 in S2PICICW2 register, 12-45 A10-A8 of Interrupt Vector bit field in MPICICW2 register, 12-32 in S1PICICW2 register, 12-57 in S2PICICW2 register, 12-45 A20 Gate Control bit field, 3-9 A20 Gate Data bit field, 3-7 A20_GATE bit field, 3-7 A20G_CTL bit field, 3-9 Access is OCW3 bit field in MPICOCW2 register, 12-28 in MPICOCW3 register, 12-30 in S1PICOCW2 register, 12-53 in S1PICOCW3 register, 12-55 in S2PICOCW2 register, 12-41 in S2PICOCW3 register, 12-43 ADDDEC bit field in MSTDMAMODE register, 11-91 in SLDMAMODE register, 11-55 ADDDECCTL register, 2-2 Address Decode Control register, 2-2 Address Decrement bit field in MSTDMAMODE register, 11-91 in SLDMAMODE register, 11-55 Address Interval bit field in MPICICW1 register, 12-26 in S1PICICW1 register, 12-51 in S2PICICW1 register, 12-39 ADI bit field in MPICICW1 register, 12-26 in S1PICICW1 register, 12-51 in S2PICICW1 register, 12-39 ADR bit field, 2-9 ADx signal, 6-16 AEOI bit field in MPICICW4 register, 12-35 in S1PICICW4 register, 12-59 in S2PICICW4 register, 12-47 AINIT bit field in MSTDMAMODE register, 11-91 in SLDMAMODE register, 11-55 Alarm Interrupt Enable bit field, 17-16 Alarm Interrupt Flag bit field, 17-18 ALM_AM_PM bit field, 17-9 ALM_HOUR bit field, 17-9 ALM_INT_ENB bit field, 17-16 ALM_INT_FLG bit field, 17-18 ALM_MINUTE bit field, 17-7 ALM_SECOND bit field, 17-5 ALT_CMP bit field in GPTMR0CTL register, 14-5 in GPTMR1CTL register, 14-11 Alternate CPU Core Reset Control bit field, 3-9 Alternate Size for Channel x bit field, 11-4 AM_PM bit field, 17-8 Am5x86(R) CPU Control register, 4-3 instruction set, xvi MMCR registers (table), 4-1 AMDebugTM Technology Hard Reset Detect bit field, 3-5 RX/TX Interrupt Mapping register, 12-21 System Reset Detect bit field, 3-5 Arbiter Priority Control register, 5-6 ARBPRICTL register, 5-6 ATTR bit field, 2-7 Attribute bit field, 2-7 Automatic Delayed Transaction Enable bit field, 6-4 Automatic EOI Mode bit field in MPICICW4 register, 12-35 in S1PICICW4 register, 12-59 in S2PICICW4 register, 12-47 ElanTMSC520 Microcontroller Register Set Manual Index-1 Index Automatic Initialization Control bit field in MSTDMAMODE register, 11-91 in SLDMAMODE register, 11-55 Buffer Chaining Control register, 11-21 Enable for Channel x bit field, 11-21 Interrupt Enable register, 11-24 Status register, 11-22 Valid register, 11-25 Buffered Mode and Master/Slave Select bit field in MPICICW4 register, 12-35 in S1PICICW4 register, 12-59 in S2PICICW4 register, 12-47 Bus Number bit field, 6-15 BUS_MAS bit field, 6-21 BUS_NUM bit field, 6-15 BUS_PARK_SEL bit field, 5-2 B BAD_CHK_ENB bit field, 7-12 Bank x Column Address Width bit field, 7-5, 7-6 Enable bit field, 7-7, 7-8 Ending Address bit field, 7-7, 7-8 ending address configuration (figure), 7-8 Internal SDRAM Bank Count bit field, 7-5, 7-6 Base Class Code bit field, 6-22 baud rates, divisors, and clock source (table), 18-9 BAx signal, 20-10, 20-11 BBATSEN signal, 17-20 BCD bit field in PITMODECTL register, 13-8 in PITxSTA register, 13-6 BI bit field, 18-21 Binary Coded Decimal Select bit field, 13-8 Binary Coded Decimal Select Status bit field, 13-6 Bits 7-3 of Base Interrupt Vector Number for this PIC bit field in MPICICW2 register, 12-32 in S1PICICW2 register, 12-57 in S2PICICW2 register, 12-45 BNKx_BNK_CNT bit field, 7-5, 7-6 BNKx_COLWDTH bit field, 7-5, 7-6 BNKx_ENB bit field, 7-7, 7-8 BNKx_END bit field, 7-7, 7-8 BOOTCS Control register, 9-2 BOOTCS Device Delay for First Access bit field, 9-3 Delay for Subsequent Access bit field, 9-2 Mode bit field, 9-2 SDRAM/GP Bus Select bit field, 9-2 Width Select bit field, 9-2 BOOTCS signal, 1-2, 2-6, 9-1, 9-2, 9-3 BOOTCSCTL register, 9-2 Break Indicator bit field, 18-21 BSY bit field, 19-6 BUF bit field in MPICICW4 register, 12-35 in S1PICICW4 register, 12-59 in S2PICICW4 register, 12-47 BUF_M/S bit field in MPICICW4 register, 12-35 in S1PICICW4 register, 12-59 in S2PICICW4 register, 12-47 C Cache Write Mode bit field, 4-3 CACHE_WR_MODE bit field, 4-3 CAS_LAT bit field, 7-4 CBAR register, 2-9 CBEx signal, 6-17 CF_DRAM signal, 7-2 CF_ROM_GPCS signal, 7-2 CFG_DATA bit field, 6-17 CFGx signal, 9-2, 9-3 Chaining Buffer Valid for Channel x bit field, 11-25 Channel x DMA Request bit field in MSTDMASTA register, 11-86 in SLDMASTA register, 11-50 Channel x Slave Cascade Select bit field, 12-33, 12-34 Channel x Terminal Count bit field in MSTDMASTA register, 11-86 in SLDMASTA register, 11-50 Chip Select Pin Function Select register, 20-7 Chip Select Recovery Time bit field, 10-7 Chip Select x Device Delay for First Access bit field in ROMCS1CTL register, 9-5 in ROMCS2CTL register, 9-7 Delay for Subsequent Accesses bit field in ROMCS1CTL register, 9-4 in ROMCS2CTL register, 9-6 Mode bit field in ROMCS1CTL register, 9-4 in ROMCS2CTL register, 9-6 SDRAM/GP Bus Select bit field in ROMCS1CTL register, 9-4 in ROMCS2CTL register, 9-6 Width Select bit field in ROMCS1CTL register, 9-4 in ROMCS2CTL register, 9-6 Index-2 ElanTMSC520 Microcontroller Register Set Manual Index CHMASK bit field in MSTDMAMSK register, 11-90 in SLDMAMSK register, 11-54 CHx_ALT_SIZE bit field in GPDMACTL register, 11-4 CHx_BCHN_ENB bit field, 11-21 CHx_CBUF_VAL bit field, 11-25 CHx_CNT bit field in PIT0CNT register, 13-2 in PIT1CNT register, 13-3 in PIT2CNT register, 13-4 CHx_DIS bit field in MSTDMAGENMSK register, 11-97 in SLDMAGENMSK register, 11-61 CHx_EOB_STA bit field, 11-22, 11-23 CHx_INT_ENB bit field, 11-24 CHx_INT_MODE bit field in MPICMODE register, 12-6, 12-7 in SL1PICMODE register, 12-8 in SL2PICMODE register, 12-9 CL_CD bit field, 6-22 Class Code/Revision ID register, 6-22 Clear FPU Error Interrupt Request bit field, 12-61 Clear To Send bit field, 18-23 CLK_INV_ENB bit field, 19-3 CLK_MODE bit field, 11-4 CLK_PIN_DIR bit field, 20-9 CLK_PIN_ENB bit field, 20-9 CLK_SEL bit field, 19-2 CLK_SRC bit field, 18-3 CLK_TST_SEL bit field, 20-9 CLKSEL register, 20-9 CLKTEST signal Output Clock Select bit field, 20-9 Pin Direction bit field, 20-9 Pin Enable bit field, 20-9 CLKTIMER signal in PIT0CNT register, 13-2 in PIT1CNT register, 13-3 in PIT2CNT register, 13-4 Pin Direction bit field, 20-9 Pin Enable bit field, 20-9 Clock Mode bit field, 11-4 Clock Select register, 20-9 CMD_SEL bit field, 19-5 CMOS RAM Location bit field, 17-21 CMOSDATA bit field, 17-3 CMOSIDX bit field, 17-2 CNCR_MODE_ENB bit field, 5-2 CNT bit field in GPTMR0CNT register, 14-6 in GPTMR1CNT register, 14-12 in GPTMR2CNT register, 14-17 CNTx bit field, 13-11 CodeKit software, iii Compressed Timing bit field in MSTDMACTL register, 11-87 in SLDMACTL register, 11-51 COMPTIM bit field in MSTDMACTL register, 11-87 in SLDMACTL register, 11-51 Configuration Base Address register, 2-9 Configuration Data bit field, 6-17 CONT_CMP bit field in GPTMR0CTL register, 14-5 in GPTMR1CTL register, 14-11 in GPTMR2CTL register, 14-16 Counter Latch Command bit field in PITCNTLAT register, 13-10 in PITxSTA register, 13-5 Counter Mode bit field, 13-8 Counter Mode Status bit field, 13-6 Counter Read/Write Operation Control bit field in PITMODECTL register, 13-7 in PITxSTA register, 13-5 COUNTH bit field, 16-5 COUNTL bit field, 16-4 CPU Clock Speed bit field, 4-3 CPU Reset Control bit field, 3-7 CPU Shutdown Reset Detect bit field, 3-6 CPU_CLK_SPD bit field, 4-3 CPU_PRI bit field, 5-6 CPU_RST bit field in SCPDATA register, 3-7 in SYSCTLA register, 3-9 CPUCTL register, 4-3 Crystal Frequency bit field, 15-4 CSPFS register, 20-7 CTR_CMD bit field, 13-10 CTR_MODE bit field, 13-8 CTR_MODE_STA bit field, 13-6 CTR_RW_LATCH bit field, 13-7 CTR_SEL bit field in PITMODECTL register, 13-7 in PITRDBACK register, 13-11 in PTCNTLAT register, 13-10 CTS bit field, 18-23 CTS2 Function Select bit field, 20-5 CTSx signal in UARTxMCR register, 18-19, 18-20 in UARTxMSR register, 18-23, 18-24 ElanTMSC520 Microcontroller Register Set Manual Index-3 Index Current Count High bit field, 16-5 Current Count Low bit field, 16-4 Disable DMA Controller bit field in MSTDMACTL register, 11-87 in SLDMACTL register, 11-51 DIV bit field in UARTxBCDH register, 18-10 in UARTxBCDL register, 18-9 Divisor Latch Access bit field, 18-17 DLAB bit field, 18-17 DMA. See also GP-DMA, Master DMA, Slave DMA. DMA Buffer Chaining Interrupt Mapping register, 12-21 DMA Channel Mask bit field in MSTDMAMSK register, 11-90 in SLDMAMSK register, 11-54 DMA Channel Mask Select bit field in MSTDMAMSK register, 11-90 in SLDMAMSK register, 11-54 DMA Channel Select bit field in MSTDMAMODE register, 11-92 in MSTDMASWREQ register, 11-89 in SLDMAMODE register, 11-56 in SLDMASWREQ register, 11-53 DMA Channel x Extended Page Address bit field in GPDMAEXTPG0 register, 11-10 in GPDMAEXTPG1 register, 11-11 in GPDMAEXTPG2 register, 11-12 in GPDMAEXTPG3 register, 11-13 in GPDMAEXTPG5 register, 11-14 in GPDMAEXTPG6 register, 11-15 in GPDMAEXTPG7 register, 11-16 DMA Channel x Mask bit field in MSTDMAGENMSK register, 11-97 in SLDMAGENMSK register, 11-61 DMA Channel x Memory Address bit field in GPDMA4MAR register, 11-78 DMA Channel x Memory Address Bits [23-16] bit field in GPDMA0PG register, 11-69 in GPDMA1PG register, 11-65 in GPDMA2PG register, 11-63 in GPDMA3PG register, 11-64 in GPDMA5PG register, 11-73 in GPDMA6PG register, 11-71 DMA Channel x Memory Address Bits [23-17] bit field in GPDMA7PG register, 11-72 DMA Channel x Next Address High bit field in GPDMANXTADDH3 register, 11-27 in GPDMANXTADDH5 register, 11-29 in GPDMANXTADDH6 register, 11-31 in GPDMANXTADDH7 register, 11-33 DMA Channel x Next Address Low bit field in GPDMANXTADDL3 register, 11-26 in GPDMANXTADDL5 register, 11-28 in GPDMANXTADDL6 register, 11-30 in GPDMANXTADDL7 register, 11-32 D D_PERR_DET bit field, 6-20 dackx internal signal, 11-51, 11-87 DAKSEN bit field in MSTDMACTL register, 11-87 in SLDMACTL register, 11-51 DAT_IN bit field, 19-7 DAT_OUT bit field, 19-4 Data Carrier Detect bit field, 18-23 Data Parity Reported bit field, 6-20 Data Ready bit field, 18-22 Data Set Ready bit field, 18-23 Data Terminal Ready bit field, 18-20 Data Width Select for GPCSx bit field, 10-3 DATA_DRIVE bit field, 20-11 DATASTRB signal, 7-2 Date Mode bit field, 17-17 DATE_MODE bit field, 17-17 DAY_OF_MTH bit field, 17-11 DAY_OF_WEEK bit field, 17-10 Daylight Savings Enable bit field, 17-17 DBCTL register, 8-2 DCD bit field, 18-23 DCD2 Function Select bit field, 20-5 DCDx signal, 18-19, 18-23 DCTS bit field, 18-24 DDCD bit field, 18-23 DDSR bit field, 18-24 Delta Clear To Send bit field, 18-24 Delta Data Carrier Detect bit field, 18-23 Delta Data Set Ready bit field, 18-24 DEV_ID bit field, 6-18 Device ID bit field, 6-18 Device Number bit field, 6-16 Device Select (DEVSEL) Timing bit field, 6-20 Device/Vendor ID register, 6-18 DEVICE_NUM bit field, 6-16 DEVSEL signal, 6-20 DGP bit field in BOOTCSCTL register, 9-2 in ROMCS1CTL register, 9-4 in ROMCS2CTL register, 9-6 Directly Trigger Priority Level Px bit field in SWINT16_1 register, 12-10, 12-11, 12-12 in SWINT22_17 register, 12-13, 12-14 direct-mapped I/O registers (table), 1-7 Index-4 ElanTMSC520 Microcontroller Register Set Manual Index DMA Channel x Next Transfer Count High bit field in GPDMANXTTCH3 register, 11-35 in GPDMANXTTCH5 register, 11-37 in GPDMANXTTCH6 register, 11-39 in GPDMANXTTCH7 register, 11-41 DMA Channel x Next Transfer Count Low bit field in GPDMANXTTCL3 register, 11-34 in GPDMANXTTCL5 register, 11-36 in GPDMANXTTCL6 register, 11-38 in GPDMANXTTCL7 register, 11-40 DMA Channel x Transfer Count bit field in GPDMA0TC register, 11-43 in GPDMA1TC register, 11-45 in GPDMA2TC register, 11-47 in GPDMA3TC register, 11-49 in GPDMA4TC register, 11-79 in GPDMA5TC register, 11-81 in GPDMA6TC register, 11-83 in GPDMA7TC register, 11-85 DMA Channel x Transfer Count Extension bit field in GPDMAEXTTC3 register, 11-17 in GPDMAEXTTC5 register, 11-18 in GPDMAEXTTC6 register, 11-19 in GPDMAEXTTC7 register, 11-20 DMA Mode bit field in UARTxFCR register, 18-15 in UARTxFCRSHAD register, 18-5 DMA_DIS bit field in MSTDMACTL register, 11-87 in SLDMACTL register, 11-51 DMA_MODE bit field in UARTxFCR register, 18-15 in UARTxFCRSHAD register, 18-5 DMABCINTMAP register, 12-21 DMARx bit field in MSTDMASTA register, 11-86 in SLDMASTA register, 11-50 DMAx_MMAP bit field in GPDMAMMIO register, 11-5 DMAx_NXT_ADR bit field in GPDMANXTADDH3 register, 11-27 in GPDMANXTADDH5 register, 11-29 in GPDMANXTADDH6 register, 11-31 in GPDMANXTADDH7 register, 11-33 in GPDMANXTADDL3 register, 11-26 in GPDMANXTADDL5 register, 11-28 in GPDMANXTADDL6 register, 11-30 in GPDMANXTADDL7 register, 11-32 DMAx_NXT_TC bit field in GPDMANXTTCH3 register, 11-35 in GPDMANXTTCH5 register, 11-37 in GPDMANXTTCH6 register, 11-39 in GPDMANXTTCH7 register, 11-41 in GPDMANXTTCL3 register, 11-34 in GPDMANXTTCL5 register, 11-36 in GPDMANXTTCL6 register, 11-38 in GPDMANXTTCL7 register, 11-40 DMAxADR bit field in GPDMAEXTPG0 register, 11-10 in GPDMAEXTPG1 register, 11-11 in GPDMAEXTPG2 register, 11-12 in GPDMAEXTPG3 register, 11-13 in GPDMAEXTPG5 register, 11-14 in GPDMAEXTPG6 register, 11-15 in GPDMAEXTPG7 register, 11-16 DMAxMAR bit field in GPDMA0MAR register, 11-42 in GPDMA0PG register, 11-69 in GPDMA1MAR register, 11-44 in GPDMA1PG register, 11-65 in GPDMA2MAR register, 11-46 in GPDMA2PG register, 11-63 in GPDMA3MAR register, 11-48 in GPDMA3PG register, 11-64 in GPDMA4MAR register, 11-78 in GPDMA5MAR register, 11-80 in GPDMA5PG register, 11-73 in GPDMA6MAR register, 11-82 in GPDMA6PG register, 11-71 in GPDMA7MAR register, 11-84 in GPDMA7PG register, 11-72 DMAxTC bit field in GPDMA0TC register, 11-43 in GPDMA1TC register, 11-45 in GPDMA2TC register, 11-47 in GPDMA3TC register, 11-49 in GPDMA4TC register, 11-79 in GPDMA5TC register, 11-81 in GPDMA6TC register, 11-83 in GPDMA7TC register, 11-85 in GPDMAEXTTC3 register, 11-17 in GPDMAEXTTC5 register, 11-18 in GPDMAEXTTC6 register, 11-19 in GPDMAEXTTC7 register, 11-20 documentation support, iii documentation notation (table), xviii DR bit field, 18-22 DRAM Refresh Indicator bit field, 13-13 DRCBENDADR register, 7-7 DRCCFG register, 7-5 DRCCTL register, 7-2 DRCTMCTL register, 7-4 ElanTMSC520 Microcontroller Register Set Manual Index-5 Index Drive Strength Control register, 20-10 DRQSEN bit field in MSTDMACTL register, 11-87 in SLDMACTL register, 11-51 drqx internal signal, 11-51, 11-87 DS_ENB bit field, 17-17 DSCTL register, 20-10 DSR bit field, 18-23 DSR2 Function Select bit field, 20-5 DSRx signal in UARTxMCR register, 18-19, 18-20 in UARTxMSR register, 18-23, 18-24 DTR bit field, 18-20 DTRx signal, 18-19, 18-20 Enable bit field in CBAR register, 2-9 in PCICFGADR register, 6-15 Enable Modem Status Interrupt bit field, 18-11 Enable Multi-Bit Interrupt bit field, 7-9 Enable Received Data Available Interrupt bit field, 18-11 Enable Receiver Line Status Interrupt bit field, 18-11 Enable Single-bit Interrupt bit field, 7-9 Enable Transmitter Holding Register Empty Interrupt bit field, 18-11 Enable UART x Interrupts bit field, 18-19 ENB bit field in GPTMR0CTL register, 14-3 in GPTMR1CTL register, 14-9 in GPTMR2CTL register, 14-15 in WDTMRCTL register, 16-2 End of Current Buffer in Channel x bit field, 11-22, 11-23 ENH_MODE_ENB bit field, 11-4 Enhanced Mode Enable bit field, 11-4 Enter AMDebugTM Technology Mode on Next Reset bit field, 3-3 EOI bit in R_SL_EOI bit field, 12-28, 12-41, 12-53 EPS bit field, 18-17 ERDAI bit field, 18-11 ERLSI bit field, 18-11 ERR_IN_FIFO bit field, 18-21 ESMM_SMM bit field in MPICOCW3 register, 12-30 in S1PICOCW3 register, 12-55 in S2PICOCW3 register, 12-43 ETHREI bit field, 18-11 Even Parity Select bit field, 18-17 EXP_SEL bit field, 16-3 Exponent Select bit field, 16-3 EXT_CLK bit field in GPTMR0CTL register, 14-5 in GPTMR1CTL register, 14-11 E ECC check bit and data bit positions (figure), 7-11 ECC Check Bit Position register, 7-11 ECC Check Code Test register, 7-12 ECC check codes and associated data (table), 7-13 ECC Control register, 7-9 ECC Data Bit Position bit field, 7-11 ECC Enable for All Four Banks bit field, 7-9 ECC Interrupt Mapping register, 12-19 ECC Multi-Bit Error Address bit field, 7-15 ECC Multi-Bit Error Address register, 7-15 ECC NMI Enable bit field, 12-19 ECC Single-bit Error Address bit field, 7-14 ECC Single-Bit Error Address register, 7-14 ECC Status register, 7-10 ECC_CHK_POS bit field, 7-11 ECC_ENB bit field, 7-9 ECC_IRQ_MAP bit field, 12-20 ECC_NMI_ENB bit field, 12-19 ECCCKBPOS register, 7-11 ECCCKTEST register, 7-12 ECCCTL register, 7-9 ECCMAP register, 12-19 ECCMBADD register, 7-15 ECCSBADD register, 7-14 ECCSTA register, 7-10 ElanTMSC520 Microcontroller Revision ID register, 4-2 EMSI bit field, 18-11 Enable Bad ECC Check Bits bit field, 7-12 ENABLE bit field in CBAR register, 2-9 in PCICFGADR register, 6-15 F Fast Back-to-Back Capable bit field, 6-20 FBTB bit field, 6-20 FE bit field, 18-22 ferr internal signal, 12-61 FERRMAP register, 12-21 FIFO Enable bit field in UARTxFCR register, 18-16 in UARTxFCRSHAD register, 18-6 FIFO Mode Indication bit field, 18-12 FIFO_ENB bit field in UARTxFCR register, 18-16 in UARTxFCRSHAD register, 18-6 Index-6 ElanTMSC520 Microcontroller Register Set Manual Index FIFO_MODE bit field, 18-12 FIRST_DLY bit field in BOOTCSCTL register, 9-3 in ROMCS1CTL register, 9-5 in ROMCS2CTL register, 9-7 Floating Point Error Interrupt Clear register, 12-61 Floating Point Error Interrupt Mapping register, 12-21 Force Bad ECC Check Bits bit field, 7-12 FPUERR_RST bit field, 12-61 FPUERRCLR register, 12-61 Framing Error bit field, 18-22 FRC_BAD_CHK bit field, 7-12 Function Number bit field, 6-16 FUNCTION_NUM bit field, 6-16 GP Chip Select Data Width register, 10-3 Offset register, 10-9 Pulse Width register, 10-8 Qualification register, 10-5 Recovery Time register, 10-7 GP Echo Mode register, 10-2 GP Read Offset register, 10-11 GP Read Pulse Width register, 10-10 GP Timer 0 Count register, 14-6 Interrupt Mapping register, 12-21 Maxcount Compare A register, 14-7 Maxcount Compare B register, 14-8 Mode/Control register, 14-3 GP Timer 1 Count register, 14-12 Interrupt Mapping register, 12-21 Maxcount Compare A register, 14-13 Maxcount Compare B register, 14-14 Mode/Control register, 14-9 GP Timer 2 Count register, 14-17 Interrupt Mapping register, 12-21 Maxcount Compare A register, 14-18 Mode/Control register, 14-15 GP Timer x Alternate Compare bit field in GPTMR0CTL register, 14-5 in GPTMR1CTL register, 14-11 GP Timer x Continuous Mode bit field in GPTMR0CTL register, 14-5 in GPTMR1CTL register, 14-11 in GPTMR2CTL register, 14-16 GP Timer x Count Register bit field in GPTMR0CNT register, 14-6 in GPTMR1CNT register, 14-12 in GPTMR2CNT register, 14-17 GP Timer x Enable bit field in GPTMR0CTL register, 14-3 in GPTMR1CTL register, 14-9 in GPTMR2CTL register, 14-15 GP Timer x External Clock bit field in GPTMR0CTL register, 14-5 in GPTMR1CTL register, 14-11 GP Timer x Interrupt Enable bit field in GPTMR0CTL register, 14-4 in GPTMR1CTL register, 14-10 in GPTMR2CTL register, 14-16 GP Timer x Interrupt Status bit field, 14-2 GP Timer x Maxcount Compare Register In Use bit field in GPTMR0CTL register, 14-4 in GPTMR1CTL register, 14-10 G General 0 register, 11-62 General 1 register, 11-66 General 2 register, 11-67 General 3 register, 11-68 General 4 register, 11-70 General 5 register, 11-74 General 6 register, 11-75 General 7 register, 11-76 General 8 register, 11-77 General-Purpose CMOS RAM (114 bytes), 17-21 General-Purpose Interrupt Request GPIRQx Polarity bit field, 12-15, 12-16 General-Purpose R/W Register bit field in GPDMAGR0 register, 11-62 in GPDMAGR1 register, 11-66 in GPDMAGR2 register, 11-67 in GPDMAGR3 register, 11-68 in GPDMAGR4 register, 11-70 in GPDMAGR5 register, 11-74 in GPDMAGR6 register, 11-75 in GPDMAGR7 register, 11-76 in GPDMAGR8 register, 11-77 general-purpose timer MMCR registers (table), 14-1 GNT_TO_ID bit field, 5-3 GNT_TO_INT_ENB bit field, 5-2 GNT_TO_STA bit field, 5-3 GNTx signal, 5-3, 5-4, 5-5, 5-7 GP Bus Echo Mode Enable bit field, 10-2 minimum timing (table), 10-2 GP bus MMCR registers (table), 10-1 GP bus signal timing adjustment (figure), 10-7 ElanTMSC520 Microcontroller Register Set Manual Index-7 Index GP Timer x Maxcount Compare Register x bit field in GPTMR0MAXCMPA register, 14-7 in GPTMR0MAXCMPB register, 14-8 in GPTMR1MAXCMPA register, 14-13 in GPTMR1MAXCMPB register, 14-14 in GPTMR2MAXCMPA register, 14-18 GP Timer x Maximum Count bit field in GPTMR0CTL register, 14-4 in GPTMR1CTL register, 14-10 in GPTMR2CTL register, 14-16 GP Timer x Permit Enable Bit Write bit field in GPTMR0CTL register, 14-3 in GPTMR1CTL register, 14-9 in GPTMR2CTL register, 14-15 GP Timer x Prescaler bit field in GPTMR0CTL register, 14-5 in GPTMR1CTL register, 14-11 GP Timer x Retrigger bit field in GPTMR0CTL register, 14-4 in GPTMR1CTL register, 14-10 GP Timers Status register, 14-2 GP Write Offset register, 10-13 GP Write Pulse Width register, 10-12 GP_ALE_OFF bit field, 10-15 GP_ALE_WIDTH bit field, 10-14 GP_ECHO_ENB bit field, 10-2 GP_RD_OFF bit field, 10-11 GP_RD_WIDTH bit field, 10-10 GP_RST bit field, 3-3 GP_WR_OFF bit field, 10-13 GP_WR_WIDTH bit field, 10-12 GPAEN Function Select bit field, 20-4 GPALE signal Function Select bit field, 20-4 in GPALEOFF register, 10-15 in GPALEW register, 10-14 minimum timing table, 10-2 Offset register, 10-15 Pulse Width register, 10-14 GPALEOFF register, 10-15 GPALEW register, 10-14 GPBHE Function Select bit field, 20-4 GPBHE signal, 20-4 GPCS_OFF bit field, 10-9 GPCS_RECOVR bit field, 10-7 GPCS_WIDTH bit field, 10-8 GPCSDW register, 10-3 GPCSOFF register, 10-9 GPCSPW register, 10-8 GPCSQUAL register, 10-5 GPCSRT register, 10-7 GPCSx signal Function Select bit field, 20-5, 20-7, 20-8 in GPCSDW register, 10-3, 10-4 in GPCSOFF register, 10-9 in GPCSPW register, 10-8 in GPCSQUAL register, 10-5, 10-6 in GPCSRT register, 10-7 in PARx register, 2-7 Qualifier Selection bit field, 10-5, 10-6 GPCSx_DW bit field, 10-3 GPCSx_RW bit field, 10-5, 10-6 GPCSx_SEL bit field, 20-7, 20-8 GPDACKx Function Select bit field, 20-3 GPDACKx signal, 11-6, 11-7 GPDBUFOE Function Select bit field, 20-6 GP-DMA. See also DMA, Master DMA, Slave DMA. GP-DMA Channel 0 Extended Page register, 11-10 GP-DMA Channel 1 Extended Page register, 11-11 GP-DMA Channel 2 Extended Page register, 11-12 GP-DMA Channel 3 Extended Page register, 11-13 Extended Transfer Count register, 11-17 Next Address High register, 11-27 Next Address Low register, 11-26 Next Transfer Count High register, 11-35 Next Transfer Count Low register, 11-34 GP-DMA Channel 5 Extended Page register, 11-14 Extended Transfer Count register, 11-18 Next Address High register, 11-29 Next Address Low register, 11-28 Next Transfer Count High register, 11-37 Next Transfer Count Low register, 11-36 GP-DMA Channel 6 Extended Page register, 11-15 Extended Transfer Count register, 11-19 Next Address High register, 11-31 Next Address Low register, 11-30 Next Transfer Count High register, 11-39 Next Transfer Count Low register, 11-38 GP-DMA Channel 7 Extended Page register, 11-16 Extended Transfer Count register, 11-20 Next Address High register, 11-33 Next Address Low register, 11-32 Next Transfer Count High register, 11-41 Next Transfer Count Low register, 11-40 GP-DMA Control register, 11-4 GP-DMA direct-mapped registers (table), 11-2 GP-DMA Memory-Mapped I/O register, 11-5 GP-DMA MMCR registers (table), 11-1 GP-DMA Resource Channel Map A register, 11-6 GP-DMA Resource Channel Map B register, 11-8 GPDMA0MAR register, 11-42 Index-8 ElanTMSC520 Microcontroller Register Set Manual Index GPDMA0PG register, 11-69 GPDMA0TC register, 11-43 GPDMA1MAR register, 11-44 GPDMA1PG register, 11-65 GPDMA1TC register, 11-45 GPDMA2MAR register, 11-46 GPDMA2PG register, 11-63 GPDMA2TC register, 11-47 GPDMA3MAR register, 11-48 GPDMA3PG register, 11-64 GPDMA3TC register, 11-49 GPDMA4MAR register, 11-78 GPDMA4TC register, 11-79 GPDMA5MAR register, 11-80 GPDMA5PG register, 11-73 GPDMA5TC register, 11-81 GPDMA6MAR register, 11-82 GPDMA6PG register, 11-71 GPDMA6TC register, 11-83 GPDMA7MAR register, 11-84 GPDMA7PG register, 11-72 GPDMA7TC register, 11-85 GPDMABCCTL register, 11-21 GPDMABCSTA register, 11-22 GPDMABCVAL register, 11-25 GPDMABSINTENB register, 11-24 GPDMACTL register, 11-4 GPDMAEXTCHMAPA register, 11-6 GPDMAEXTCHMAPB register, 11-8 GPDMAEXTPG0 register, 11-10 GPDMAEXTPG1 register, 11-11 GPDMAEXTPG2 register, 11-12 GPDMAEXTPG3 register, 11-13 GPDMAEXTPG5 register, 11-14 GPDMAEXTPG6 register, 11-15 GPDMAEXTPG7 register, 11-16 GPDMAEXTTC3 register, 11-17 GPDMAEXTTC5 register, 11-18 GPDMAEXTTC6 register, 11-19 GPDMAEXTTC7 register, 11-20 GPDMAGR0 register, 11-62 GPDMAGR1 register, 11-66 GPDMAGR2 register, 11-67 GPDMAGR3 register, 11-68 GPDMAGR4 register, 11-70 GPDMAGR5 register, 11-74 GPDMAGR6 register, 11-75 GPDMAGR7 register, 11-76 GPDMAGR8 register, 11-77 GPDMAMMIO register, 11-5 GPDMANXTADDH3 register, 11-27 GPDMANXTADDH5 register, 11-29 GPDMANXTADDH6 register, 11-31 GPDMANXTADDH7 register, 11-33 GPDMANXTADDL3 register, 11-26 GPDMANXTADDL5 register, 11-28 GPDMANXTADDL6 register, 11-30 GPDMANXTADDL7 register, 11-32 GPDMANXTTCH3 register, 11-35 GPDMANXTTCH5 register, 11-37 GPDMANXTTCH6 register, 11-39 GPDMANXTTCH7 register, 11-41 GPDMANXTTCL3 register, 11-34 GPDMANXTTCL5 register, 11-36 GPDMANXTTCL6 register, 11-38 GPDMANXTTCL7 register, 11-40 GPDRQx signal Channel Mapping bit field, 11-6, 11-7 Function Select bit field, 20-4 in GPDMAEXTCHMAPA register, 11-6, 11-7 GPDRQx_CHSEL bit field, 11-6, 11-7 GPECHO register, 10-2 GPINTx_POL bit field, 12-15, 12-16 GPIOCS16 Function Select bit field, 20-5 GPIOCSx signal, 10-4 GPIORD signal Compressed Timing bit field in MSTDMACTL register, 11-87 in SLDMACTL register, 11-51 in GPCSQUAL register, 10-5, 10-6 in GPDMAMMIO register, 11-5 in GPRDOFF register, 10-11 in GPRDW register, 10-10 GPIOWR signal in GPCSQUAL register, 10-5, 10-6 in GPDMAMMIO register, 11-5 in GPWROFF register, 10-13 in GPWRW register, 10-12 Write Selection Control bit field in MSTDMACTL register, 11-87 in SLDMACTL register, 11-51 GPIRQx signal Function Select bit field, 20-3, 20-6 in INTPINPOL register, 12-15, 12-16 Interrupt Mapping register, 12-21 GPMEMCS16 Function Select bit field, 20-5 GPMEMCSx signal, 10-4 ElanTMSC520 Microcontroller Register Set Manual Index-9 Index GPMEMRD signal Compressed Timing bit field in MSTDMACTL register, 11-87 in SLDMACTL register, 11-51 in GPCSQUAL register, 10-5, 10-6 in GPDMAMMIO register, 11-5 in GPRDOFF register, 10-11 in GPRDW register, 10-10 GPMEMWR signal in GPCSQUAL register, 10-5, 10-6 in GPDMAMMIO register, 11-5 in GPWROFF register, 10-13 in GPWRW register, 10-12 Write Selection Control bit field in MSTDMACTL register, 11-87 in SLDMACTL register, 11-51 GPRDOFF register, 10-11 GPRDW register, 10-10 GPRDY Function Select bit field, 20-4 GPRESET signal reset sources, 3-6 Software GP Bus Reset bit field, 3-3 GPTC signal Function Select bit field, 20-4 in GPDMABCVAL register, 11-25 in UARTxCTL register, 18-3 in UARTxSTA register, 18-4 GPTMR0CNT register, 14-6 GPTMR0CTL register, 14-3 GPTMR0MAP register, 12-21 GPTMR0MAXCMPA register, 14-7 GPTMR0MAXCMPB register, 14-8 GPTMR1CNT register, 14-12 GPTMR1CTL register, 14-9 GPTMR1MAP register, 12-21 GPTMR1MAXCMPA register, 14-13 GPTMR1MAXCMPB register, 14-14 GPTMR2CNT register, 14-17 GPTMR2CTL register, 14-15 GPTMR2MAP register, 12-21 GPTMR2MAXCMPA register, 14-18 GPTMRSTA register, 14-2 GPWROFF register, 10-13 GPWRW register, 10-12 GPxIMAP register, 12-21 HBTGTIRQSTA register, 6-7 HDR_TYP bit field, 6-23 Header Type bit field, 6-23 Header Type register, 6-23 HI_PRI_0_SEL bit field, 5-7 HI_PRI_1_SEL bit field, 5-7 Host Bridge Control register, 6-3 Host Bridge Master Interrupt Address register, 6-14 Host Bridge Master Interrupt Control register, 6-9 Host Bridge Master Interrupt Status register, 6-12 Host Bridge Target Interrupt Control register, 6-5 Host Bridge Target Interrupt Status register, 6-7 HOUR bit field, 17-8 HOUR_MODE_SEL bit field, 17-17 I I/O Hole Access Destination bit field, 2-2 I/O Pad Drive Strength for MA12-MA0 and BA1-BA0 bit field, 20-11 for MD31-MD0 and MECC6-MECC0 bit field, 20-11 for SCS3-SCS0 bit field, 20-10 for SDQM3-SDQM0 bit field, 20-10 for SRASA-SRASB, SCASA-SCASB and SWEA- SWEB bit field, 20-10 I/O Space Enable bit field, 6-21 IC4 bit field in MPICICW1 register, 12-27 in S1PICICW1 register, 12-52 in S2PICICW1 register, 12-40 ICE_HRST_DET bit field, 3-5 ICE_ON_RST bit field, 3-3 ICE_SRST_DET bit field, 3-5 ICEMAP register, 12-21 ID2-ID0 bit field in S1PICICW3 register, 12-58 in S2PICICW3 register, 12-46 ignne internal signal, 12-61 IMx bit field in MPICINTMSK register, 12-36 in S1PICINTMSK register, 12-60 in S2PICINTMSK register, 12-48 Initialization Control Word 1 Select bit field in MPICOCW3 register, 12-30 in S1PICICW1 register, 12-51 in S1PICOCW2 register, 12-53 in S1PICOCW3 register, 12-55 in S2PICICW1 register, 12-39 in S2PICOCW2 register, 12-41 in S2PICOCW3 register, 12-43 H HBCTL register, 6-3 HBMSTIRQCTL register, 6-9 HBMSTIRQSTA register, 6-12 HBTGTIRQCTL register, 6-5 Index-10 ElanTMSC520 Microcontroller Register Set Manual Index Initialization Control Word 4 bit field in MPICICW1 register, 12-27 in S1PICICW1 register, 12-52 in S2PICICW1 register, 12-40 instruction set, xvi INT_ENB bit field in GPTMR0CTL register, 14-4 in GPTMR1CTL register, 14-10 in GPTMR2CTL register, 14-16 INT_FLG bit field, 17-18 INT_ID bit field, 18-13 INT_MAP bit field, 12-22 INT_NOT_PND bit field, 18-13 Internal dackx Sense bit field in MSTDMACTL register, 11-87 in SLDMACTL register, 11-51 Internal drqx Sense bit field in MSTDMACTL register, 11-87 in SLDMACTL register, 11-51 Internal Oscillator Control Bits bit field, 17-14 Interrupt Control register, 12-4 Interrupt Enable for Channel x bit field, 11-24 Interrupt Identification Bit Field bit field, 18-13 Interrupt Mapping bit field, 12-22 Interrupt Pin Polarity register, 12-15 Interrupt Request EOI and Priority Rotation Controls bit field in MPICOCW2 register, 12-28 in S1PICOCW2 register, 12-53 in S2PICOCW2 register, 12-41 Interrupt Request Flag bit field in RTCSTAC register, 17-18 in WDTMRCTL register, 16-2 Interrupt Request x bit field in MPICIR register, 12-24 in S1PICIR register, 12-49 in S2PICIR register, 12-37 Interrupt Request x In-Service bit field in MPICISR register, 12-25 in S1PICISR register, 12-50 in S2PICISR register, 12-38 INTPINPOL register, 12-15 INTx signal, 12-15 INTx_POL bit field, 12-15 IO_ENB bit field, 6-21 IO_HOLE_DEST bit field, 2-2 IOCHCK bit field, 13-13 IRQ_FLG bit field, 16-2 IRx bit field in MPICIR register, 12-24 in S1PICIR register, 12-49 in S2PICIR register, 12-37 IRx Mask bit field in MPICINTMSK register, 12-36 in S1PICINTMSK register, 12-60 in S2PICINTMSK register, 12-48 IS_OCW3 bit field in MPICOCW2 register, 12-28 in MPICOCW3 register, 12-30 in S1PICOCW2 register, 12-53 in S1PICOCW3 register, 12-55 in S2PICOCW2 register, 12-41 in S2PICOCW3 register, 12-43 ISx bit field in MPICISR register, 12-25 in S1PICISR register, 12-50 in S2PICISR register, 12-38 L Latch Count (Low True) bit field, 13-11 Latch Status (Low True) bit field, 13-11 LCNT bit field, 13-11 Level-Triggered Interrupt Mode bit field in MPICICW1 register, 12-26 in S1PICICW1 register, 12-51 in S2PICICW1 register, 12-39 literature support, iii LOOP bit field, 18-19 Loopback Mode (Diagnostic Mode) Enable bit field, 18-19 Lower 16 Bits of DMA Channel x Memory Address bit field in GPDMA0MAR register, 11-42 in GPDMA1MAR register, 11-44 in GPDMA2MAR register, 11-46 in GPDMA3MAR register, 11-48 in GPDMA5MAR register, 11-80 in GPDMA6MAR register, 11-82 in GPDMA7MAR register, 11-84 LS bit field in MPICOCW2 register, 12-28 in S1PICOCW2 register, 12-54 in S2PICOCW2 register, 12-41 LSTAT bit field, 13-11 LTIM bit field in MPICICW1 register, 12-26 in S1PICICW1 register, 12-51 in S2PICICW1 register, 12-39 M M/S bit field in MPICICW4 register, 12-35 in S1PICICW4 register, 12-59 in S2PICICW4 register, 12-47 ElanTMSC520 Microcontroller Register Set Manual Index-11 Index M_AD_IRQ_ID bit field, 6-14 M_CMD_IRQ_ID bit field, 6-12 M_DPER_IRQ_ENB bit field, 6-10 M_DPER_IRQ_SEL bit field, 6-10 M_DPER_IRQ_STA bit field, 6-13 M_GINT_MODE bit field, 12-5 M_MABRT_IRQ_ENB bit field, 6-10 M_MABRT_IRQ_SEL bit field, 6-9 M_MABRT_IRQ_STA bit field, 6-13 M_RETRY_TO bit field, 6-24 M_RPER_IRQ_ENB bit field, 6-10 M_RPER_IRQ_SEL bit field, 6-10 M_RPER_IRQ_STA bit field, 6-13 M_RTRTO_IRQ_ENB bit field, 6-10 M_RTRTO_IRQ_SEL bit field, 6-9 M_RTRTO_IRQ_STA bit field, 6-13 M_SERR_IRQ_ENB bit field, 6-10 M_SERR_IRQ_SEL bit field, 6-9 M_SERR_IRQ_STA bit field, 6-13 M_TABRT_IRQ_ENB bit field, 6-10 M_TABRT_IRQ_SEL bit field, 6-9 M_TABRT_IRQ_STA bit field, 6-13 M_WPOST_ENB bit field, 6-4 MA_DRIVE bit field, 20-11 Major Stepping Level bit field, 4-2 MAJORSTEP bit field, 4-2 Master Abort Interrupt Enable bit field, 6-10 Select bit field, 6-9 Status bit field, 6-13 Master Address Interrupt Identification bit field, 6-14 Master Command Interrupt Identification bit field, 6-12 Master Controller Write Posting Enable bit field, 6-4 Master Detected Parity Error Interrupt Enable bit field, 6-10 Select bit field, 6-10 Status bit field, 6-13 Master DMA. See also DMA, GP-DMA, Slave DMA. Master DMA Channel 4 Memory Address register, 11-78 Transfer Count register, 11-79 Master DMA Channel 4-7 Control register, 11-87 Mask register, 11-90 Mode register, 11-91 Status register, 11-86 Master DMA Channel 5 Memory Address register, 11-80 Page register, 11-73 Transfer Count register, 11-81 Master DMA Channel 6 Memory Address register, 11-82 Page register, 11-71 Transfer Count register, 11-83 Master DMA Channel 7 Memory Address register, 11-84 Page register, 11-72 Transfer Count register, 11-85 Master DMA Clear Byte Pointer register, 11-93 Master DMA Controller Reset register, 11-94 Master DMA Controller Temporary register, 11-95 Master DMA General Mask register, 11-97 Master DMA Mask Reset register, 11-96 Master Enable bit field, 6-21 Master NMI Enable bit field, 12-4 Master PIC Channel x Interrupt Mode bit field, 12-6, 12-7 Global Interrupt Mode Enable bit field, 12-5 I/O Port 0020h access summary (table), 12-27 Initialization Control Word 1 register, 12-26 Initialization Control Word 2 register, 12-32 Initialization Control Word 3 register, 12-33 Initialization Control Word 4 register, 12-35 In-Service register, 12-25 Interrupt Mask register, 12-36 Interrupt Mode register, 12-6 Interrupt Request register, 12-24 Operation Control Word 2 register, 12-28 Operation Control Word 3 register, 12-30 Master Received Parity Error Interrupt Enable bit field, 6-10 Select bit field, 6-10 Status bit field, 6-13 Master Retry Time-Out Interrupt Enable bit field, 6-10 Select bit field, 6-9 Status bit field, 6-13 Master Retry Time-Out register, 6-24 Master Software DRQ(n) Request register, 11-89 Master System Error Interrupt Enable bit field, 6-10 Select bit field, 6-9 Status bit field, 6-13 Master Target Abort Interrupt Enable bit field, 6-10 Select bit field, 6-9 Status bit field, 6-13 MASTR_CBP bit field, 11-93 MASTR_MSK_RST bit field, 11-96 MASTR_RST bit field, 11-94 MASTR_TMP bit field, 11-95 MATCH bit field, 2-10 Index-12 ElanTMSC520 Microcontroller Register Set Manual Index MAx signal in DRCCTL register, 7-3 in DSCTL register, 7-3, 20-10, 20-11 MAX_CNT bit field in GPTMR0CTL register, 14-4 in GPTMR1CTL register, 14-10 in GPTMR2CTL register, 14-16 MAX_CNT_RIU bit field in GPTMR0CTL register, 14-4 in GPTMR1CTL register, 14-10 MB_ADDR bit field, 7-15 MBIT_ERR bit field, 7-10 MCA bit field in GPTMR0MAXCMPA register, 14-7 in GPTMR1MAXCMPA register, 14-13 in GPTMR2MAXCMPA register, 14-18 MCB bit field in GPTMR0MAXCMPB register, 14-8 in GPTMR1MAXCMPB register, 14-14 MDx signal, 20-10, 20-11 MECCx signal, 20-10, 20-11 MEM_ENB bit field, 6-21 Memory Access Enable bit field, 6-21 memory write and invalidate enable bit not implemented, 6-21 memory-mapped configuration region (MMCR) registers (table), 1-2 Memory-Mapped Device for DMA Channel x bit field, 11-5 microcontroller reset sources (table), 3-6 Microprocessor Mode bit field in MPICICW4 register, 12-35 in S1PICICW4 register, 12-59 in S2PICICW4 register, 12-47 Minor Stepping Level bit field, 4-2 MINORSTEP bit field, 4-2 MINUTE bit field, 17-6 MODE bit field in BOOTCSCTL register, 9-2 in ROMCS1CTL register, 9-4 in ROMCS2CTL register, 9-6 MODSEL bit field in MSTDMAMODE register, 11-92 in SLDMAMODE register, 11-56 MONTH bit field, 17-12 MPICICW1 register, 12-26 MPICICW2 register, 12-32 MPICICW3 register, 12-33 MPICICW4 register, 12-35 MPICINTMSK register, 12-36 MPICIR register, 12-24 MPICISR register, 12-25 MPICMODE register, 12-6 MPICOCW2 register, 12-28 MPICOCW3 register, 12-30 MS_CNT bit field, 15-2 MSBF_ENB bit field, 19-3 MSKSEL bit field in MSTDMAMSK register, 11-90 in SLDMAMSK register, 11-54 MSTDMACBP register, 11-93 MSTDMACTL register, 11-87 MSTDMAGENMSK register, 11-97 MSTDMAMODE register, 11-91 MSTDMAMSK register, 11-90 MSTDMAMSKRST register, 11-96 MSTDMARST register, 11-94 MSTDMASTA register, 11-86 MSTDMASWREQ register, 11-89 MSTDMATMP register, 11-95 MSTINTADD register, 6-14 MULT_INT_ENB bit field, 7-9 Multi-Bit Error Detected bit field, 7-10 N NMI Routine Done bit field, 12-4 NMI_DONE bit field, 12-4 NMI_ENB bit field, 12-4 NMI_TRIG bit field, 12-13 No Serial Port Interrupt Pending bit field, 18-13 Null Count bit field, 13-5 NULL_CNT bit field, 13-5 O OE bit field, 18-22 Offset Time for GPALE bit field, 10-15 for GPIORD and GPMEMRD bit field, 10-11 for GPIOWR and GPMEMWR bit field, 10-13 for the GP Bus Chip Select bit field, 10-9 Operation Select bit field in MSTDMAMODE register, 11-91 in SLDMAMODE register, 11-55 OPMODE_SEL bit field, 7-3 OPSEL bit field in MSTDMAMODE register, 11-91 in SLDMAMODE register, 11-55 OSC_CTL bit field, 17-14 OUT1 bit field, 18-19 OUT2 bit field, 18-19 OUTPUT bit field, 13-5 ElanTMSC520 Microcontroller Register Set Manual Index-13 Index Output State bit field, 13-5 Overrun Error bit field, 18-22 PCICFGADR register, 6-15 PCICFGDATA register, 6-17 PCIDEVID register, 6-18 PCIHEADTYPE register, 6-23 PCIHOSTMAP register, 12-17 PCIINTAMAP register, 12-21 PCIINTBMAP register, 12-21 PCIINTCMAP register, 12-21 PCIINTDMAP register, 12-21 PCIMRETRYTO register, 6-24 PCISTACMD register, 6-19 PE bit field, 18-22 PENB bit field, 18-17 PER_INT_ENB bit field, 17-16 PER_INT_FLG bit field, 17-18 Periodic Interrupt Enable bit field, 17-16 Flag bit field, 17-18 PERR bit field, 13-13 PERR signal in HBMSTIRQCTL register, 6-10 in PCISTACMD register, 6-20 PERR signal in HBMSTIRQCTL register, 6-10 PERR_DET bit field, 6-19 PERR_RES bit field, 6-21 PG_SZ bit field, 2-7 PHS_INV_ENB bit field, 19-3 PIC Poll Command bit field in MPICOCW3 register, 12-30 in S1PICOCW3 register, 12-55 in S2PICOCW3 register, 12-43 PICICR register, 12-4 PIO register programming summary (table), 20-2 PIO15-PIO0 signals Clear register, 20-24 Data register, 20-16 Direction register, 20-12 Pin Function Select register, 20-3 Set register, 20-20 PIO31-PIO16 signals Clear register, 20-26 Data register, 20-18 Direction register, 20-14 Pin Function Select register, 20-5 Set register, 20-22 PIOCLR15_0 register, 20-24 PIOCLR31_16 register, 20-26 PIODATA15_0 register, 20-16 PIODATA31_16 register, 20-18 PIODIR15_0 register, 20-12 PIODIR31_16 register, 20-14 PIOPFS15_0 register, 20-3 P P bit field in MPICOCW3 register, 12-30 in S1PICOCW3 register, 12-55 in S2PICOCW3 register, 12-43 P_ENB_WR bit field in GPTMR0CTL register, 14-3 in GPTMR1CTL register, 14-9 in GPTMR2CTL register, 14-15 Page Size bit field, 2-7 PAR signal, 2-8 Parity Enable bit field, 18-17 Parity Error bit field, 18-22 Parity Error Detected bit field, 6-19 Parity Error Response bit field, 6-21 PARx register, 2-5 PC/AT Channel Check Indicator bit field, 13-13 PC/AT Parity Error Indicator bit field, 13-13 PCI Bus Arbiter Bus Park bit field, 5-2 CPU Priority bit field, 5-6 Grant Time-Out Identification bit field, 5-3 Interrupt Enable bit field, 5-2 Status bit field, 5-3 High Priority 0 bit field, 5-7 High Priority 1 bit field, 5-7 Request #x Enable bit field, 5-4, 5-5 Status register, 5-3 PCI Bus Host Bridge direct-mapped registers (table), 6-2 indexed registers (table), 6-2 MMCR registers (table), 6-1 PCI Bus Reset bit field, 6-3 PCI Configuration Address register, 6-15 Data register, 6-17 PCI Host Bridge Interrupt Mapping bit field, 12-18 Interrupt Mapping register, 12-17 NMI Enable bit field, 12-17 PCI indexed registers (table), 1-11 PCI Interrupt Request INTx Polarity bit field, 12-15 PCI Interrupt x Mapping register, 12-21 PCI_IRQ_MAP bit field, 12-18 PCI_NMI_ENB bit field, 12-17 PCI_RST bit field, 6-3 PCIARBSTA register, 5-3 PCICCREVID register, 6-22 Index-14 ElanTMSC520 Microcontroller Register Set Manual Index PIOPFS31_16 register, 20-5 PIOSET15_0 register, 20-20 PIOSET31_16 register, 20-22 PIOx Clear bit field in PIOCLR15_0 bit field, 20-24, 20-25 in PIOCLR31_16 bit field, 20-26, 20-27 PIOx Function Select bit field in PIOPFS15_0 register, 20-3, 20-4 in PIOPFS31_16 register, 20-5, 20-6 PIOx Input or Output Select bit field in PIODIR15_0 bit field, 20-12, 20-13 in PIODIR31_16 bit field, 20-14, 20-15 PIOx Set bit field in PIOSET15_0 bit field, 20-20, 20-21 in PIOSET31_16 bit field, 20-22, 20-23 PIOx_CLR bit field in PIOCLR15_0 register, 20-24, 20-25 in PIOCLR31_16 register, 20-26, 20-27 PIOx_DATA bit field in PIODATA15_0 register, 20-16, 20-17 in PIODATA31_16 register, 20-18, 20-19 PIOx_DIR bit field in PIODIR15_0 register, 20-12, 20-13 in PIODIR31_16 register, 20-14, 20-15 PIOx_FNC bit field in PIOPFS15_0 register, 20-3, 20-4 in PIOPFS31_16 register, 20-5, 20-6 PIOx_SET bit field in PIOSET15_0 register, 20-20, 20-21 in PIOSET31_16 register, 20-22, 20-23 PIT Channel x Count register Channel 0, 13-2 Channel 1, 13-3 Channel 2, 13-4 PIT Counter Latch Command register, 13-10 PIT counter mode settings (table), 13-9 PIT Counter Select bit field in PITCNTLAT bit field, 13-10 in PITMODECTL bit field, 13-7 in PITRDBACK bit field, 13-11 PIT Mode Control register, 13-7 PIT Output Channel 2 Enable bit field, 13-13 PIT Read-Back Command register, 13-11 PIT Timer 2 Output Pin State bit field, 13-13 PIT x Interrupt Mapping register Channel 0, 12-21 Channel 1, 12-21 Channel 2, 12-21 PIT x Status register Channel 0, 13-5 Channel 1, 13-5 Channel 2, 13-5 PIT_GATE2 bit field, 13-13 PIT_OUT2_ENB bit field, 13-13 PIT_OUT2_STA bit field, 13-13 PIT0CNT register, 13-2 PIT0MAP register, 12-21 PIT0STA register, 13-5 PIT1CNT register, 13-3 PIT1MAP register, 12-21 PIT1STA register, 13-5 PIT2CNT register, 13-4 PIT2MAP register, 12-21 PIT2STA register, 13-5 PITCNTLAT register, 13-10 PITGATE2 Function Select bit field, 20-7 PITGATE2 signal, 13-9, 13-13, 20-7 PITMODECTL register, 13-7 PITOUT2 signal, 13-5, 13-13 PITRDBACK register, 13-11 PM bit field in MPICICW4 register, 12-35 in S1PICICW4 register, 12-59 in S2PICICW4 register, 12-47 PORT80 bit field, 11-62 PORT84 bit field, 11-66 PORT85 bit field, 11-67 PORT86 bit field, 11-68 PORT88 bit field, 11-70 PORT8C bit field, 11-74 PORT8D bit field, 11-75 PORT8E bit field, 11-76 PORT8F bit field, 11-77 POWERGOOD Reset Detect bit field, 3-6 PRG_IF bit field, 6-22 PRG_RST_ENB bit field, 3-3 PRGRESET Detect bit field, 3-6 PRGRESET signal in RESCFG register, 3-3, 3-4 in RESSTA register, 3-6 PRGRESET signal in RESSTA register, 3-5 PRGRST_DET bit field, 3-6 Priority Type bit field in MSTDMACTL register, 11-87 in SLDMACTL register, 11-51 PRITYPE bit field in MSTDMACTL register, 11-87 in SLDMACTL register, 11-51 Product Type of ElanTMSC520 Microcontroller bit field, 4-2 PRODUCT_ID bit field, 4-2 Program Interface bit field, 6-22 Programmable Address Region x register, 2-5 programmable I/O MMCR registers (table), 20-1 Index-15 ElanTMSC520 Microcontroller Register Set Manual Index programmable interrupt controller direct-mapped registers (table), 12-2 MMCR registers (table), 12-1 programmable interval timer direct-mapped registers (table), 13-1 Programmable Reset Enable bit field, 3-3 PSC_SEL bit field in GPTMR0CTL register, 14-5 in GPTMR1CTL register, 14-11 PWRGOOD signal in BOOTCSCTL register, 9-2 in RESCFG register, 3-4 in RESSTA register, 3-6 in SYSINFO register, 3-2 PWRGOOD_DET bit field, 3-6 REQDMA bit field in MSTDMASWREQ register, 11-89 in SLDMASWREQ register, 11-53 REQSEL bit field in MSTDMASWREQ register, 11-89 in SLDMASWREQ register, 11-53 Request To Send bit field, 18-20 REQx signal, 5-4, 5-5, 5-7 REQx_ENB bit field, 5-4, 5-5 RESCFG register, 3-3 Reset Configuration register, 3-3 reset generation direct-mapped registers (table), 3-1 MMCR registers (table), 3-1 reset sources (table), 3-6 Reset Latched Input Data bit field, 3-2 Reset Status register, 3-5 RESSTA register, 3-5 REV_ID bit field, 6-22 REVID register, 4-2 Revision I.D. bit field, 6-22 RF_CLR bit field in UARTxFCR register, 18-15 in UARTxFCRSHAD register, 18-5 RFD bit field, 13-13 RFRT bit field in UARTxFCR register, 18-15 in UARTxFCRSHAD register, 18-5 RFSH_ENB bit field, 7-2 RFSH_SPD bit field, 7-2 RI bit field, 18-23 RIN2 Function Select bit field, 20-5 Ring Indicator bit field, 18-23 RINx signal, 18-19, 18-23, 20-5 ROM controller MMCR registers (table), 9-1 ROMCS1CTL register, 9-4 ROMCS2CTL register, 9-6 ROMCSx signal Function Select bit field, 20-7, 20-8 in PARx registers, 2-6 in ROMCS1CTL register, 9-4 in ROMCS2CTL register, 9-6 RR_RIS bit field in MPICOCW3 register, 12-30 in S1PICOCW3 register, 12-55 in S2PICOCW3 register, 12-43 RST signal in HBCTL register, 6-3 reset sources, 3-6 RST_LD bit field, 3-2 RSTLDx signal, 3-2 R R bit in R_SL_EOI bit field, 12-28, 12-41, 12-53 R_MST_ABT bit field, 6-20 R_SL_EOI bit field in MPICOCW2 register, 12-28 in S1PICOCW2 register, 12-53 in S2PICOCW2 register, 12-41 R_TGT_ABT bit field, 6-20 RAB_ENB bit field, 8-2 RAS_CAS_DLY bit field, 7-4 RAS_PCHG_DLY bit field, 7-4 Rate Selection bit field, 17-15 RATE_SEL bit field, 17-15 RBR bit field, 18-8 Read or Write the PIOx Pin bit field in PIODATA15_0 register, 20-16, 20-17 in PIODATA31_16 register, 20-18, 20-19 Read-Ahead Feature Enable bit field, 8-2 Read-back Command bit field, 13-11 real-time clock direct-mapped registers (table), 17-1 indexed registers (table), 1-11, 17-1 Received Master Abort bit field, 6-20 Received Target Abort bit field, 6-20 Receiver FIFO Clear bit field in UARTxFCR register, 18-15 in UARTxFCRSHAD register, 18-5 Receiver FIFO Register Trigger Bits bit field in UARTxFCR register, 18-15 in UARTxFCRSHAD register, 18-5 Refresh Enable bit field, 7-2 Region Size/Start Address bit field, 2-8 Register Number bit field, 6-16 REGISTER_NUM bit field, 6-16 Index-16 ElanTMSC520 Microcontroller Register Set Manual Index RTC Alarm AM/PM Indicator bit field, 17-9 Hour register, 17-9 Minute register, 17-7 Second register, 17-5 RTC AM/PM Indicator bit field, 17-8 RTC Control A register, 17-14 RTC Control B register, 17-16 RTC Current Day of the Month register, 17-11 RTC Current Day of the Week register, 17-10 RTC Current Hour register, 17-8 RTC Current Minute register, 17-6 RTC Current Month register, 17-12 RTC Current Second register, 17-4 RTC Current Year register, 17-13 RTC Disable bit field, 2-3 RTC Interrupt Mapping register, 12-21 RTC Status C register, 17-18 RTC Status D register, 17-20 RTC/CMOS Data Port bit field, 17-3 RTC/CMOS RAM Data Port register, 17-3 RTC/CMOS RAM Index bit field, 17-2 RTC/CMOS RAM Index register, 17-2 RTC_CMOS_REG_X bit field, 17-21 RTC_DIS bit field, 2-3 RTC_VRT bit field, 17-20 RTCALMHR register, 17-9 RTCALMMIN register, 17-7 RTCALMSEC register, 17-5 RTCCMOS register, 17-21 RTCCTLA register, 17-14 RTCCTLB register, 17-16 RTCCURDOM register, 17-11 RTCCURDOW register, 17-10 RTCCURHR register, 17-8 RTCCURMIN register, 17-6 RTCCURMON register, 17-12 RTCCURSEC register, 17-4 RTCCURYR register, 17-13 RTCDATA register, 17-3 RTCIDX register, 17-2 RTCMAP register, 12-21 RTCSTAC register, 17-18 RTCSTAD register, 17-20 RTG bit field in GPTMR0CTL register, 14-4 in GPTMR1CTL register, 14-10 RTS bit field, 18-20 RTSx signal, 18-19, 18-20 RW bit field, 13-5 rxdackx internal signal, 11-8, 11-9 RXDRQx Channel Mapping bit field, 11-8, 11-9 rxdrqx internal signal, 11-8, 11-9, 18-5, 18-15 RXDRQx_CHSEL bit field, 11-8, 11-9 RXTC_DET bit field, 18-4 RXTC_ENB bit field, 18-3 S S_DVSL_TIM bit field, 6-20 S_TGT_ABT bit field, 6-20 S1PICICW1 register, 12-51 S1PICICW2 register, 12-57 S1PICICW3 register, 12-58 S1PICICW4 register, 12-59 S1PICINTMSK register, 12-60 S1PICIR register, 12-49 S1PICISR register, 12-50 S1PICOCW2 register, 12-53 S1PICOCW3 register, 12-55 S2PICICW1 register, 12-39 S2PICICW2 register, 12-45 S2PICICW3 register, 12-46 S2PICICW4 register, 12-47 S2PICINTMSK register, 12-48 S2PICIR register, 12-37 S2PICISR register, 12-38 S2PICOCW2 register, 12-41 S2PICOCW3 register, 12-43 SB bit field, 18-17 SB_ADDR bit field, 7-14 SBCL_CD bit field, 6-22 SBIT_ERR bit field, 7-10 SCASx signal, 7-4, 20-10 SCP Command Port register, 3-8 SCP Data Port register, 3-7 SCP Reset Detect bit field, 3-5 SCP_CMD bit field, 3-8 SCP_DATA bit field, 3-7 SCP_RST_DET bit field, 3-5 SCPCMD register, 3-8 SCPDATA register, 3-7 SCRATCH bit field, 18-25 Scratch Bits bit field, 18-25 SCS_DRIVE bit field, 20-10 SCSx signal, 20-10 SD_RST_DET bit field, 3-6 SDQM_DRIVE bit field, 20-10 SDQMx signal, 20-10 ElanTMSC520 Microcontroller Register Set Manual Index-17 Index SDRAM Bank 0-3 Ending Address register, 7-7 SDRAM Bank Configuration register, 7-5 SDRAM Buffer Control register, 8-2 SDRAM CAS Latency bit field, 7-4 SDRAM Control register, 7-2 SDRAM controller MMCR registers (table), 7-1 SDRAM ECC Interrupt Mapping bit field, 12-20 SDRAM Operation Mode Select bit field, 7-3 SDRAM RAS Precharge Delay bit field, 7-4 SDRAM RAS-to-CAS Delay bit field, 7-4 SDRAM Refresh Request Speed bit field, 7-2 SDRAM Timing Control register, 7-4 SECOND bit field, 17-4 Select Counter x bit field, 13-11 Select ICW1 bit field in MPICICW1 register, 12-26 in MPICOCW2 register, 12-28 SERR Enable bit field, 6-20 SERR signal in HBMSTIRQCTL register, 6-9, 6-10 in PCISTACMD register, 6-13, 6-19, 6-20 SERR_ENB bit field, 6-20 SET bit field, 17-16 Set Break Enable bit field, 18-17 SFNM bit field in MPICICW4 register, 12-35 in S1PICICW4 register, 12-59 in S2PICICW4 register, 12-47 SGL_INT_ENB bit field, 7-9 SIG_SERR bit field, 6-19 Signal Width for (GPIOWR and GPMEMWR) bit field, 10-12 for GPALE bit field, 10-14 for GPIORD and GPMEMRD bit field, 10-10 for the GP Bus Chip Selects bit field, 10-8 Signaled System Error bit field, 6-19 Signaled Target Abort bit field, 6-20 Single PIC bit field in MPICICW1 register, 12-26 in S1PICICW1 register, 12-52 in S2PICICW1 register, 12-40 Single-bit ECC Error bit field, 7-10 SL bit in R_SL_EOI bit field, 12-28, 12-41, 12-53 SL1PICMODE register, 12-8 SL2PICMODE register, 12-9 Slave 1 PIC I/O Port 00A0h access summary (table), 12-52 Initialization Control Word 1 register, 12-51 Initialization Control Word 2 register, 12-57 Initialization Control Word 3 register, 12-58 Initialization Control Word 4 register, 12-59 In-Service register, 12-50 Interrupt Mask register, 12-60 Interrupt Mode register, 12-8 Interrupt Request register, 12-49 Operation Control Word 2 register, 12-53 Operation Control Word 3 register, 12-55 Slave 2 PIC I/O Port 0024h access summary (table), 12-40 Initialization Control Word 1 register, 12-39 Initialization Control Word 2 register, 12-45 Initialization Control Word 3 register, 12-46 Initialization Control Word 4 register, 12-47 In-Service register, 12-38 Interrupt Mask register, 12-48 Interrupt Mode register, 12-9 Interrupt Request register, 12-37 Operation Control Word 2 register, 12-41 Operation Control Word 3 register, 12-43 Slave DMA. See also DMA, GP-DMA, Master DMA. Slave DMA Channel 0 Memory Address register, 11-42 Page register, 11-69 Transfer Count register, 11-43 Slave DMA Channel 0-3 Control register, 11-51 Mask register, 11-54 Mode register, 11-55 Status register, 11-50 Slave DMA Channel 1 Memory Address register, 11-44 Page register, 11-65 Transfer Count register, 11-45 Slave DMA Channel 2 Memory Address register, 11-46 Page register, 11-63 Transfer Count register, 11-47 Slave DMA Channel 3 Memory Address register, 11-48 Page register, 11-64 Transfer Count register, 11-49 Slave DMA Clear Byte Pointer register, 11-57 Slave DMA Controller Reset register, 11-58 Slave DMA Controller Temporary register, 11-59 Slave DMA General Mask register, 11-61 Slave DMA Mask Reset register, 11-60 Slave Software DRQ(n) Request register, 11-53 Index-18 ElanTMSC520 Microcontroller Register Set Manual Index Slave x PIC Channel x Interrupt Mode bit field in SL1PICMODE register, 12-8 in SL2PICMODE register, 12-9 Global Interrupt Mode Enable bit field, 12-4, 12-5 ID 2-0 bit field in S1PICICW3 register, 12-58 in S2PICICW3 register, 12-46 SLAVE_CBP bit field, 11-57 SLAVE_MSK_RST bit field, 11-60 SLAVE_RST bit field, 11-58 SLAVE_TMP bit field, 11-59 SLCT_ICW1 bit field in MPICICW1 register, 12-26 in MPICOCW2 register, 12-28 in MPICOCW3 register, 12-30 in S1PICICW1 register, 12-51 in S1PICOCW2 register, 12-53 in S1PICOCW3 register, 12-55 in S2PICICW1 register, 12-39 in S2PICOCW2 register, 12-41 in S2PICOCW3 register, 12-43 SLDMACBP register, 11-57 SLDMACTL register, 11-51 SLDMAGENMSK register, 11-61 SLDMAMODE register, 11-55 SLDMAMSK register, 11-54 SLDMAMSKRST register, 11-60 SLDMARST register, 11-58 SLDMASTA register, 11-50 SLDMASWREQ register, 11-53 SLDMATMP register, 11-59 SMM bit field in MPICOCW3 register, 12-30 in S1PICOCW3 register, 12-55 in S2PICOCW3 register, 12-43 SNGL bit field in MPICICW1 register, 12-26 in S1PICICW1 register, 12-52 in S2PICICW1 register, 12-40 Software DMA Request bit field in MSTDMASWREQ register, 11-89 in SLDMASWREQ register, 11-53 Software GP Bus Reset bit field, 3-3 Software Interrupt 16-1 Control register, 12-10 22-17/NMI Control register, 12-13 Software NMI Source bit field, 12-13 Software System Reset bit field, 3-4 Software Timer Configuration register, 15-4 Microsecond Count register, 15-3 Millisecond Count register, 15-2 MMCR registers (table), 15-1 SOUTx signal, 18-17, 18-19 SP bit field, 18-17 special cycle recognition bit not implemented, 6-21 Special Fully Nested Mode Enable bit field in MPICICW4 register, 12-35 in S1PICICW4 register, 12-59 in S2PICICW4 register, 12-47 Special Mask Mode bit field in MPICOCW3 register, 12-30 in S1PICOCW3 register, 12-55 in S2PICOCW3 register, 12-43 Specific EOI Level Select bit field in MPICOCW2 register, 12-28 in S1PICOCW2 register, 12-54 in S2PICOCW2 register, 12-41 SRASx signal, 7-4, 20-10 SRCW_DRIVE bit field, 20-10 sreset internal signal, 3-8, 3-9 SSI Busy bit field, 19-6 SSI Clock Speed Select bit field, 19-2 selections (table), 19-2 SSI Command register, 19-5 SSI Control register, 19-2 SSI Data IN bit field, 19-7 SSI Data Out bit field, 19-4 SSI Interrupt Mapping register, 12-21 SSI Inverted Clock Mode Enable bit field, 19-3 SSI Inverted Phase Mode Enable bit field, 19-3 SSI MMCR registers (table), 19-1 SSI Most Significant Bit First Mode Enable bit field, 19-3 SSI Receive register, 19-7 SSI Status register, 19-6 SSI Transaction Complete Interrupt bit field, 19-6 SSI Transmit register, 19-4 SSI_CLK signal, 19-3, 19-6 in SSICTL register, 19-2, 19-3 in SSISTA register, 19-6 SSI_DI signal in SSICTL register, 19-3 in SSIRCV register, 19-7 SSI_DO signal in SSICTL register, 19-3 in SSIXMIT register, 19-4 SSICMD register, 19-5 SSICTL register, 19-2 SSIMAP register, 12-21 ElanTMSC520 Microcontroller Register Set Manual Index-19 Index SSIRCV register, 19-7 SSISTA register, 19-6 SSIXMIT register, 19-4 Start Address bit field, 2-9 Status Register Select bit field in MPICOCW3 register, 12-30 in S1PICOCW3 register, 12-55 in S2PICOCW3 register, 12-43 Status/Command register, 6-19 Stick Parity Enable bit field, 18-17 Stop Bits bit field, 18-18 STP bit field, 18-18 Sub Class Code bit field, 6-22 SUB_DLY bit field in BOOTCSCTL register, 9-2 in ROMCS1CTL register, 9-4 in ROMCS2CTL register, 9-6 support, iii SW_Px_TRIG bit field in SWINT16_1 register, 12-10, 12-11, 12-12 in SWINT22_17 register, 12-13, 12-14 SWEx signal, 20-10 SWINT16_1 register, 12-10 SWINT22_17 register, 12-13 SWT Microsecond Count bit field, 15-3 SWTMRCFG register, 15-4 SWTMRMICRO register, 15-3 SWTMRMILLI register, 15-2 Sx bit field, 12-33, 12-34 Sx_GINT_MODE bit field, 12-4, 12-5 SYS_RST bit field, 3-4 SYSARBCTL register, 5-2 SYSARBMENB register, 5-4 SYSCTLA register, 3-9 SYSCTLB register, 13-13 SYSINFO register, 3-2 system address mapping MMCR registers (table), 2-1 System Arbiter Concurrent Mode Enable bit field, 5-2 Control register, 5-2 Master Enable register, 5-4 MMCR registers (table), 5-1 System Board Information register, 3-2 System Control Port A register, 3-9 System Control Port B register, 13-13 System Control Processor Data bit field, 3-7 SZ_ST_ADR bit field, 2-8 T T_APER_IRQ_ENB bit field, 6-5 T_APER_IRQ_SEL bit field, 6-5 T_APER_IRQ_STA bit field, 6-8 T_DLYTO_IRQ_ENB bit field, 6-5 T_DLYTO_IRQ_SEL bit field, 6-5 T_DLYTO_IRQ_STA bit field, 6-7 T_DLYTR_ENB bit field, 6-4 T_DPER_IRQ_ENB bit field, 6-6 T_DPER_IRQ_SEL bit field, 6-5 T_DPER_IRQ_STA bit field, 6-8 T_IRQ_ID bit field, 6-7 T_PURGE_RD_ENB bit field, 6-3 T7-T3 bit field in MPICICW2 register, 12-32 in S1PICICW2 register, 12-57 in S2PICICW2 register, 12-45 Target Address Parity Interrupt Enable bit field, 6-5 Select bit field, 6-5 Status bit field, 6-8 TARGET bit field, 2-6 Target Data Parity Interrupt Enable bit field, 6-6 Select bit field, 6-5 Status bit field, 6-8 Target Delayed Transaction Time-Out Interrupt Enable bit field, 6-5 Select bit field, 6-5 Status bit field, 6-7 Target FIFO Purge Enable bit field, 6-3 Target Interrupt Identification bit field, 6-7 Target of the PARx Window bit field, 2-6 TC_INT bit field, 19-6 TC_INT_ENB bit field, 19-2 TCx bit field in MSTDMASTA register, 11-86 in SLDMASTA register, 11-50 technical support, iii TEMT bit field, 18-21 TERI bit field, 18-23 TF_CLR bit field in UARTxFCR register, 18-15 in UARTxFCRSHAD register, 18-5 third-party support, iii THR bit field, 18-7 THRE bit field, 18-21 Timer 2 Gate Input Control bit field, 13-13 Index-20 ElanTMSC520 Microcontroller Register Set Manual Index TMRIN0 signal Function Select bit field, 20-7 in GPTMR0CNT register, 14-6 in GPTMR0CTL register, 14-4, 14-5 TMRIN1 signal Function Select bit field, 20-7 in GPTMR1CNT register, 14-12 in GPTMR1CTL register, 14-10, 14-11 TMROUT0 signal Function Select bit field, 20-7 in GPTMR0CTL register, 14-3, 14-5 TMROUT1 signal Function Select bit field, 20-7 in GPTMR1CTL register, 14-9, 14-11 Trailing Edge Ring Indicator bit field, 18-23 Transaction Complete Interrupt Enable bit field, 19-2 Transfer Mode bit field in MSTDMAMODE register, 11-91 in SLDMAMODE register, 11-55 Transmit Holding Register (16450-Compatible Mode) or Transmitter FIFO (16550-Compatible Mode) Empty bit field, 18-21 Transmit/Receive Word Length Select bit field, 18-18 Transmitter Empty Indicator bit field, 18-21 Transmitter FIFO Clear bit field in UARTxFCR register, 18-15 in UARTxFCRSHAD register, 18-5 TRNMOD bit field in MSTDMAMODE register, 11-91 in SLDMAMODE register, 11-55 Tx_INT_STA bit field in GPTMRSTA register, 14-2 txdackx internal signal, 11-8 TXDRQx Channel Mapping bit field, 11-8 txdrqx internal signal, 11-8, 18-5, 18-15 TXDRQx_CHSEL bit field, 11-8 TXTC_DET bit field, 18-4 TXTC_ENB bit field, 18-3 Interrupt Enable register, 18-11 Interrupt ID register, 18-12 interrupt identification and priority (table), 18-13 Interrupt Mapping register, 12-21 interrupt programming summary (table), 18-14 Line Control register, 18-17 Line Status register, 18-21 MMCR registers (table), 18-1 Modem Control register, 18-19 Modem Status register, 18-23 Receive Buffer bit field, 18-8 Receive Buffer register, 18-8 Receive TC Detected bit field, 18-4 Receive TC Interrupt Enable bit field, 18-3 Scratch Pad register, 18-25 Transmit Holding register, 18-7 Transmit Holding Register bit field, 18-7 Transmit TC Detected bit field, 18-4 Transmit TC Interrupt Enable bit field, 18-3 UART1BCDH register, 18-10 UART1BCDL register, 18-9 UART1CTL register, 18-3 UART1FCR register, 18-15 UART1FCRSHAD register, 18-5 UART1INTENB register, 18-11 UART1INTID register, 18-12 UART1LCR register, 18-17 UART1LSR register, 18-21 UART1MAP register, 12-21 UART1MCR register, 18-19 UART1MSR register, 18-23 UART1RBR register, 18-8 UART1SCRATCH register, 18-25 UART1STA register, 18-4 UART1THR register, 18-7 UART2BCDH register, 18-10 UART2BCDL register, 18-9 UART2CTL register, 18-3 UART2FCR register, 18-15 UART2FCRSHAD register, 18-5 UART2INTENB register, 18-11 UART2INTID register, 18-12 UART2LCR register, 18-17 UART2LSR register, 18-21 UART2MAP register, 12-21 UART2MCR register, 18-19 UART2MSR register, 18-23 UART2RBR register, 18-8 UART2SCRATCH register, 18-25 UART2STA register, 18-4 UART2THR register, 18-7 UARTx_DIS bit field, 2-3 U UART x Baud Clock Divisor Latch bit field in UARTxBCDH register, 18-10 in UARTxBCDL register, 18-9 Baud Clock Divisor Latch LSB register, 18-9 Baud Clock Divisor Latch MSB register, 18-10 Clock Source Enable bit field, 18-3 direct-mapped registers (table), 18-1 Disable bit field, 2-3 FIFO Control register, 18-15 FIFO Control Shadow register, 18-5 General Control register, 18-3 General Status register, 18-4 ElanTMSC520 Microcontroller Register Set Manual Index-21 Index UDF Supported bit field, 6-20 UDFS bit field, 6-20 UIP bit field, 17-14 UPD_INT_ENB bit field, 17-17 UPD_INT_FLG bit field, 17-19 Update in Progress bit field, 17-14 Update-Ended Interrupt Enable bit field, 17-17 Flag bit field, 17-19 URL AMD, iii literature ordering, iii US_CNT bit field, 15-3 WPV_WINDOW bit field, 2-4 WPVMAP register, 12-21 WPVSTA register, 2-4 Write Buffer Enable bit field, 8-3 Flush bit field, 8-3 Test Mode Enable bit field, 7-2 Watermark bit field, 8-2 write buffer and read buffer MMCR registers (table), 8-1 Write Selection Control bit field in MSTDMACTL register, 11-87 in SLDMACTL register, 11-51 Write-Protect Violation Interrupt Enable bit field, 2-2 Interrupt Status bit field, 2-4 Master bit field, 2-4 Window Number bit field, 2-4 Write-Protect Violation Interrupt Mapping register, 12-21 Write-Protect Violation Status register, 2-4 WRST_ENB bit field, 16-2 WRTSEL bit field in MSTDMACTL register, 11-87 in SLDMACTL register, 11-51 www.amd.com, iii V Valid RAM and Time bit field, 17-20 VDR_ID bit field, 6-18 Vendor ID bit field, 6-18 VGA palette snoop enable bit not implemented, 6-21 W wait cycle control bit not implemented, 6-21 Watchdog Timer Control register, 16-2 Count High register, 16-5 Count Low register, 16-4 Enable bit field, 16-2 exponent selections (table), 16-3 Interrupt Mapping register, 12-21 MMCR registers (table), 16-1 Reset Detect bit field, 3-5 Reset Enable bit field, 16-2 WB_ENB bit field, 8-3 WB_FLUSH bit field, 8-3 WB_TST_ENB bit field, 7-2 WB_WM bit field, 8-2 WBMSTRx signal, 7-2 WDT_RST_DET bit field, 3-5 WDTMAP register, 12-21 WDTMRCNTH register, 16-5 WDTMRCNTL register, 16-4 WDTMRCTL register, 16-2 WIDTH bit field in BOOTCSCTL register, 9-2 in ROMCS1CTL register, 9-4 in ROMCS2CTL register, 9-6 WLS bit field, 18-18 WPV_INT_ENB bit field, 2-2 WPV_MSTR bit field, 2-4 WPV_STA bit field, 2-4 Index-22 X XTAL_FREQ bit field, 15-4 Y YEAR bit field, 17-13 ElanTMSC520 Microcontroller Register Set Manual |
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